[llvm] r299816 - AMDGPU: Actually write nops for writeNopData

[Matt Arsenault via llvm-commits]

Author: arsenm
Date: Sat Apr  8 16:28:38 2017
New Revision: 299816

URL: http://llvm.org/viewvc/llvm-project?rev=299816&view=rev
Log:
AMDGPU: Actually write nops for writeNopData

Before this was just writing 0s, which ends up looking like a
v_cndmask_b32 v0, s0, v0, vcc. Write out an encoded s_nop instead.

Added:
    llvm/trunk/test/CodeGen/AMDGPU/nop-data.ll
Modified:
    llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp

Modified: llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp?rev=299816&r1=299815&r2=299816&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp Sat Apr  8 16:28:38 2017
@@ -164,7 +164,20 @@ const MCFixupKindInfo &AMDGPUAsmBackend:
 }
 
 bool AMDGPUAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
-  OW->WriteZeros(Count);
+  // If the count is not 4-byte aligned, we must be writing data into the text
+  // section (otherwise we have unaligned instructions, and thus have far
+  // bigger problems), so just write zeros instead.
+  OW->WriteZeros(Count % 4);
+
+  // We are properly aligned, so write NOPs as requested.
+  Count /= 4;
+
+  // FIXME: R600 support.
+  // s_nop 0
+  const uint32_t Encoded_S_NOP_0 = 0xbf800000;
+
+  for (uint64_t I = 0; I != Count; ++I)
+    OW->write32(Encoded_S_NOP_0);
 
   return true;
 }

Added: llvm/trunk/test/CodeGen/AMDGPU/nop-data.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/nop-data.ll?rev=299816&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/nop-data.ll (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/nop-data.ll Sat Apr  8 16:28:38 2017
@@ -0,0 +1,87 @@
+; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -filetype=obj < %s | llvm-objdump -d - -mcpu=fiji | FileCheck %s
+
+; CHECK: kernel0:
+; CHECK-NEXT: s_endpgm
+define amdgpu_kernel void @kernel0() align 256 {
+entry:
+  ret void
+}
+
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: s_nop 0
+
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: s_nop 0
+
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: s_nop 0
+
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: s_nop 0
+
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: s_nop 0
+
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: s_nop 0
+
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: s_nop 0
+
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: s_nop 0  // 0000000001FC: BF800000
+
+; CHECK-NEXT: {{^$}}
+; CHECK-NEXT: kernel1:
+; CHECK-NEXT: s_endpgm
+define amdgpu_kernel void @kernel1(i32 addrspace(1)* addrspace(2)* %ptr.out) align 256 {
+entry:
+  ret void
+}