[llvm] r299799 - [AArch64] Allow global register asm("x18") or asm("w18") under -ffixed-x18

[Petr Hosek via llvm-commits]

Author: phosek
Date: Fri Apr  7 15:41:58 2017
New Revision: 299799

URL: http://llvm.org/viewvc/llvm-project?rev=299799&view=rev
Log:
[AArch64] Allow global register asm("x18") or asm("w18") under -ffixed-x18

When using -ffixed-x18, the x18 (or w18) register can safely be used
with the "global register variable" GCC extension, but the backend
fails to recognize it.

Patch by Roland McGrath.

Differential Revision: https://reviews.llvm.org/D31793

Added:
    llvm/trunk/test/CodeGen/AArch64/aarch64-named-reg-w18.ll
    llvm/trunk/test/CodeGen/AArch64/aarch64-named-reg-x18.ll
Modified:
    llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp

Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=299799&r1=299798&r2=299799&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp Fri Apr  7 15:41:58 2017
@@ -4510,7 +4510,12 @@ unsigned AArch64TargetLowering::getRegis
                                                   SelectionDAG &DAG) const {
   unsigned Reg = StringSwitch<unsigned>(RegName)
                        .Case("sp", AArch64::SP)
+                       .Case("x18", AArch64::X18)
+                       .Case("w18", AArch64::W18)
                        .Default(0);
+  if ((Reg == AArch64::X18 || Reg == AArch64::W18) &&
+      !Subtarget->isX18Reserved())
+    Reg = 0;
   if (Reg)
     return Reg;
   report_fatal_error(Twine("Invalid register name \""

Added: llvm/trunk/test/CodeGen/AArch64/aarch64-named-reg-w18.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/aarch64-named-reg-w18.ll?rev=299799&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/aarch64-named-reg-w18.ll (added)
+++ llvm/trunk/test/CodeGen/AArch64/aarch64-named-reg-w18.ll Fri Apr  7 15:41:58 2017
@@ -0,0 +1,14 @@
+; RUN: not llc -mtriple=aarch64-fuchsia -o - %s 2>&1 | FileCheck %s --check-prefix=ERROR
+; RUN: llc -mtriple=aarch64-fuchsia -mattr=+reserve-x18 -o - %s
+
+define void @set_w18(i32 %x) {
+entry:
+; FIXME: Include an allocatable-specific error message
+; ERROR: Invalid register name "w18".
+  tail call void @llvm.write_register.i32(metadata !0, i32 %x)
+  ret void
+}
+
+declare void @llvm.write_register.i32(metadata, i32) nounwind
+
+!0 = !{!"w18"}

Added: llvm/trunk/test/CodeGen/AArch64/aarch64-named-reg-x18.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/aarch64-named-reg-x18.ll?rev=299799&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/aarch64-named-reg-x18.ll (added)
+++ llvm/trunk/test/CodeGen/AArch64/aarch64-named-reg-x18.ll Fri Apr  7 15:41:58 2017
@@ -0,0 +1,14 @@
+; RUN: not llc -mtriple=aarch64-fuchsia -o - %s 2>&1 | FileCheck %s --check-prefix=ERROR
+; RUN: llc -mtriple=aarch64-fuchsia -mattr=+reserve-x18 -o - %s
+
+define void @set_x18(i64 %x) {
+entry:
+; FIXME: Include an allocatable-specific error message
+; ERROR: Invalid register name "x18".
+  tail call void @llvm.write_register.i64(metadata !0, i64 %x)
+  ret void
+}
+
+declare void @llvm.write_register.i64(metadata, i64) nounwind
+
+!0 = !{!"x18"}