[PATCH] D31754: [X86][MMX] Add fast-isel support for MMX non-temporal writes

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.

Repository:
  rL LLVM

https://reviews.llvm.org/D31754

Files:
  lib/Target/X86/X86FastISel.cpp
  test/CodeGen/X86/fast-isel-nontemporal.ll


Index: test/CodeGen/X86/fast-isel-nontemporal.ll
===================================================================
--- test/CodeGen/X86/fast-isel-nontemporal.ll
+++ test/CodeGen/X86/fast-isel-nontemporal.ll
@@ -100,7 +100,7 @@
 ; ALL:       # BB#0: # %entry
 ; ALL-NEXT:    movq (%rdi), %mm0
 ; ALL-NEXT:    psrlq $3, %mm0
-; ALL-NEXT:    movq %mm0, (%rsi)
+; ALL-NEXT:    movntq %mm0, (%rsi)
 ; ALL-NEXT:    retq
 entry:
   %0 = load x86_mmx, x86_mmx* %a0
Index: lib/Target/X86/X86FastISel.cpp
===================================================================
--- lib/Target/X86/X86FastISel.cpp
+++ lib/Target/X86/X86FastISel.cpp
@@ -528,6 +528,7 @@
 bool X86FastISel::X86FastEmitStore(EVT VT, unsigned ValReg, bool ValIsKill,
                                    X86AddressMode &AM,
                                    MachineMemOperand *MMO, bool Aligned) {
+  bool HasSSE1 = Subtarget->hasSSE1();
   bool HasSSE2 = Subtarget->hasSSE2();
   bool HasSSE4A = Subtarget->hasSSE4A();
   bool HasAVX = Subtarget->hasAVX();
@@ -588,6 +589,9 @@
     } else
       Opc = X86::ST_Fp64m;
     break;
+  case MVT::x86mmx:
+    Opc = (IsNonTemporal && HasSSE1) ? X86::MMX_MOVNTQmr : X86::MMX_MOVQ64mr;
+    break;
   case MVT::v4f32:
     if (Aligned) {
       if (IsNonTemporal)


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