[llvm] r299637 - [globalisel][tablegen] Move <Target>InstructionSelector declarations to anonymous namespaces
Daniel Sanders via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 6 02:49:34 PDT 2017
Author: dsanders
Date: Thu Apr 6 04:49:34 2017
New Revision: 299637
URL: http://llvm.org/viewvc/llvm-project?rev=299637&view=rev
Log:
[globalisel][tablegen] Move <Target>InstructionSelector declarations to anonymous namespaces
Summary: This resolves the issue of tablegen-erated includes in the headers for non-GlobalISel builds in a simpler way than before.
Reviewers: qcolombet, ab
Reviewed By: ab
Subscribers: igorb, ab, mgorny, dberris, rovka, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D30998
Removed:
llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.h
llvm/trunk/lib/Target/X86/X86InstructionSelector.h
Modified:
llvm/trunk/lib/Target/AArch64/AArch64.h
llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp
llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp
llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.h
llvm/trunk/lib/Target/X86/X86.h
llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp
llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
llvm/trunk/lib/Target/X86/X86TargetMachine.h
Modified: llvm/trunk/lib/Target/AArch64/AArch64.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64.h?rev=299637&r1=299636&r2=299637&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64.h (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64.h Thu Apr 6 04:49:34 2017
@@ -22,8 +22,11 @@
namespace llvm {
+class AArch64RegisterBankInfo;
+class AArch64Subtarget;
class AArch64TargetMachine;
class FunctionPass;
+class InstructionSelector;
class MachineFunctionPass;
FunctionPass *createAArch64DeadRegisterDefinitions();
@@ -45,6 +48,9 @@ FunctionPass *createAArch64A53Fix835769(
FunctionPass *createAArch64CleanupLocalDynamicTLSPass();
FunctionPass *createAArch64CollectLOHPass();
+InstructionSelector *
+createAArch64InstructionSelector(const AArch64TargetMachine &,
+ AArch64Subtarget &, AArch64RegisterBankInfo &);
void initializeAArch64A53Fix835769Pass(PassRegistry&);
void initializeAArch64A57FPLoadBalancingPass(PassRegistry&);
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp?rev=299637&r1=299636&r2=299637&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp Thu Apr 6 04:49:34 2017
@@ -12,7 +12,6 @@
/// \todo This should be generated by TableGen.
//===----------------------------------------------------------------------===//
-#include "AArch64InstructionSelector.h"
#include "AArch64InstrInfo.h"
#include "AArch64MachineFunctionInfo.h"
#include "AArch64RegisterBankInfo.h"
@@ -20,10 +19,12 @@
#include "AArch64Subtarget.h"
#include "AArch64TargetMachine.h"
#include "MCTargetDesc/AArch64AddressingModes.h"
+#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/IR/Type.h"
#include "llvm/Support/Debug.h"
@@ -37,6 +38,47 @@ using namespace llvm;
#error "You shouldn't build this"
#endif
+namespace {
+
+class AArch64InstructionSelector : public InstructionSelector {
+public:
+ AArch64InstructionSelector(const AArch64TargetMachine &TM,
+ const AArch64Subtarget &STI,
+ const AArch64RegisterBankInfo &RBI);
+
+ bool select(MachineInstr &I) const override;
+
+private:
+ /// tblgen-erated 'select' implementation, used as the initial selector for
+ /// the patterns that don't require complex C++.
+ bool selectImpl(MachineInstr &I) const;
+
+ bool selectVaStartAAPCS(MachineInstr &I, MachineFunction &MF,
+ MachineRegisterInfo &MRI) const;
+ bool selectVaStartDarwin(MachineInstr &I, MachineFunction &MF,
+ MachineRegisterInfo &MRI) const;
+
+ bool selectCompareBranch(MachineInstr &I, MachineFunction &MF,
+ MachineRegisterInfo &MRI) const;
+
+ bool selectArithImmed(MachineOperand &Root, MachineOperand &Result1,
+ MachineOperand &Result2) const;
+
+ const AArch64TargetMachine &TM;
+ const AArch64Subtarget &STI;
+ const AArch64InstrInfo &TII;
+ const AArch64RegisterInfo &TRI;
+ const AArch64RegisterBankInfo &RBI;
+
+// We declare the temporaries used by selectImpl() in the class to minimize the
+// cost of constructing placeholder values.
+#define GET_GLOBALISEL_TEMPORARIES_DECL
+#include "AArch64GenGlobalISel.inc"
+#undef GET_GLOBALISEL_TEMPORARIES_DECL
+};
+
+} // end anonymous namespace
+
#define GET_GLOBALISEL_IMPL
#include "AArch64GenGlobalISel.inc"
#undef GET_GLOBALISEL_IMPL
@@ -1315,3 +1357,12 @@ bool AArch64InstructionSelector::selectA
Result2.clearParent();
return true;
}
+
+namespace llvm {
+InstructionSelector *
+createAArch64InstructionSelector(const AArch64TargetMachine &TM,
+ AArch64Subtarget &Subtarget,
+ AArch64RegisterBankInfo &RBI) {
+ return new AArch64InstructionSelector(TM, Subtarget, RBI);
+}
+}
Removed: llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.h?rev=299636&view=auto
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.h (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.h (removed)
@@ -1,74 +0,0 @@
-//===- AArch64InstructionSelector --------------------------------*- C++ -*-==//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-/// \file
-/// This file declares the targeting of the InstructionSelector class for
-/// AArch64.
-//===----------------------------------------------------------------------===//
-
-#ifdef LLVM_BUILD_GLOBAL_ISEL
-
-#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64INSTRUCTIONSELECTOR_H
-#define LLVM_LIB_TARGET_AARCH64_AARCH64INSTRUCTIONSELECTOR_H
-
-#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
-#include "llvm/CodeGen/MachineOperand.h"
-
-namespace llvm {
-
-class AArch64InstrInfo;
-class AArch64RegisterBankInfo;
-class AArch64RegisterInfo;
-class AArch64Subtarget;
-class AArch64TargetMachine;
-class MachineOperand;
-
-class MachineFunction;
-class MachineRegisterInfo;
-
-class AArch64InstructionSelector : public InstructionSelector {
-public:
- AArch64InstructionSelector(const AArch64TargetMachine &TM,
- const AArch64Subtarget &STI,
- const AArch64RegisterBankInfo &RBI);
-
- bool select(MachineInstr &I) const override;
-
-private:
- /// tblgen-erated 'select' implementation, used as the initial selector for
- /// the patterns that don't require complex C++.
- bool selectImpl(MachineInstr &I) const;
-
- bool selectVaStartAAPCS(MachineInstr &I, MachineFunction &MF,
- MachineRegisterInfo &MRI) const;
- bool selectVaStartDarwin(MachineInstr &I, MachineFunction &MF,
- MachineRegisterInfo &MRI) const;
-
- bool selectCompareBranch(MachineInstr &I, MachineFunction &MF,
- MachineRegisterInfo &MRI) const;
-
- bool selectArithImmed(MachineOperand &Root, MachineOperand &Result1,
- MachineOperand &Result2) const;
-
- const AArch64TargetMachine &TM;
- const AArch64Subtarget &STI;
- const AArch64InstrInfo &TII;
- const AArch64RegisterInfo &TRI;
- const AArch64RegisterBankInfo &RBI;
-
-// We declare the temporaries used by selectImpl() in the class to minimize the
-// cost of constructing placeholder values.
-#define GET_GLOBALISEL_TEMPORARIES_DECL
-#include "AArch64GenGlobalISel.inc"
-#undef GET_GLOBALISEL_TEMPORARIES_DECL
-};
-
-} // end namespace llvm
-
-#endif // LLVM_LIB_TARGET_AARCH64_AARCH64INSTRUCTIONSELECTOR_H
-#endif // LLVM_BUILD_GLOBAL_ISEL
Modified: llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp?rev=299637&r1=299636&r2=299637&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp Thu Apr 6 04:49:34 2017
@@ -12,7 +12,6 @@
#include "AArch64.h"
#include "AArch64CallLowering.h"
-#include "AArch64InstructionSelector.h"
#include "AArch64LegalizerInfo.h"
#include "AArch64MacroFusion.h"
#ifdef LLVM_BUILD_GLOBAL_ISEL
@@ -286,7 +285,8 @@ AArch64TargetMachine::getSubtargetImpl(c
// FIXME: At this point, we can't rely on Subtarget having RBI.
// It's awkward to mix passing RBI and the Subtarget; should we pass
// TII/TRI as well?
- GISel->InstSelector.reset(new AArch64InstructionSelector(*this, *I, *RBI));
+ GISel->InstSelector.reset(
+ createAArch64InstructionSelector(*this, *I, *RBI));
GISel->RegBankInfo.reset(RBI);
#endif
Modified: llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.h?rev=299637&r1=299636&r2=299637&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.h (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.h Thu Apr 6 04:49:34 2017
@@ -21,6 +21,8 @@
namespace llvm {
+class AArch64RegisterBankInfo;
+
class AArch64TargetMachine : public LLVMTargetMachine {
protected:
std::unique_ptr<TargetLoweringObjectFile> TLOF;
Modified: llvm/trunk/lib/Target/X86/X86.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.h?rev=299637&r1=299636&r2=299637&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86.h (original)
+++ llvm/trunk/lib/Target/X86/X86.h Thu Apr 6 04:49:34 2017
@@ -21,7 +21,10 @@ namespace llvm {
class FunctionPass;
class ImmutablePass;
+class InstructionSelector;
class PassRegistry;
+class X86RegisterBankInfo;
+class X86Subtarget;
class X86TargetMachine;
/// This pass converts a legalized DAG into a X86-specific DAG, ready for
@@ -92,6 +95,9 @@ void initializeFixupBWInstPassPass(PassR
/// encoding when possible in order to reduce code size.
FunctionPass *createX86EvexToVexInsts();
+InstructionSelector *createX86InstructionSelector(X86Subtarget &,
+ X86RegisterBankInfo &);
+
void initializeEvexToVexInstPassPass(PassRegistry &);
} // End llvm namespace
Modified: llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp?rev=299637&r1=299636&r2=299637&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp Thu Apr 6 04:49:34 2017
@@ -12,7 +12,6 @@
/// \todo This should be generated by TableGen.
//===----------------------------------------------------------------------===//
-#include "X86InstructionSelector.h"
#include "X86InstrBuilder.h"
#include "X86InstrInfo.h"
#include "X86RegisterBankInfo.h"
@@ -23,7 +22,9 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
#include "llvm/IR/Type.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
@@ -36,6 +37,47 @@ using namespace llvm;
#error "You shouldn't build this"
#endif
+namespace {
+
+class X86InstructionSelector : public InstructionSelector {
+public:
+ X86InstructionSelector(const X86Subtarget &STI,
+ const X86RegisterBankInfo &RBI);
+
+ bool select(MachineInstr &I) const override;
+
+private:
+ /// tblgen-erated 'select' implementation, used as the initial selector for
+ /// the patterns that don't require complex C++.
+ bool selectImpl(MachineInstr &I) const;
+
+ // TODO: remove after selectImpl support pattern with a predicate.
+ unsigned getFAddOp(LLT &Ty, const RegisterBank &RB) const;
+ unsigned getFSubOp(LLT &Ty, const RegisterBank &RB) const;
+ unsigned getAddOp(LLT &Ty, const RegisterBank &RB) const;
+ unsigned getSubOp(LLT &Ty, const RegisterBank &RB) const;
+ unsigned getLoadStoreOp(LLT &Ty, const RegisterBank &RB, unsigned Opc,
+ uint64_t Alignment) const;
+
+ bool selectBinaryOp(MachineInstr &I, MachineRegisterInfo &MRI,
+ MachineFunction &MF) const;
+ bool selectLoadStoreOp(MachineInstr &I, MachineRegisterInfo &MRI,
+ MachineFunction &MF) const;
+ bool selectFrameIndex(MachineInstr &I, MachineRegisterInfo &MRI,
+ MachineFunction &MF) const;
+
+ const X86Subtarget &STI;
+ const X86InstrInfo &TII;
+ const X86RegisterInfo &TRI;
+ const X86RegisterBankInfo &RBI;
+
+#define GET_GLOBALISEL_TEMPORARIES_DECL
+#include "X86GenGlobalISel.inc"
+#undef GET_GLOBALISEL_TEMPORARIES_DECL
+};
+
+} // end anonymous namespace
+
#define GET_GLOBALISEL_IMPL
#include "X86GenGlobalISel.inc"
#undef GET_GLOBALISEL_IMPL
@@ -415,3 +457,9 @@ bool X86InstructionSelector::selectFrame
return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
}
+
+InstructionSelector *
+llvm::createX86InstructionSelector(X86Subtarget &Subtarget,
+ X86RegisterBankInfo &RBI) {
+ return new X86InstructionSelector(Subtarget, RBI);
+}
Removed: llvm/trunk/lib/Target/X86/X86InstructionSelector.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstructionSelector.h?rev=299636&view=auto
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstructionSelector.h (original)
+++ llvm/trunk/lib/Target/X86/X86InstructionSelector.h (removed)
@@ -1,72 +0,0 @@
-//===- X86InstructionSelector --------------------------------*- C++ -*-==//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-/// \file
-/// This file declares the targeting of the InstructionSelector class for X86.
-//===----------------------------------------------------------------------===//
-
-#ifdef LLVM_BUILD_GLOBAL_ISEL
-#ifndef LLVM_LIB_TARGET_X86_X86INSTRUCTIONSELECTOR_H
-#define LLVM_LIB_TARGET_X86_X86INSTRUCTIONSELECTOR_H
-
-#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
-#include "llvm/CodeGen/MachineOperand.h"
-
-namespace llvm {
-
-class X86InstrInfo;
-class X86RegisterBankInfo;
-class X86RegisterInfo;
-class X86Subtarget;
-class X86TargetMachine;
-class LLT;
-class RegisterBank;
-class MachineRegisterInfo;
-class MachineFunction;
-
-class X86InstructionSelector : public InstructionSelector {
-public:
- X86InstructionSelector(const X86Subtarget &STI,
- const X86RegisterBankInfo &RBI);
-
- bool select(MachineInstr &I) const override;
-
-private:
- /// tblgen-erated 'select' implementation, used as the initial selector for
- /// the patterns that don't require complex C++.
- bool selectImpl(MachineInstr &I) const;
-
- // TODO: remove after selectImpl support pattern with a predicate.
- unsigned getFAddOp(LLT &Ty, const RegisterBank &RB) const;
- unsigned getFSubOp(LLT &Ty, const RegisterBank &RB) const;
- unsigned getAddOp(LLT &Ty, const RegisterBank &RB) const;
- unsigned getSubOp(LLT &Ty, const RegisterBank &RB) const;
- unsigned getLoadStoreOp(LLT &Ty, const RegisterBank &RB, unsigned Opc,
- uint64_t Alignment) const;
-
- bool selectBinaryOp(MachineInstr &I, MachineRegisterInfo &MRI,
- MachineFunction &MF) const;
- bool selectLoadStoreOp(MachineInstr &I, MachineRegisterInfo &MRI,
- MachineFunction &MF) const;
- bool selectFrameIndex(MachineInstr &I, MachineRegisterInfo &MRI,
- MachineFunction &MF) const;
-
- const X86Subtarget &STI;
- const X86InstrInfo &TII;
- const X86RegisterInfo &TRI;
- const X86RegisterBankInfo &RBI;
-
-#define GET_GLOBALISEL_TEMPORARIES_DECL
-#include "X86GenGlobalISel.inc"
-#undef GET_GLOBALISEL_TEMPORARIES_DECL
-};
-
-} // end namespace llvm
-
-#endif // LLVM_LIB_TARGET_X86_X86INSTRUCTIONSELECTOR_H
-#endif // LLVM_BUILD_GLOBAL_ISEL
Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=299637&r1=299636&r2=299637&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86TargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Thu Apr 6 04:49:34 2017
@@ -15,7 +15,6 @@
#include "X86.h"
#include "X86CallLowering.h"
#include "X86LegalizerInfo.h"
-#include "X86InstructionSelector.h"
#ifdef LLVM_BUILD_GLOBAL_ISEL
#include "X86RegisterBankInfo.h"
#endif
@@ -287,8 +286,7 @@ X86TargetMachine::getSubtargetImpl(const
auto *RBI = new X86RegisterBankInfo(*I->getRegisterInfo());
GISel->RegBankInfo.reset(RBI);
- GISel->InstSelector.reset(new X86InstructionSelector(*I, *RBI));
-
+ GISel->InstSelector.reset(createX86InstructionSelector(*I, *RBI));
#endif
I->setGISelAccessor(*GISel);
}
Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.h?rev=299637&r1=299636&r2=299637&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86TargetMachine.h (original)
+++ llvm/trunk/lib/Target/X86/X86TargetMachine.h Thu Apr 6 04:49:34 2017
@@ -25,6 +25,8 @@
namespace llvm {
class StringRef;
+class X86Subtarget;
+class X86RegisterBankInfo;
class X86TargetMachine final : public LLVMTargetMachine {
std::unique_ptr<TargetLoweringObjectFile> TLOF;
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