[PATCH] D31628: Add Explanation of Mips Backend Relocation Principles

Simon Dardis via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Apr 5 08:12:45 PDT 2017


sdardis added a comment.

Another batch of comment inlined. Hopefully they should help tie it all together.

One nit: Mips should be spelt MIPS when referring to the architecture. Referring to it as Mips when highlighting a file or in existing code is fine, it's just an inconsistency that crept in over time.



================
Comment at: lib/Target/Mips/Relocation.txt:12
+factored into common code for generating different address forms and
+is called by the relocation specific lowering function, using
+templated functions. For example:
----------------
relocation model specific lowering function, ...

(Some of MIPS relocations are shared between relocation models, so I think it's clearer to describe those lowering functions as relocation model specific rather than relocation specific)


================
Comment at: lib/Target/Mips/Relocation.txt:31-33
+2. Instruction selection is deferred by using
+MipsISD::{Highest, Higher, Hi, Lo}. For example, in getAddrLocal, the
+pseudo-code generated is:
----------------
Generic address nodes are lowered to some combination of target independent and machine specific SDNodes (MipsISD::{Wrapper, GotHi, Highest, Higher, Hi, Lo}) depending on relocation model, ABI and compilation options.

The choice of specific instructions that are to be used is delegated to ISel which in turn relies on TableGen patterns to choose subtarget specific instructions.  


================
Comment at: lib/Target/Mips/Relocation.txt:42
+
+3. A TableGen multiclass patter "MipsHiLoRelocs is used to define a
+template pattern parameterized over the load and add operations, the
----------------
patter -> pattern.

Missing " after MipsHiLocRelocs.


================
Comment at: lib/Target/Mips/Relocation.txt:43
+3. A TableGen multiclass patter "MipsHiLoRelocs is used to define a
+template pattern parameterized over the load and add operations, the
+zero register, and register class. Here the instantiation of
----------------
I goofed here. This should be "template pattern parameterized over the load upper immediate (lui) instruction and add operations.."


================
Comment at: lib/Target/Mips/Relocation.txt:44
+template pattern parameterized over the load and add operations, the
+zero register, and register class. Here the instantiation of
+MipsHiLoRelocs in MipsInstrInfo.td is used by Mips32.
----------------
Before the 'Here the..', you should note that this specific pattern is used to compute addresses for the static relocation model. (Readers may get confused as you've given the example of PIC address nodes above).


================
Comment at: lib/Target/Mips/Relocation.txt:65
+mode, as guarded by the predicate "SYM_32" and also for a submode of
+LP64 where symbols are assumed to be 32 bits wide.. A similar
+multiclass for Mips64 in LP64 mode is also defined:
----------------
Duplicated '.'


================
Comment at: lib/Target/Mips/Relocation.txt:99
+"TableGen Language Introduction"
+
+4. Instruction definitions are multiply defined to cover the different
----------------
You should note that these patterns are used during the Instruction selection phase to match MipsISD::{Highest, Higher, Hi, Lo} to a specific machine instruction and operands.


================
Comment at: lib/Target/Mips/Relocation.txt:117
+defines two names "LW" and "LW64" with two different register classes,
+but with the same encoding---"LW_RM<0x23>".
----------------
Another example would be LUi/LUi64 (as used in the TableGen patterns above) which loads a 16 bit immediate into bits 31-16 and clears the lower 15 bits. As with lw on MIPS64, the result is sign extended to 64 bits.

(This helps tie 4. into the rest of the doc imho. As it is, I felt point 4 was a bit left of field.)


Repository:
  rL LLVM

https://reviews.llvm.org/D31628





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