[llvm] r299439 - [X86][MS-compatability]Allow named synonymous for MS-assembly operators

[Coby Tayree via llvm-commits]

Author: coby
Date: Tue Apr  4 09:43:23 2017
New Revision: 299439

URL: http://llvm.org/viewvc/llvm-project?rev=299439&view=rev
Log:
[X86][MS-compatability]Allow named synonymous for MS-assembly operators

This patch enhances X86AsmParser's immediate expression parsing abilities, to include a named synonymous for selected binary/unary bitwise operators: {and,shl,shr,or,xor,not}, ultimately achieving better MS-compatability
MASM reference:
https://msdn.microsoft.com/en-us/library/94b6khh4.aspx

Differential Revision: D31277


Modified:
    llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp
    llvm/trunk/test/MC/X86/intel-syntax-bitwise-ops.s

Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=299439&r1=299438&r2=299439&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original)
+++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Tue Apr  4 09:43:23 2017
@@ -717,6 +717,7 @@ private:
   std::unique_ptr<X86Operand>
   ParseIntelSegmentOverride(unsigned SegReg, SMLoc Start, unsigned Size);
   std::unique_ptr<X86Operand> ParseRoundingModeOp(SMLoc Start, SMLoc End);
+  bool ParseIntelNamedOperator(StringRef Name, IntelExprStateMachine &SM);
   bool ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End);
   std::unique_ptr<X86Operand>
   ParseIntelBracExpression(unsigned SegReg, SMLoc Start, int64_t ImmDisp,
@@ -1298,6 +1299,30 @@ RewriteIntelBracExpression(SmallVectorIm
   }
 }
 
+// Some binary bitwise operators have a named synonymous
+// Query a candidate string for being such a named operator
+// and if so - invoke the appropriate handler
+bool X86AsmParser::ParseIntelNamedOperator(StringRef Name, IntelExprStateMachine &SM) {
+  // A named operator should be either lower or upper case, but not a mix
+  if (Name.compare(Name.lower()) && Name.compare(Name.upper()))
+    return false;
+  if (Name.equals_lower("not"))
+    SM.onNot();
+  else if (Name.equals_lower("or"))
+    SM.onOr();
+  else if (Name.equals_lower("shl"))
+    SM.onLShift();
+  else if (Name.equals_lower("shr"))
+    SM.onRShift();
+  else if (Name.equals_lower("xor"))
+    SM.onXor();
+  else if (Name.equals_lower("and"))
+    SM.onAnd();
+  else
+    return false;
+  return true;
+}
+
 bool X86AsmParser::ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End) {
   MCAsmParser &Parser = getParser();
   const AsmToken &Tok = Parser.getTok();
@@ -1339,6 +1364,8 @@ bool X86AsmParser::ParseIntelExpression(
       UpdateLocLex = false;
       if (TK != AsmToken::String && !ParseRegister(TmpReg, IdentLoc, End)) {
         SM.onRegister(TmpReg);
+      } else if (ParseIntelNamedOperator(Identifier, SM)) {
+        UpdateLocLex = true;
       } else if (!isParsingInlineAsm()) {
         if (getParser().parsePrimaryExpr(Val, End))
           return Error(Tok.getLoc(), "Unexpected identifier!");

Modified: llvm/trunk/test/MC/X86/intel-syntax-bitwise-ops.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/intel-syntax-bitwise-ops.s?rev=299439&r1=299438&r2=299439&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/intel-syntax-bitwise-ops.s (original)
+++ llvm/trunk/test/MC/X86/intel-syntax-bitwise-ops.s Tue Apr  4 09:43:23 2017
@@ -6,19 +6,53 @@
     and ecx, 1+2
 // CHECK: andl	$3, %ecx
     and ecx, 1|2
-// CHECK: andl	$3, %ecx
+// CHECK: andl $3, %ecx
+    and ecx, 1 or 2
+// CHECK: andl $3, %ecx
+    and ecx, 1 OR 2
+// CHECK: andl $3, %ecx
     and ecx, 1*3
 // CHECK: andl	$1, %ecx
     and ecx, 1&3
-// CHECK: andl	$0, %ecx
+// CHECK: andl $1, %ecx
+    and ecx, 1 and 3
+// CHECK: andl $1, %ecx
+    and ecx, 1 AND 3
+// CHECK: andl $0, %ecx
     and ecx, (1&2)
-// CHECK: andl	$3, %ecx
+// CHECK: andl $0, %ecx
+    and ecx, (1 and 2)
+// CHECK: andl $0, %ecx
+    and ecx, (1 AND 2)
+// CHECK: andl $3, %ecx
     and ecx, ((1)|2)
-// CHECK: andl	$1, %ecx
+// CHECK: andl $3, %ecx
+    and ecx, ((1) or 2)
+// CHECK: andl $3, %ecx
+    and ecx, ((1) OR 2)
+// CHECK: andl $1, %ecx
     and ecx, 1&2+3
-// CHECK: addl	$4938, %eax
+// CHECK: andl $1, %ecx
+    and ecx, 1 and 2+3
+// CHECK: andl $1, %ecx
+    and ecx, 1 AND 2+3
+// CHECK: addl $4938, %eax
     add eax, 9876 >> 1
-// CHECK: addl	$19752, %eax
+// CHECK: addl $4938, %eax
+    add eax, 9876 shr 1
+// CHECK: addl $4938, %eax
+    add eax, 9876 SHR 1
+// CHECK: addl $19752, %eax
     add eax, 9876 << 1
-// CHECK: addl	$5, %eax
+// CHECK: addl $19752, %eax
+    add eax, 9876 shl 1
+// CHECK: addl $19752, %eax
+    add eax, 9876 SHL 1
+// CHECK: addl $5, %eax
     add eax, 6 ^ 3
+// CHECK: addl $5, %eax
+    add eax, 6 xor 3
+// CHECK: addl $5, %eax
+    add eax, 6 XOR 3
+// CHECK: addl $5, %eax
+    add eax, 6 XOR 3 shl 1 SHR 1