[PATCH] D31615: AMDGPU: Add way to specify that instructions zero high 16-bits

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
Herald added subscribers: t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, kzhuravl.

https://reviews.llvm.org/D31615

Files:
  lib/Target/AMDGPU/SIDefines.h
  lib/Target/AMDGPU/SIInstrFormats.td
  lib/Target/AMDGPU/SIInstrInfo.cpp
  lib/Target/AMDGPU/SIInstrInfo.td


Index: lib/Target/AMDGPU/SIInstrInfo.td
===================================================================
--- lib/Target/AMDGPU/SIInstrInfo.td
+++ lib/Target/AMDGPU/SIInstrInfo.td
@@ -785,7 +785,7 @@
   RegisterOperand ret = !if(!eq(VT.Size, 32), VOPDstOperand<VGPR_32>,
                           !if(!eq(VT.Size, 128), VOPDstOperand<VReg_128>,
                             !if(!eq(VT.Size, 64), VOPDstOperand<VReg_64>,
-                              !if(!eq(VT.Size, 16), VOPDstOperand<VGPR_32>,
+                              !if(!eq(VT.Size, 16), VOPDstOperand16,
                               VOPDstOperand<SReg_64>)))); // else VT == i1
 }
 
Index: lib/Target/AMDGPU/SIInstrInfo.cpp
===================================================================
--- lib/Target/AMDGPU/SIInstrInfo.cpp
+++ lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -4082,7 +4082,21 @@
     KnownZero = 0xffff0000;
     return;
   }
-  default:
+  default: {
+    // XXX - Are there any 16-bit output instructions with second defs?
+    // FIXME:
+    assert(Def->getOperand(0).getReg() == Op.getReg() &&
+           Def->getOperand(0).getSubReg() == Op.getSubReg());
+    if (Def->getDesc().OpInfo[0].OperandType == AMDGPU::OPERAND_REG_DEF16) {
+      // FIXME: This isn't true for all instructions on gfx9, where some new
+      // instructions default to leaving high bits intact and there is a control
+      // bit for old instructions to change zeroing behavior.
+
+      KnownZero = 0xffff0000;
+      return;
+    }
+
     return;
+    }
   }
 }
Index: lib/Target/AMDGPU/SIInstrFormats.td
===================================================================
--- lib/Target/AMDGPU/SIInstrFormats.td
+++ lib/Target/AMDGPU/SIInstrFormats.td
@@ -178,6 +178,16 @@
 
 class VOPDstOperand <RegisterClass rc> : RegisterOperand <rc, "printVOPDst">;
 
+let OperandNamespace = "AMDGPU" in {
+def VOPDstOperand16 : VOPDstOperand<VGPR_32> {
+  let OperandType = "OPERAND_REG_DEF16";
+}
+}
+
+def VOPDstOperand32 : VOPDstOperand<VGPR_32>;
+def VOPDstOperand64 : VOPDstOperand<VReg_64>;
+def VOPDstOperand128 : VOPDstOperand<VReg_128>;
+
 class VINTRPe <bits<2> op> : Enc32 {
   bits<8> vdst;
   bits<8> vsrc;
Index: lib/Target/AMDGPU/SIDefines.h
===================================================================
--- lib/Target/AMDGPU/SIDefines.h
+++ lib/Target/AMDGPU/SIDefines.h
@@ -120,7 +120,10 @@
 
     /// Operand with 32-bit immediate that uses the constant bus.
     OPERAND_KIMM32,
-    OPERAND_KIMM16
+    OPERAND_KIMM16,
+
+    // Output register operand with 16-bit output.
+    OPERAND_REG_DEF16
   };
 }
 


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