[PATCH] D31331: [mips][msa] Truncation of vector elements for instructions creating ISD::SHL, ISD::SRL or ISD::SRA nodes

[Simon Dardis via Phabricator via llvm-commits]

sdardis requested changes to this revision.
sdardis added a comment.
This revision now requires changes to proceed.

This latest diff is too general. For the constant case we can perform the bit masking at compile time to reformulate the constant into something that LLVM's IR will treat as legal and that matches what the hardware will do.

For the general case we can elide the '(and operand, (build_vector <ElementSizeInBits -1>...))' with the following:

  def immi32Cst31 : ImmLeaf<i32, [{return isUInt<32>(Imm) && Imm == 31;}]>;
  
  def : MSAPat<
    (v4i32 (shl v4i32:$ws, (v4i32 (and v4i32:$wt,
                                       (build_vector immi32Cst31, immi32Cst31,
                                                     immi32Cst31, immi32Cst31))))),
    (v4i32 (SLL_W v4i32:$ws, v4i32:$wt))>;

(That example may need some reformatting.)

That example which I've briefly tested removes the and SDNode during ISel. You can modify that pattern into a multiclass and then instantiate it for the relevant instructions.

In principle we should cover the .b and .h cases as well.



================
Comment at: lib/Target/Mips/MipsSEISelLowering.cpp:1556-1560
+  SDValue ConstValue = DAG.getConstant(Vec.getScalarValueSizeInBits() - 1,
+                                       DL, ResEltTy);
+  SDValue SplatVec = getBuildVectorSplat(ResTy, ConstValue, BigEndian, DAG);
+
+  return DAG.getNode(ISD::AND, DL, ResTy, Vec, SplatVec);
----------------
This hunk only covers the non-constant case. When the operand to a logical ISD vector node--which implicitly masks the lower bits--is a ConstantSDnode, we should instead reformulate the constant so that it only contains bits that the MSA instructions will look at. 


https://reviews.llvm.org/D31331