[PATCH] D28152: Cortex-A57 scheduling model for ARM backend (AArch32)

[Andrew Zhogin via Phabricator via llvm-commits]

andrew.zhogin updated this revision to Diff 93801.
andrew.zhogin added a comment.

Changes to fix the performance regressions:

- Implemented FeatureCheapPredicableCPSR to disable +1 predication cost for CPSR-defining instructions and MispredictPenalty increased to 16. It tweaks if-conversion.
- Added FeatureAvoidPartialCPSR in the ProcessorModel.

With those changes only 2 tests have significant stable regressions (with --exec-multisample 5):
SingleSource/Benchmarks/BenchmarkGame/fannkuch	            6.19%
MultiSource/Benchmarks/Ptrdist/ft/ft	                                    3.75%

Both tests have problem with unrolling of inner loops with small (dynamic) loop counts.

With PGO-compilation the regressions are gone.

Also fixed problem with atomic loads second argument.


https://reviews.llvm.org/D28152

Files:
  include/llvm/CodeGen/TargetSchedule.h
  lib/Target/ARM/ARM.td
  lib/Target/ARM/ARMBaseInstrInfo.cpp
  lib/Target/ARM/ARMBaseInstrInfo.h
  lib/Target/ARM/ARMSchedule.td
  lib/Target/ARM/ARMScheduleA57.td
  lib/Target/ARM/ARMScheduleA57WriteRes.td
  lib/Target/ARM/ARMSubtarget.h
  test/CodeGen/ARM/cortex-a57-misched-alu.ll
  test/CodeGen/ARM/cortex-a57-misched-basic.ll
  test/CodeGen/ARM/cortex-a57-misched-ldm-wrback.ll
  test/CodeGen/ARM/cortex-a57-misched-ldm.ll
  test/CodeGen/ARM/cortex-a57-misched-stm-wrback.ll
  test/CodeGen/ARM/cortex-a57-misched-stm.ll
  test/CodeGen/ARM/cortex-a57-misched-vfma.ll
  test/CodeGen/ARM/cortex-a57-misched-vldm-wrback.ll
  test/CodeGen/ARM/cortex-a57-misched-vldm.ll
  test/CodeGen/ARM/cortex-a57-misched-vstm-wrback.ll
  test/CodeGen/ARM/cortex-a57-misched-vstm.ll

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