[PATCH] D31124: AMDGPU/SI: Add lane tracking to SI Scheduler

[Valery Pykhtin via Phabricator via llvm-commits]

vpykhtin added a comment.

I may miss something, but it looks that you can build data edges when building a superdag consisting of blocks. Incoming data edges would be liveins, outcoming - liveouts.

In https://reviews.llvm.org/D31124#715509, @axeldavy wrote:

> Could you describe how you would get all the relevant information ?
>
> Liveins are everything needed by instructions of the block that are not produced by the block (but you need to be careful of register reuse. Some SU in the block may produce the register, but after another would have consumed it).
>  LiveOuts are everything produced by the Block which is not released (because another consumer elsewhere). Similarly you need to capture when the register is consumed for the last time in the Block (there may be a later block with a consumer of the register, but another instruction of another Block would have produced the register before).
>  This seems hard to do without correct liveIntervals. Those are correct only when reordering and doing handleMove, etc.
>
> In https://reviews.llvm.org/D31124#715499, @vpykhtin wrote:
>
> > In general, I think moving instructions just to use standard RP tracker to discover liveins/liveouts isn't a good idea. It isn't only slow but doesn't look reliable too. Why not discover these sets using DAG directly?
>





Repository:
  rL LLVM

https://reviews.llvm.org/D31124