[PATCH] D31483: [DAGCombiner] convert and-of-seteq to bitwise logic+seteq (PR32401)

[Eli Friedman via Phabricator via llvm-commits]

efriedma added inline comments.


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Comment at: lib/CodeGen/SelectionDAG/DAGCombiner.cpp:3251
+    SDValue Zero = DAG.getConstant(0, DL, OpVT);
+    return DAG.getSetCC(DL, VT, Or, Zero, ISD::SETEQ);
+  }
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If you're going to do this, it would be nice to at least handle the inverse case: or(setne, setne).  Not sure what other related cases are worth transforming.


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Comment at: test/CodeGen/ARM/and-setcc.ll:27
+; CHECK-NEXT:    mov r0, #0
+; CHECK-NEXT:    movweq r0, #1
 ; CHECK-NEXT:    bx lr
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This isn't the shortest possible sequence; for example, gcc generates:

        cmp     r0, r1
        cmpeq   r2, r3
        moveq   r0, #1
        movne   r0, #0
        bx      lr

Probably not worth worrying about, though.


https://reviews.llvm.org/D31483