[PATCH] D31161: [AMDGPU] New Waitcnt Insertion Pass

[Kannan Narayanan via Phabricator via llvm-commits]

kanarayan updated this revision to Diff 93410.
kanarayan added a comment.

In response to review comments from arsenm, the following updates/responses:

The following updates to the code:

1. Removed Extra blank line.
2. Removed macro defining iterator on enum and replace it with inline code.
3. Replace with C++ style comments.
4. Use nullptr.
5. Replace Linemapping with LineMapping.
6. Use MI.isDebugValue()
7. Use getNamedOperand
8. Braces around the block (but clang-format likes addImm on same line).

The following will be addressed in a subsequent put-back.

1. LDS access check & GDS tests: The code can be simplified further as suggested. The generated code is overly conservative but correct.
2. Uses of getAtomicNoRetOp: The code is looking for atomic operations that do not return. The atomic operations that do return are covered by the  code that look for stores. Again, this is conservatively correct as is written, but needs to be fixed.

CreateMachineInstr - BuildMI was unusable in this context. Besides, X86 and some other code written for our target also use CreateMachineInstr.


https://reviews.llvm.org/D31161

Files:
  lib/Target/AMDGPU/AMDGPU.h
  lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
  lib/Target/AMDGPU/CMakeLists.txt
  lib/Target/AMDGPU/SIInsertWaitcnts.cpp
  test/CodeGen/AMDGPU/basic-branch.ll
  test/CodeGen/AMDGPU/branch-condition-and.ll
  test/CodeGen/AMDGPU/branch-relaxation.ll
  test/CodeGen/AMDGPU/control-flow-fastregalloc.ll
  test/CodeGen/AMDGPU/indirect-addressing-si.ll
  test/CodeGen/AMDGPU/infinite-loop.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.image.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.inv.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.inv.vol.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.vol.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.s.waitcnt.ll
  test/CodeGen/AMDGPU/multi-divergent-exit-region.ll
  test/CodeGen/AMDGPU/ret_jump.ll
  test/CodeGen/AMDGPU/si-lower-control-flow-unreachable-block.ll
  test/CodeGen/AMDGPU/smrd-vccz-bug.ll
  test/CodeGen/AMDGPU/spill-m0.ll
  test/CodeGen/AMDGPU/valu-i1.ll

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