[llvm] r299002 - [DAGCombiner] reduce code duplication by rearranging checks; NFCI

[Sanjay Patel via llvm-commits]

Author: spatel
Date: Wed Mar 29 10:37:33 2017
New Revision: 299002

URL: http://llvm.org/viewvc/llvm-project?rev=299002&view=rev
Log:
[DAGCombiner] reduce code duplication by rearranging checks; NFCI

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=299002&r1=299001&r2=299002&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Mar 29 10:37:33 2017
@@ -3188,62 +3188,56 @@ SDValue DAGCombiner::foldAndOfSetCCs(SDV
 
   if (LR == RR && CC0 == CC1 && IsInteger) {
     EVT CCVT = getSetCCResultType(LRVT);
-    // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0)
-    if (isNullConstant(LR) && CC1 == ISD::SETEQ) {
-      if (VT == CCVT || (!LegalOperations && VT == MVT::i1)) {
+    if (VT == CCVT || (!LegalOperations && VT == MVT::i1)) {
+      // (and (seteq X, 0), (seteq Y, 0)) --> (seteq (or X, Y), 0)
+      if (isNullConstant(LR) && CC1 == ISD::SETEQ) {
         SDValue Or = DAG.getNode(ISD::OR, SDLoc(N0), LRVT, LL, RL);
         AddToWorklist(Or.getNode());
         return DAG.getSetCC(DL, VT, Or, LR, CC1);
       }
-    }
-    if (isAllOnesConstant(LR)) {
-      // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1)
-      if (CC1 == ISD::SETEQ) {
-        if (VT == CCVT || (!LegalOperations && VT == MVT::i1)) {
-          SDValue And = DAG.getNode(ISD::AND, SDLoc(N0), LRVT, LL, RL);
-          AddToWorklist(And.getNode());
-          return DAG.getSetCC(DL, VT, And, LR, CC1);
-        }
+
+      // (and (seteq X, -1), (seteq Y, -1)) --> (seteq (and X, Y), -1)
+      if (isAllOnesConstant(LR) && CC1 == ISD::SETEQ) {
+        SDValue And = DAG.getNode(ISD::AND, SDLoc(N0), LRVT, LL, RL);
+        AddToWorklist(And.getNode());
+        return DAG.getSetCC(DL, VT, And, LR, CC1);
       }
-      // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1)
-      if (CC1 == ISD::SETGT) {
-        if (VT == CCVT || (!LegalOperations && VT == MVT::i1)) {
-          SDValue Or = DAG.getNode(ISD::OR, SDLoc(N0), LRVT, LL, RL);
-          AddToWorklist(Or.getNode());
-          return DAG.getSetCC(DL, VT, Or, LR, CC1);
-        }
+
+      // (and (setgt X, -1), (setgt Y, -1)) --> (setgt (or X, Y), -1)
+      if (isAllOnesConstant(LR) && CC1 == ISD::SETGT) {
+        SDValue Or = DAG.getNode(ISD::OR, SDLoc(N0), LRVT, LL, RL);
+        AddToWorklist(Or.getNode());
+        return DAG.getSetCC(DL, VT, Or, LR, CC1);
       }
     }
   }
 
-  // Simplify (and (setne X, 0), (setne X, -1)) -> (setuge (add X, 1), 2)
-  if (LL == RL && CC0 == CC1 && IsInteger && CC0 == ISD::SETNE &&
-      ((isNullConstant(LR) && isAllOnesConstant(RR)) ||
-       (isAllOnesConstant(LR) && isNullConstant(RR)))) {
-    EVT CCVT = getSetCCResultType(LLVT);
-    if (VT == CCVT || (!LegalOperations && VT == MVT::i1)) {
-      SDLoc DL0(N0);
-      SDValue Add =
-          DAG.getNode(ISD::ADD, DL0, LLVT, LL, DAG.getConstant(1, DL, LLVT));
+  EVT CCVT = getSetCCResultType(LLVT);
+  if (VT == CCVT || (!LegalOperations && VT == MVT::i1)) {
+    // (and (setne X, 0), (setne X, -1)) --> (setuge (add X, 1), 2)
+    if (LL == RL && CC0 == CC1 && IsInteger && CC0 == ISD::SETNE &&
+        ((isNullConstant(LR) && isAllOnesConstant(RR)) ||
+         (isAllOnesConstant(LR) && isNullConstant(RR)))) {
+      SDValue One = DAG.getConstant(1, DL, LLVT);
+      SDValue Two = DAG.getConstant(2, DL, LLVT);
+      SDValue Add = DAG.getNode(ISD::ADD, SDLoc(N0), LLVT, LL, One);
       AddToWorklist(Add.getNode());
-      return DAG.getSetCC(DL, VT, Add, DAG.getConstant(2, DL, LLVT),
-                          ISD::SETUGE);
+      return DAG.getSetCC(DL, VT, Add, Two, ISD::SETUGE);
     }
-  }
 
-  // Canonicalize equivalent operands to LL == RL.
-  if (LL == RR && LR == RL) {
-    CC1 = ISD::getSetCCSwappedOperands(CC1);
-    std::swap(RL, RR);
-  }
-  if (LL == RL && LR == RR) {
-    ISD::CondCode NewCC = ISD::getSetCCAndOperation(CC0, CC1, IsInteger);
-    if (NewCC != ISD::SETCC_INVALID &&
-        (!LegalOperations ||
-         (TLI.isCondCodeLegal(NewCC, LL.getSimpleValueType()) &&
-          TLI.isOperationLegal(ISD::SETCC, LLVT)))) {
-      EVT CCVT = getSetCCResultType(LLVT);
-      if (VT == CCVT || (!LegalOperations && VT == MVT::i1))
+    // Canonicalize equivalent operands to LL == RL.
+    if (LL == RR && LR == RL) {
+      CC1 = ISD::getSetCCSwappedOperands(CC1);
+      std::swap(RL, RR);
+    }
+
+    // (and (setcc X, Y, CC0), (setcc X, Y, CC1)) --> (setcc X, Y, NewCC)
+    if (LL == RL && LR == RR) {
+      ISD::CondCode NewCC = ISD::getSetCCAndOperation(CC0, CC1, IsInteger);
+      if (NewCC != ISD::SETCC_INVALID &&
+          (!LegalOperations ||
+           (TLI.isCondCodeLegal(NewCC, LL.getSimpleValueType()) &&
+            TLI.isOperationLegal(ISD::SETCC, LLVT))))
         return DAG.getSetCC(DL, VT, LL, LR, NewCC);
     }
   }