[PATCH] D31124: AMDGPU/SI: Add lane tracking to SI Scheduler

[Valery Pykhtin via Phabricator via llvm-commits]

vpykhtin added a comment.

Why SIScheduleBlockCreator::scheduleInsideBlocks() actually move instructions? Why it isn't done on the final scheduling?



================
Comment at: lib/Target/AMDGPU/SIMachineScheduler.cpp:1388
+        // Reset read - undef flags and update them later.
+        for (auto &Op : MI.operands())
+          if (Op.isReg() && Op.isDef())
----------------
duplicated code


================
Comment at: lib/Target/AMDGPU/SIMachineScheduler.h:498
 
-  std::set<unsigned> getInRegs() {
-    std::set<unsigned> InRegs;
-    for (const auto &RegMaskPair : RPTracker.getPressure().LiveInRegs) {
-      InRegs.insert(RegMaskPair.RegUnit);
-    }
-    return InRegs;
+  const SmallVector<RegisterMaskPair, 8> getInRegs() {
+    return RPTracker.getPressure().LiveInRegs;
----------------
You can make it const and return reference, like

const SmallVector<RegisterMaskPair, 8> &getInRegs() const;


================
Comment at: lib/Target/AMDGPU/SIMachineScheduler.h:502
 
-  std::set<unsigned> getOutRegs() {
-    std::set<unsigned> OutRegs;
-    for (const auto &RegMaskPair : RPTracker.getPressure().LiveOutRegs) {
-      OutRegs.insert(RegMaskPair.RegUnit);
-    }
-    return OutRegs;
+  const SmallVector<RegisterMaskPair, 8> getOutRegs() {
+    return RPTracker.getPressure().LiveOutRegs;
----------------
Ditto


Repository:
  rL LLVM

https://reviews.llvm.org/D31124