[PATCH] D31331: [mips][msa] Truncation of vector elements for instructions creating ISD::SHL, ISD::SRL or ISD::SRA nodes
Stefan Maksimovic via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 24 07:36:30 PDT 2017
smaksimovic created this revision.
Instructions that use said nodes, which have had their arguments altered are sll, srl, sra, bneg, bclr and bset.
In the specs, all of them have a comment that either the shift amount or the bit position that is specified in the corresponding vector elements will be interpreted as the shift amount/bit position modulo the size of the element in bits.
The problem lies in compiling with -O2 enabled, where the instructions for formats .w and .d are not generated, but are instead optimized away.
In this case, having shift amounts that are either negative or greater than the element bit size results in generation of incorrect results when doing the constant folding.
We remedy this by truncating the operands for the nodes mentioned above before actually creating them, so that the final result is correct before
placed into the constant pool.
We did it this way because we found out that the actual shifting of vector elements is done somewhere in llvm common code, not specific to MIPS.
While this seems necessary for -O2, it will also be done for other -O levels as well as of now. Is there a way to opt out for other levels of -O, since the instructions are generated and there is no need for this then?
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