[PATCH] D31124: AMDGPU/SI: Add lane tracking to SI Scheduler

[Axel Davy via Phabricator via llvm-commits]

axeldavy added a comment.

In https://reviews.llvm.org/D31124#708110, @rampitec wrote:

> In https://reviews.llvm.org/D31124#708105, @axeldavy wrote:
>
> > Si scheduler has a test file: test/CodeGen/AMDGPU/si-scheduler.ll
> >
> > But perhaps you meant a test with subreg ?
> >  I'm afraid it's hard to design a test for subregs specifically, since if the ops using subregs are inside the same blocks, the blocks inputs and outputs won't have subregs. And block creation algorithms can vary.
>
>
> You can create a MIR test. For example schedule-regpressure.mir runs only machine scheduler.


That doesn't entirely fix the mentionned problem.
Sisched works by regroupping instructions into Blocks, and scheduling the Blocks between them.
For the test to really check subregs, we'd have to make sure some blocks have subreg outputs.
One way would be to have the subregs involve high latency instructions, because those are always in separated blocks when there is Data dependency.
That is complicated though, I'd have to really investigate how to write tests.


Repository:
  rL LLVM

https://reviews.llvm.org/D31124