[llvm] r298357 - [DAGTypeLegalizer] Handle widening truncate to vector of i1.

[Jonas Paulsson via llvm-commits]

Author: jonpa
Date: Tue Mar 21 05:24:14 2017
New Revision: 298357

URL: http://llvm.org/viewvc/llvm-project?rev=298357&view=rev
Log:
[DAGTypeLegalizer]  Handle widening truncate to vector of i1.

Previously, PromoteIntRes_TRUNCATE() did not handle the case where
the operand needs widening, which resulted in llvm_unreachable().

This patch adds the needed handling, along with a test case.

Review: Eli Friedman, Simon Pilgrim.
https://reviews.llvm.org/D31077

Added:
    llvm/trunk/test/CodeGen/SystemZ/vec-trunc-to-i1.ll
Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=298357&r1=298356&r2=298357&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Tue Mar 21 05:24:14 2017
@@ -690,7 +690,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_
   case TargetLowering::TypePromoteInteger:
     Res = GetPromotedInteger(InOp);
     break;
-  case TargetLowering::TypeSplitVector:
+  case TargetLowering::TypeSplitVector: {
     EVT InVT = InOp.getValueType();
     assert(InVT.isVector() && "Cannot split scalar types");
     unsigned NumElts = InVT.getVectorNumElements();
@@ -709,6 +709,26 @@ SDValue DAGTypeLegalizer::PromoteIntRes_
 
     return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, EOp1, EOp2);
   }
+  case TargetLowering::TypeWidenVector: {
+    SDValue WideInOp = GetWidenedVector(InOp);
+
+    // Truncate widened InOp.
+    unsigned NumElem = WideInOp.getValueType().getVectorNumElements();
+    EVT TruncVT = EVT::getVectorVT(*DAG.getContext(),
+                                   N->getValueType(0).getScalarType(), NumElem);
+    SDValue WideTrunc = DAG.getNode(ISD::TRUNCATE, dl, TruncVT, WideInOp);
+
+    // Zero extend so that the elements are of same type as those of NVT
+    EVT ExtVT = EVT::getVectorVT(*DAG.getContext(), NVT.getVectorElementType(),
+                                 NumElem);
+    SDValue WideExt = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, WideTrunc);
+
+    // Extract the low NVT subvector.
+    MVT IdxTy = TLI.getVectorIdxTy(DAG.getDataLayout());
+    SDValue ZeroIdx = DAG.getConstant(0, dl, IdxTy);
+    return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, WideExt, ZeroIdx);
+  }
+  }
 
   // Truncate to NVT instead of VT
   return DAG.getNode(ISD::TRUNCATE, dl, NVT, Res);

Added: llvm/trunk/test/CodeGen/SystemZ/vec-trunc-to-i1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/vec-trunc-to-i1.ll?rev=298357&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/vec-trunc-to-i1.ll (added)
+++ llvm/trunk/test/CodeGen/SystemZ/vec-trunc-to-i1.ll Tue Mar 21 05:24:14 2017
@@ -0,0 +1,37 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+;
+; Check that a widening truncate to a vector of i1 elements can be handled.
+
+
+define void @pr32275(<4 x i8> %B15) {
+; CHECK-LABEL: pr32275:
+; CHECK:       # BB#0: # %BB
+; CHECK-NEXT:    vrepif %v0, 1
+; CHECK-NEXT:  .LBB0_1: # %CF34
+; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    vlgvb %r0, %v24, 3
+; CHECK-NEXT:    vlgvb %r1, %v24, 1
+; CHECK-NEXT:    vlvgp %v1, %r1, %r0
+; CHECK-NEXT:    vlgvb %r0, %v24, 0
+; CHECK-NEXT:    vlvgf %v1, %r0, 0
+; CHECK-NEXT:    vlgvb %r0, %v24, 2
+; CHECK-NEXT:    vlvgf %v1, %r0, 2
+; CHECK-NEXT:    vn %v1, %v1, %v0
+; CHECK-NEXT:    vlgvf %r0, %v1, 3
+; CHECK-NEXT:    tmll %r0, 1
+; CHECK-NEXT:    jne .LBB0_1
+; CHECK-NEXT:  # BB#2: # %CF36
+; CHECK-NEXT:    br %r14
+BB:
+  br label %CF34
+
+CF34:
+  %Tr24 = trunc <4 x i8> %B15 to <4 x i1>
+  %E28 = extractelement <4 x i1> %Tr24, i32 3
+  br i1 %E28, label %CF34, label %CF36
+
+CF36:
+  ret void
+}