[llvm] r298328 - [ARM] Revert r297443 and r297820.
Friedman, Eli via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 20 17:43:05 PDT 2017
(Adding some people to the CC list for this revert.)
-Eli
On 3/20/2017 5:26 PM, Eli Friedman via llvm-commits wrote:
> Author: efriedma
> Date: Mon Mar 20 19:26:39 2017
> New Revision: 298328
>
> URL: http://llvm.org/viewvc/llvm-project?rev=298328&view=rev
> Log:
> [ARM] Revert r297443 and r297820.
>
> The glueless lowering of addc/adde in Thumb1 has known serious
> miscompiles (see https://reviews.llvm.org/D31081), and r297820
> causes an infinite loop for certain constructs. It's not
> clear when they will be fixed, so let's just take them out
> of the tree for now.
>
> (I resolved a small conflict with r297453.)
>
>
> Modified:
> llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
> llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
> llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
> llvm/trunk/test/CodeGen/Thumb/long.ll
>
> Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=298328&r1=298327&r2=298328&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Mon Mar 20 19:26:39 2017
> @@ -2028,16 +2028,6 @@ static const AddSubFlagsOpcodePair AddSu
> {ARM::RSBSrsi, ARM::RSBrsi},
> {ARM::RSBSrsr, ARM::RSBrsr},
>
> - {ARM::tADDSi3, ARM::tADDi3},
> - {ARM::tADDSi8, ARM::tADDi8},
> - {ARM::tADDSrr, ARM::tADDrr},
> - {ARM::tADCS, ARM::tADC},
> -
> - {ARM::tSUBSi3, ARM::tSUBi3},
> - {ARM::tSUBSi8, ARM::tSUBi8},
> - {ARM::tSUBSrr, ARM::tSUBrr},
> - {ARM::tSBCS, ARM::tSBC},
> -
> {ARM::t2ADDSri, ARM::t2ADDri},
> {ARM::t2ADDSrr, ARM::t2ADDrr},
> {ARM::t2ADDSrs, ARM::t2ADDrs},
>
> Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=298328&r1=298327&r2=298328&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Mon Mar 20 19:26:39 2017
> @@ -822,10 +822,13 @@ ARMTargetLowering::ARMTargetLowering(con
> setOperationAction(ISD::SRL, MVT::i64, Custom);
> setOperationAction(ISD::SRA, MVT::i64, Custom);
>
> - setOperationAction(ISD::ADDC, MVT::i32, Custom);
> - setOperationAction(ISD::ADDE, MVT::i32, Custom);
> - setOperationAction(ISD::SUBC, MVT::i32, Custom);
> - setOperationAction(ISD::SUBE, MVT::i32, Custom);
> + if (!Subtarget->isThumb1Only()) {
> + // FIXME: We should do this for Thumb1 as well.
> + setOperationAction(ISD::ADDC, MVT::i32, Custom);
> + setOperationAction(ISD::ADDE, MVT::i32, Custom);
> + setOperationAction(ISD::SUBC, MVT::i32, Custom);
> + setOperationAction(ISD::SUBE, MVT::i32, Custom);
> + }
>
> if (!Subtarget->isThumb1Only() && Subtarget->hasV6T2Ops())
> setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
> @@ -9093,45 +9096,19 @@ void ARMTargetLowering::AdjustInstrPostI
>
> // Rename pseudo opcodes.
> unsigned NewOpc = convertAddSubFlagsOpcode(MI.getOpcode());
> - unsigned ccOutIdx;
> if (NewOpc) {
> const ARMBaseInstrInfo *TII = Subtarget->getInstrInfo();
> MCID = &TII->get(NewOpc);
>
> - assert(MCID->getNumOperands() ==
> - MI.getDesc().getNumOperands() + 5 - MI.getDesc().getSize()
> - && "converted opcode should be the same except for cc_out"
> - " (and, on Thumb1, pred)");
> + assert(MCID->getNumOperands() == MI.getDesc().getNumOperands() + 1 &&
> + "converted opcode should be the same except for cc_out");
>
> MI.setDesc(*MCID);
>
> // Add the optional cc_out operand
> MI.addOperand(MachineOperand::CreateReg(0, /*isDef=*/true));
> -
> - // On Thumb1, move all input operands to the end, then add the predicate
> - if (Subtarget->isThumb1Only()) {
> - for (unsigned c = MCID->getNumOperands() - 4; c--;) {
> - MI.addOperand(MI.getOperand(1));
> - MI.RemoveOperand(1);
> - }
> -
> - // Restore the ties
> - for (unsigned i = MI.getNumOperands(); i--;) {
> - const MachineOperand& op = MI.getOperand(i);
> - if (op.isReg() && op.isUse()) {
> - int DefIdx = MCID->getOperandConstraint(i, MCOI::TIED_TO);
> - if (DefIdx != -1)
> - MI.tieOperands(DefIdx, i);
> - }
> - }
> -
> - MI.addOperand(MachineOperand::CreateImm(ARMCC::AL));
> - MI.addOperand(MachineOperand::CreateReg(0, /*isDef=*/false));
> - ccOutIdx = 1;
> - } else
> - ccOutIdx = MCID->getNumOperands() - 1;
> - } else
> - ccOutIdx = MCID->getNumOperands() - 1;
> + }
> + unsigned ccOutIdx = MCID->getNumOperands() - 1;
>
> // Any ARM instruction that sets the 's' bit should specify an optional
> // "cc_out" operand in the last operand position.
> @@ -9162,9 +9139,7 @@ void ARMTargetLowering::AdjustInstrPostI
> if (deadCPSR) {
> assert(!MI.getOperand(ccOutIdx).getReg() &&
> "expect uninitialized optional cc_out operand");
> - // Thumb1 instructions must have the S bit even if the CPSR is dead.
> - if (!Subtarget->isThumb1Only())
> - return;
> + return;
> }
>
> // If this instruction was defined with an optional CPSR def and its dag node
> @@ -9784,48 +9759,6 @@ static SDValue PerformUMLALCombine(SDNod
> return SDValue();
> }
>
> -static SDValue PerformAddcSubcCombine(SDNode *N, SelectionDAG &DAG,
> - const ARMSubtarget *Subtarget) {
> - if (Subtarget->isThumb1Only()) {
> - SDValue RHS = N->getOperand(1);
> - if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
> - int64_t imm = C->getSExtValue();
> - if (imm < 0) {
> - SDLoc DL(N);
> - RHS = DAG.getConstant(-imm, DL, MVT::i32);
> - unsigned Opcode = (N->getOpcode() == ARMISD::ADDC) ? ARMISD::SUBC
> - : ARMISD::ADDC;
> - return DAG.getNode(Opcode, DL, N->getVTList(), N->getOperand(0), RHS);
> - }
> - }
> - }
> - return SDValue();
> -}
> -
> -static SDValue PerformAddeSubeCombine(SDNode *N, SelectionDAG &DAG,
> - const ARMSubtarget *Subtarget) {
> - if (Subtarget->isThumb1Only()) {
> - SDValue RHS = N->getOperand(1);
> - if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
> - int64_t imm = C->getSExtValue();
> - if (imm < 0) {
> - SDLoc DL(N);
> -
> - // The with-carry-in form matches bitwise not instead of the negation.
> - // Effectively, the inverse interpretation of the carry flag already
> - // accounts for part of the negation.
> - RHS = DAG.getConstant(~imm, DL, MVT::i32);
> -
> - unsigned Opcode = (N->getOpcode() == ARMISD::ADDE) ? ARMISD::SUBE
> - : ARMISD::ADDE;
> - return DAG.getNode(Opcode, DL, N->getVTList(),
> - N->getOperand(0), RHS, N->getOperand(2));
> - }
> - }
> - }
> - return SDValue();
> -}
> -
> /// PerformADDECombine - Target-specific dag combine transform from
> /// ARMISD::ADDC, ARMISD::ADDE, and ISD::MUL_LOHI to MLAL or
> /// ARMISD::ADDC, ARMISD::ADDE and ARMISD::UMLAL to ARMISD::UMAAL
> @@ -9834,7 +9767,7 @@ static SDValue PerformADDECombine(SDNode
> const ARMSubtarget *Subtarget) {
> // Only ARM and Thumb2 support UMLAL/SMLAL.
> if (Subtarget->isThumb1Only())
> - return PerformAddeSubeCombine(N, DCI.DAG, Subtarget);
> + return SDValue();
>
> // Only perform the checks after legalize when the pattern is available.
> if (DCI.isBeforeLegalize()) return SDValue();
> @@ -11934,9 +11867,6 @@ SDValue ARMTargetLowering::PerformDAGCom
> case ISD::OR: return PerformORCombine(N, DCI, Subtarget);
> case ISD::XOR: return PerformXORCombine(N, DCI, Subtarget);
> case ISD::AND: return PerformANDCombine(N, DCI, Subtarget);
> - case ARMISD::ADDC:
> - case ARMISD::SUBC: return PerformAddcSubcCombine(N, DCI.DAG, Subtarget);
> - case ARMISD::SUBE: return PerformAddeSubeCombine(N, DCI.DAG, Subtarget);
> case ARMISD::BFI: return PerformBFICombine(N, DCI);
> case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI, Subtarget);
> case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);
>
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=298328&r1=298327&r2=298328&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Mon Mar 20 19:26:39 2017
> @@ -905,7 +905,7 @@ let isAdd = 1 in {
> def tADC : // A8.6.2
> T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
> "adc", "\t$Rdn, $Rm",
> - []>, Sched<[WriteALU]>;
> + [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
>
> // Add immediate
> def tADDi3 : // A8.6.4 T1
> @@ -933,43 +933,6 @@ let isAdd = 1 in {
> "add", "\t$Rd, $Rn, $Rm",
> [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
>
> - /// Similar to the above except these set the 's' bit so the
> - /// instruction modifies the CPSR register.
> - ///
> - /// These opcodes will be converted to the real non-S opcodes by
> - /// AdjustInstrPostInstrSelection after giving then an optional CPSR operand.
> - let hasPostISelHook = 1, Defs = [CPSR] in {
> - let isCommutable = 1 in
> - def tADCS : tPseudoInst<(outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
> - 2, IIC_iALUr,
> - [(set tGPR:$Rdn, CPSR, (ARMadde tGPR:$Rn, tGPR:$Rm,
> - CPSR))]>,
> - Requires<[IsThumb1Only]>,
> - Sched<[WriteALU]>;
> -
> - def tADDSi3 : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
> - 2, IIC_iALUi,
> - [(set tGPR:$Rd, CPSR, (ARMaddc tGPR:$Rm,
> - imm0_7:$imm3))]>,
> - Requires<[IsThumb1Only]>,
> - Sched<[WriteALU]>;
> -
> - def tADDSi8 : tPseudoInst<(outs tGPR:$Rdn), (ins tGPR:$Rn, imm0_255:$imm8),
> - 2, IIC_iALUi,
> - [(set tGPR:$Rdn, CPSR, (ARMaddc tGPR:$Rn,
> - imm8_255:$imm8))]>,
> - Requires<[IsThumb1Only]>,
> - Sched<[WriteALU]>;
> -
> - let isCommutable = 1 in
> - def tADDSrr : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
> - 2, IIC_iALUr,
> - [(set tGPR:$Rd, CPSR, (ARMaddc tGPR:$Rn,
> - tGPR:$Rm))]>,
> - Requires<[IsThumb1Only]>,
> - Sched<[WriteALU]>;
> - }
> -
> let hasSideEffects = 0 in
> def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr,
> "add", "\t$Rdn, $Rm", []>,
> @@ -1229,7 +1192,7 @@ def tSBC : // A8.6.
> T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
> IIC_iALUr,
> "sbc", "\t$Rdn, $Rm",
> - []>,
> + [(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>,
> Sched<[WriteALU]>;
>
> // Subtract immediate
> @@ -1258,41 +1221,6 @@ def tSUBrr : // A8.6.
> [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>,
> Sched<[WriteALU]>;
>
> -/// Similar to the above except these set the 's' bit so the
> -/// instruction modifies the CPSR register.
> -///
> -/// These opcodes will be converted to the real non-S opcodes by
> -/// AdjustInstrPostInstrSelection after giving then an optional CPSR operand.
> -let hasPostISelHook = 1, Defs = [CPSR] in {
> - def tSBCS : tPseudoInst<(outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
> - 2, IIC_iALUr,
> - [(set tGPR:$Rdn, CPSR, (ARMsube tGPR:$Rn, tGPR:$Rm,
> - CPSR))]>,
> - Requires<[IsThumb1Only]>,
> - Sched<[WriteALU]>;
> -
> - def tSUBSi3 : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
> - 2, IIC_iALUi,
> - [(set tGPR:$Rd, CPSR, (ARMsubc tGPR:$Rm,
> - imm0_7:$imm3))]>,
> - Requires<[IsThumb1Only]>,
> - Sched<[WriteALU]>;
> -
> - def tSUBSi8 : tPseudoInst<(outs tGPR:$Rdn), (ins tGPR:$Rn, imm0_255:$imm8),
> - 2, IIC_iALUi,
> - [(set tGPR:$Rdn, CPSR, (ARMsubc tGPR:$Rn,
> - imm8_255:$imm8))]>,
> - Requires<[IsThumb1Only]>,
> - Sched<[WriteALU]>;
> -
> - def tSUBSrr : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
> - 2, IIC_iALUr,
> - [(set tGPR:$Rd, CPSR, (ARMsubc tGPR:$Rn,
> - tGPR:$Rm))]>,
> - Requires<[IsThumb1Only]>,
> - Sched<[WriteALU]>;
> -}
> -
> // Sign-extend byte
> def tSXTB : // A8.6.222
> T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
> @@ -1453,6 +1381,22 @@ def : T1Pat<(ARMcmpZ tGPR:$Rn, imm0_255:
> def : T1Pat<(ARMcmpZ tGPR:$Rn, tGPR:$Rm),
> (tCMPr tGPR:$Rn, tGPR:$Rm)>;
>
> +// Add with carry
> +def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs),
> + (tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
> +def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs),
> + (tADDi8 tGPR:$lhs, imm8_255:$rhs)>;
> +def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs),
> + (tADDrr tGPR:$lhs, tGPR:$rhs)>;
> +
> +// Subtract with carry
> +def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs),
> + (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
> +def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs),
> + (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
> +def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs),
> + (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
> +
> // Bswap 16 with load/store
> def : T1Pat<(srl (bswap (extloadi16 t_addrmode_is2:$addr)), (i32 16)),
> (tREV16 (tLDRHi t_addrmode_is2:$addr))>;
>
> Modified: llvm/trunk/test/CodeGen/Thumb/long.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/long.ll?rev=298328&r1=298327&r2=298328&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Thumb/long.ll (original)
> +++ llvm/trunk/test/CodeGen/Thumb/long.ll Mon Mar 20 19:26:39 2017
> @@ -1,47 +1,33 @@
> -; RUN: llc -mtriple=thumb-eabi %s -verify-machineinstrs -o - | FileCheck %s
> -; RUN: llc -mtriple=thumb-apple-darwin %s -verify-machineinstrs -o - | \
> +; RUN: llc -mtriple=thumb-eabi %s -o - | FileCheck %s
> +; RUN: llc -mtriple=thumb-apple-darwin %s -o - | \
> ; RUN: FileCheck %s -check-prefix CHECK -check-prefix CHECK-DARWIN
>
> define i64 @f1() {
> entry:
> ret i64 0
> -; CHECK-LABEL: f1:
> -; CHECK: movs r0, #0
> -; CHECK: movs r1, r0
> }
>
> define i64 @f2() {
> entry:
> ret i64 1
> -; CHECK-LABEL: f2:
> -; CHECK: movs r0, #1
> -; CHECK: movs r1, #0
> }
>
> define i64 @f3() {
> entry:
> ret i64 2147483647
> -; CHECK-LABEL: f3:
> -; CHECK: ldr r0,
> -; CHECK: movs r1, #0
> }
>
> define i64 @f4() {
> entry:
> ret i64 2147483648
> -; CHECK-LABEL: f4:
> -; CHECK: movs r0, #1
> -; CHECK: lsls r0, r0, #31
> -; CHECK: movs r1, #0
> }
>
> define i64 @f5() {
> entry:
> ret i64 9223372036854775807
> ; CHECK-LABEL: f5:
> -; CHECK: movs r0, #0
> -; CHECK: mvns r0, r0
> -; CHECK: ldr r1,
> +; CHECK: mvn
> +; CHECK-NOT: mvn
> }
>
> define i64 @f6(i64 %x, i64 %y) {
> @@ -49,40 +35,14 @@ entry:
> %tmp1 = add i64 %y, 1 ; <i64> [#uses=1]
> ret i64 %tmp1
> ; CHECK-LABEL: f6:
> -; CHECK: movs r1, #0
> -; CHECK: adds r0, r2, #1
> -; CHECK: adcs r1, r3
> -}
> -
> -define i64 @f6a(i64 %x, i64 %y) {
> -entry:
> - %tmp1 = add i64 %y, 10
> - ret i64 %tmp1
> -; CHECK-LABEL: f6a:
> -; CHECK: movs r1, #0
> -; CHECK: adds r2, #10
> -; CHECK: adcs r1, r3
> -; CHECK: movs r0, r2
> -}
> -
> -define i64 @f6b(i64 %x, i64 %y) {
> -entry:
> - %tmp1 = add i64 %y, 1000
> - ret i64 %tmp1
> -; CHECK-LABEL: f6b:
> -; CHECK: movs r0, #125
> -; CHECK: lsls r0, r0, #3
> -; CHECK: movs r1, #0
> -; CHECK: adds r0, r2, r0
> -; CHECK: adcs r1, r3
> +; CHECK: adc
> +; CHECK-NOT: adc
> }
>
> define void @f7() {
> entry:
> %tmp = call i64 @f8( ) ; <i64> [#uses=0]
> ret void
> -; CHECK-LABEL: f7:
> -; CHECK: bl
> }
>
> declare i64 @f8()
> @@ -92,56 +52,8 @@ entry:
> %tmp = sub i64 %a, %b ; <i64> [#uses=1]
> ret i64 %tmp
> ; CHECK-LABEL: f9:
> -; CHECK: subs r0, r0, r2
> -; CHECK: sbcs r1, r3
> -}
> -
> -define i64 @f9a(i64 %x, i64 %y) { ; ADDC with small negative imm => SUBS imm
> -entry:
> - %tmp1 = sub i64 %y, 10
> - ret i64 %tmp1
> -; CHECK-LABEL: f9a:
> -; CHECK: movs r0, #0
> -; CHECK: subs r2, #10
> -; CHECK: sbcs r3, r0
> -; CHECK: movs r0, r2
> -; CHECK: movs r1, r3
> -}
> -
> -define i64 @f9b(i64 %x, i64 %y) { ; ADDC with big negative imm => SUBS reg
> -entry:
> - %tmp1 = sub i64 1000, %y
> - ret i64 %tmp1
> -; CHECK-LABEL: f9b:
> -; CHECK: movs r0, #125
> -; CHECK: lsls r0, r0, #3
> -; CHECK: movs r1, #0
> -; CHECK: subs r0, r0, r2
> -; CHECK: sbcs r1, r3
> -}
> -
> -define i64 @f9c(i64 %x, i32 %y) { ; SUBS with small positive imm => SUBS imm
> -entry:
> - %conv = sext i32 %y to i64
> - %shl = shl i64 %conv, 32
> - %or = or i64 %shl, 1
> - %sub = sub nsw i64 %x, %or
> - ret i64 %sub
> -; CHECK-LABEL: f9c:
> -; CHECK: subs r0, r0, #1
> -; CHECK: sbcs r1, r2
> -}
> -
> -define i64 @f9d(i64 %x, i32 %y) { ; SUBS with small negative imm => ADDS imm
> -entry:
> - %conv = sext i32 %y to i64
> - %shl = shl i64 %conv, 32
> - %or = or i64 %shl, 4294967295
> - %sub = sub nsw i64 %x, %or
> - ret i64 %sub
> -; CHECK-LABEL: f9d:
> -; CHECK: adds r0, r0, #1
> -; CHECK: sbcs r1, r2
> +; CHECK: sbc
> +; CHECK-NOT: sbc
> }
>
> define i64 @f(i32 %a, i32 %b) {
> @@ -151,7 +63,6 @@ entry:
> %tmp2 = mul i64 %tmp1, %tmp ; <i64> [#uses=1]
> ret i64 %tmp2
> ; CHECK-LABEL: f:
> -; CHECK-V6: bl __aeabi_lmul
> ; CHECK-DARWIN: __muldi3
> }
>
> @@ -162,7 +73,6 @@ entry:
> %tmp2 = mul i64 %tmp1, %tmp ; <i64> [#uses=1]
> ret i64 %tmp2
> ; CHECK-LABEL: g:
> -; CHECK-V6: bl __aeabi_lmul
> ; CHECK-DARWIN: __muldi3
> }
>
> @@ -171,26 +81,4 @@ entry:
> %a = alloca i64, align 8 ; <i64*> [#uses=1]
> %retval = load i64, i64* %a ; <i64> [#uses=1]
> ret i64 %retval
> -; CHECK-LABEL: f10:
> -; CHECK: sub sp, #8
> -; CHECK: ldr r0, [sp]
> -; CHECK: ldr r1, [sp, #4]
> -; CHECK: add sp, #8
> }
> -
> -define i64 @f11(i64 %x, i64 %y) {
> -entry:
> - %tmp1 = add i64 -1000, %y
> - %tmp2 = add i64 %tmp1, -1000
> - ret i64 %tmp2
> -; CHECK-LABEL: f11:
> -; CHECK: movs r0, #125
> -; CHECK: lsls r0, r0, #3
> -; CHECK: movs r1, #0
> -; CHECK: subs r2, r2, r0
> -; CHECK: sbcs r3, r1
> -; CHECK: subs r0, r2, r0
> -; CHECK: sbcs r3, r1
> -; CHECK: movs r1, r3
> -}
> -
>
>
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