[llvm] r298222 - [GlobalISel][AArch64] Split out cast select tests. NFC.

Ahmed Bougacha via llvm-commits llvm-commits at lists.llvm.org
Sun Mar 19 09:12:51 PDT 2017


Author: ab
Date: Sun Mar 19 11:12:51 2017
New Revision: 298222

URL: http://llvm.org/viewvc/llvm-project?rev=298222&view=rev
Log:
[GlobalISel][AArch64] Split out cast select tests. NFC.

And remove some redundant bitcast tests.

Also split the test functions themselves: it makes it obvious to see
what's tested where and what isn't, it makes the tests much easier to
read and manually update, and, most importantly, it makes them almost
trivial to update using tooling.  Yes, it's obnoxiously verbose, but
said tooling helps upgrade to better MIR syntax whenever available.

Added:
    llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir
    llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir
    llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-trunc.mir
Removed:
    llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-casts.mir
Modified:
    llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-bitcast.mir

Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-bitcast.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-bitcast.mir?rev=298222&r1=298221&r2=298222&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-bitcast.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-bitcast.mir Sun Mar 19 11:12:51 2017
@@ -1,16 +1,8 @@
-# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
+# RUN: llc -O0 -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
 
 --- |
   target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
 
-  define void @trunc() { ret void }
-
-  define void @anyext_gpr() { ret void }
-  define void @zext_gpr() { ret void }
-  define void @sext_gpr() { ret void }
-
-  define void @other_casts() { ret void }
-
   define void @bitcast_s32_gpr() { ret void }
   define void @bitcast_s32_fpr() { ret void }
   define void @bitcast_s32_gpr_fpr() { ret void }
@@ -22,198 +14,6 @@
 ...
 
 ---
-# CHECK-LABEL: name: trunc
-name:            trunc
-legalized:       true
-regBankSelected: true
-
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32 }
-# CHECK-NEXT:  - { id: 1, class: gpr32 }
-# CHECK-NEXT:  - { id: 2, class: gpr64 }
-# CHECK-NEXT:  - { id: 3, class: gpr32 }
-# CHECK-NEXT:  - { id: 4, class: gpr32 }
-registers:
-  - { id: 0, class: gpr }
-  - { id: 1, class: gpr }
-  - { id: 2, class: gpr }
-  - { id: 3, class: gpr }
-  - { id: 4, class: gpr }
-
-# CHECK:  body:
-# CHECK:    %1 = COPY %0
-# CHECK:    %3 = COPY %2.sub_32
-# CHECK:    %4 = COPY %2.sub_32
-body:             |
-  bb.0:
-    liveins: %w0, %x0
-
-    %0(s32) = COPY %w0
-    %1(s1) = G_TRUNC %0
-
-    %2(s64) = COPY %x0
-    %3(s32) = G_TRUNC %2
-    %4(s8) = G_TRUNC %2
-...
-
----
-# CHECK-LABEL: name: anyext_gpr
-name:            anyext_gpr
-legalized:       true
-regBankSelected: true
-
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32all }
-# CHECK-NEXT:  - { id: 1, class: gpr64all }
-# CHECK-NEXT:  - { id: 2, class: gpr32all }
-# CHECK-NEXT:  - { id: 3, class: gpr32all }
-# CHECK-NEXT:  - { id: 4, class: gpr64all }
-registers:
-  - { id: 0, class: gpr }
-  - { id: 1, class: gpr }
-  - { id: 2, class: gpr }
-  - { id: 3, class: gpr }
-
-# CHECK:  body:
-# CHECK:    %0 = COPY %w0
-# CHECK:    %4 = SUBREG_TO_REG 0, %0, 15
-# CHECK:    %1 = COPY %4
-# CHECK:    %2 = COPY %w0
-# CHECK:    %3 = COPY %2
-body:             |
-  bb.0:
-    liveins: %w0
-
-    %0(s32) = COPY %w0
-    %1(s64) = G_ANYEXT %0
-    %2(s8) = COPY %w0
-    %3(s32) = G_ANYEXT %2
-...
-
----
-# CHECK-LABEL: name: zext_gpr
-name:            zext_gpr
-legalized:       true
-regBankSelected: true
-
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32 }
-# CHECK-NEXT:  - { id: 1, class: gpr64 }
-# CHECK-NEXT:  - { id: 2, class: gpr32 }
-# CHECK-NEXT:  - { id: 3, class: gpr32 }
-# CHECK-NEXT:  - { id: 4, class: gpr32 }
-# CHECK-NEXT:  - { id: 5, class: gpr64 }
-registers:
-  - { id: 0, class: gpr }
-  - { id: 1, class: gpr }
-  - { id: 2, class: gpr }
-  - { id: 3, class: gpr }
-  - { id: 4, class: gpr }
-
-# CHECK:  body:
-# CHECK:    %0 = COPY %w0
-# CHECK:    %5 = SUBREG_TO_REG 0, %0, 15
-# CHECK:    %1 = UBFMXri %5, 0, 31
-# CHECK:    %2 = COPY %w0
-# CHECK:    %3 = UBFMWri %2, 0, 7
-# CHECK:    %4 = UBFMWri %2, 0, 7
-body:             |
-  bb.0:
-    liveins: %w0
-
-    %0(s32) = COPY %w0
-    %1(s64) = G_ZEXT %0
-    %2(s8) = COPY %w0
-    %3(s32) = G_ZEXT %2
-    %4(s16)= G_ZEXT %2
-...
-
----
-# CHECK-LABEL: name: sext_gpr
-name:            sext_gpr
-legalized:       true
-regBankSelected: true
-
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32 }
-# CHECK-NEXT:  - { id: 1, class: gpr64 }
-# CHECK-NEXT:  - { id: 2, class: gpr32 }
-# CHECK-NEXT:  - { id: 3, class: gpr32 }
-# CHECK-NEXT:  - { id: 4, class: gpr32 }
-# CHECK-NEXT:  - { id: 5, class: gpr64 }
-registers:
-  - { id: 0, class: gpr }
-  - { id: 1, class: gpr }
-  - { id: 2, class: gpr }
-  - { id: 3, class: gpr }
-  - { id: 4, class: gpr }
-
-# CHECK:  body:
-# CHECK:    %0 = COPY %w0
-# CHECK:    %5 = SUBREG_TO_REG 0, %0, 15
-# CHECK:    %1 = SBFMXri %5, 0, 31
-# CHECK:    %2 = COPY %w0
-# CHECK:    %3 = SBFMWri %2, 0, 7
-# CHECK:    %4 = SBFMWri %2, 0, 7
-body:             |
-  bb.0:
-    liveins: %w0
-
-    %0(s32) = COPY %w0
-    %1(s64) = G_SEXT %0
-    %2(s8) = COPY %w0
-    %3(s32) = G_SEXT %2
-    %4(s16) = G_SEXT %2
-...
-
----
-# CHECK-LABEL: name: other_casts
-name:            other_casts
-legalized:       true
-regBankSelected: true
-
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64all }
-# CHECK-NEXT:  - { id: 1, class: fpr64 }
-# CHECK-NEXT:  - { id: 2, class: gpr64 }
-# CHECK-NEXT:  - { id: 3, class: gpr64 }
-# CHECK-NEXT:  - { id: 4, class: gpr32 }
-# CHECK-NEXT:  - { id: 5, class: gpr32 }
-# CHECK-NEXT:  - { id: 6, class: gpr32 }
-# CHECK-NEXT:  - { id: 7, class: gpr32 }
-registers:
-  - { id: 0, class: gpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: gpr }
-  - { id: 3, class: gpr }
-  - { id: 4, class: gpr }
-  - { id: 5, class: gpr }
-  - { id: 6, class: gpr }
-  - { id: 7, class: gpr }
-# CHECK:  body:
-# CHECK:    %0 = COPY %x0
-# CHECK:    %1 = COPY %0
-# CHECK:    %2 = COPY %0
-# CHECK:    %3 = COPY %2
-# CHECK:    %4 = COPY %2.sub_32
-# CHECK:    %5 = COPY %2.sub_32
-# CHECK:    %6 = COPY %2.sub_32
-# CHECK:    %7 = COPY %2.sub_32
-body:             |
-  bb.0:
-    liveins: %x0
-    %0(s64) = COPY %x0
-    %1(<8 x s8>) = G_BITCAST %0(s64)
-    %2(p0) = G_INTTOPTR %0
-
-    %3(s64) = G_PTRTOINT %2
-    %4(s32) = G_PTRTOINT %2
-    %5(s16) = G_PTRTOINT %2
-    %6(s8) = G_PTRTOINT %2
-    %7(s1) = G_PTRTOINT %2
-...
-
----
 # CHECK-LABEL: name: bitcast_s32_gpr
 name:            bitcast_s32_gpr
 legalized:       true

Removed: llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-casts.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-casts.mir?rev=298221&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-casts.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-casts.mir (removed)
@@ -1,204 +0,0 @@
-# RUN: llc -O0 -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
-
---- |
-  target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
-
-  define void @bitcast_s32_gpr() { ret void }
-  define void @bitcast_s32_fpr() { ret void }
-  define void @bitcast_s32_gpr_fpr() { ret void }
-  define void @bitcast_s32_fpr_gpr() { ret void }
-  define void @bitcast_s64_gpr() { ret void }
-  define void @bitcast_s64_fpr() { ret void }
-  define void @bitcast_s64_gpr_fpr() { ret void }
-  define void @bitcast_s64_fpr_gpr() { ret void }
-...
-
----
-# CHECK-LABEL: name: bitcast_s32_gpr
-name:            bitcast_s32_gpr
-legalized:       true
-regBankSelected: true
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32all }
-# CHECK-NEXT:  - { id: 1, class: gpr32all }
-registers:
-  - { id: 0, class: gpr }
-  - { id: 1, class: gpr }
-
-# CHECK:  body:
-# CHECK:    %0 = COPY %w0
-# CHECK:    %1 = COPY %0
-body:             |
-  bb.0:
-    liveins: %w0
-
-    %0(s32) = COPY %w0
-    %1(s32) = G_BITCAST %0
-...
-
----
-# CHECK-LABEL: name: bitcast_s32_fpr
-name:            bitcast_s32_fpr
-legalized:       true
-regBankSelected: true
-
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: fpr32 }
-# CHECK-NEXT:  - { id: 1, class: fpr32 }
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-
-# CHECK:  body:
-# CHECK:    %0 = COPY %s0
-# CHECK:    %1 = COPY %0
-body:             |
-  bb.0:
-    liveins: %s0
-
-    %0(s32) = COPY %s0
-    %1(s32) = G_BITCAST %0
-...
-
----
-# CHECK-LABEL: name: bitcast_s32_gpr_fpr
-name:            bitcast_s32_gpr_fpr
-legalized:       true
-regBankSelected: true
-
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32all }
-# CHECK-NEXT:  - { id: 1, class: fpr32 }
-registers:
-  - { id: 0, class: gpr }
-  - { id: 1, class: fpr }
-
-# CHECK:  body:
-# CHECK:    %0 = COPY %w0
-# CHECK:    %1 = COPY %0
-body:             |
-  bb.0:
-    liveins: %w0
-
-    %0(s32) = COPY %w0
-    %1(s32) = G_BITCAST %0
-...
-
----
-# CHECK-LABEL: name: bitcast_s32_fpr_gpr
-name:            bitcast_s32_fpr_gpr
-legalized:       true
-regBankSelected: true
-
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: fpr32 }
-# CHECK-NEXT:  - { id: 1, class: gpr32all }
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: gpr }
-
-# CHECK:  body:
-# CHECK:    %0 = COPY %s0
-# CHECK:    %1 = COPY %0
-body:             |
-  bb.0:
-    liveins: %s0
-
-    %0(s32) = COPY %s0
-    %1(s32) = G_BITCAST %0
-...
-
----
-# CHECK-LABEL: name: bitcast_s64_gpr
-name:            bitcast_s64_gpr
-legalized:       true
-regBankSelected: true
-
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64all }
-# CHECK-NEXT:  - { id: 1, class: gpr64all }
-registers:
-  - { id: 0, class: gpr }
-  - { id: 1, class: gpr }
-
-# CHECK:  body:
-# CHECK:    %0 = COPY %x0
-# CHECK:    %1 = COPY %0
-body:             |
-  bb.0:
-    liveins: %x0
-
-    %0(s64) = COPY %x0
-    %1(s64) = G_BITCAST %0
-...
-
----
-# CHECK-LABEL: name: bitcast_s64_fpr
-name:            bitcast_s64_fpr
-legalized:       true
-regBankSelected: true
-
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: fpr64 }
-# CHECK-NEXT:  - { id: 1, class: fpr64 }
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-
-# CHECK:  body:
-# CHECK:    %0 = COPY %d0
-# CHECK:    %1 = COPY %0
-body:             |
-  bb.0:
-    liveins: %d0
-
-    %0(s64) = COPY %d0
-    %1(s64) = G_BITCAST %0
-...
-
----
-# CHECK-LABEL: name: bitcast_s64_gpr_fpr
-name:            bitcast_s64_gpr_fpr
-legalized:       true
-regBankSelected: true
-
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64all }
-# CHECK-NEXT:  - { id: 1, class: fpr64 }
-registers:
-  - { id: 0, class: gpr }
-  - { id: 1, class: fpr }
-# CHECK:  body:
-# CHECK:    %0 = COPY %x0
-# CHECK:    %1 = COPY %0
-body:             |
-  bb.0:
-    liveins: %x0
-
-    %0(s64) = COPY %x0
-    %1(s64) = G_BITCAST %0
-...
-
----
-# CHECK-LABEL: name: bitcast_s64_fpr_gpr
-name:            bitcast_s64_fpr_gpr
-legalized:       true
-regBankSelected: true
-
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: fpr64 }
-# CHECK-NEXT:  - { id: 1, class: gpr64all }
-registers:
-  - { id: 0, class: fpr }
-  - { id: 1, class: gpr }
-
-# CHECK:  body:
-# CHECK:    %0 = COPY %d0
-# CHECK:    %1 = COPY %0
-body:             |
-  bb.0:
-    liveins: %d0
-
-    %0(s64) = COPY %d0
-    %1(s64) = G_BITCAST %0
-...

Added: llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir?rev=298222&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir (added)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir Sun Mar 19 11:12:51 2017
@@ -0,0 +1,214 @@
+# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
+
+--- |
+  target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+
+  define void @anyext_s64_s32() { ret void }
+  define void @anyext_s32_s8() { ret void }
+
+  define void @zext_s64_s32() { ret void }
+  define void @zext_s32_s8() { ret void }
+  define void @zext_s16_s8() { ret void }
+
+  define void @sext_s64_s32() { ret void }
+  define void @sext_s32_s8() { ret void }
+  define void @sext_s16_s8() { ret void }
+...
+
+---
+# CHECK-LABEL: name: anyext_s64_s32
+name:            anyext_s64_s32
+legalized:       true
+regBankSelected: true
+
+# CHECK:      registers:
+# CHECK-NEXT:  - { id: 0, class: gpr32all }
+# CHECK-NEXT:  - { id: 1, class: gpr64all }
+# CHECK-NEXT:  - { id: 2, class: gpr64all }
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+
+# CHECK:  body:
+# CHECK:    %0 = COPY %w0
+# CHECK:    %2 = SUBREG_TO_REG 0, %0, 15
+# CHECK:    %1 = COPY %2
+body:             |
+  bb.0:
+    liveins: %w0
+
+    %0(s32) = COPY %w0
+    %1(s64) = G_ANYEXT %0
+...
+
+---
+# CHECK-LABEL: name: anyext_s32_s8
+name:            anyext_s32_s8
+legalized:       true
+regBankSelected: true
+
+# CHECK:      registers:
+# CHECK-NEXT:  - { id: 0, class: gpr32all }
+# CHECK-NEXT:  - { id: 1, class: gpr32all }
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+
+# CHECK:  body:
+# CHECK:    %0 = COPY %w0
+# CHECK:    %1 = COPY %0
+body:             |
+  bb.0:
+    liveins: %w0
+
+    %0(s8) = COPY %w0
+    %1(s32) = G_ANYEXT %0
+...
+
+---
+# CHECK-LABEL: name: zext_s64_s32
+name:            zext_s64_s32
+legalized:       true
+regBankSelected: true
+
+# CHECK:      registers:
+# CHECK-NEXT:  - { id: 0, class: gpr32 }
+# CHECK-NEXT:  - { id: 1, class: gpr64 }
+# CHECK-NEXT:  - { id: 2, class: gpr64 }
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+
+# CHECK:  body:
+# CHECK:    %0 = COPY %w0
+# CHECK:    %2 = SUBREG_TO_REG 0, %0, 15
+# CHECK:    %1 = UBFMXri %2, 0, 31
+body:             |
+  bb.0:
+    liveins: %w0
+
+    %0(s32) = COPY %w0
+    %1(s64) = G_ZEXT %0
+...
+
+---
+# CHECK-LABEL: name: zext_s32_s8
+name:            zext_s32_s8
+legalized:       true
+regBankSelected: true
+
+# CHECK:      registers:
+# CHECK-NEXT:  - { id: 0, class: gpr32 }
+# CHECK-NEXT:  - { id: 1, class: gpr32 }
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+
+# CHECK:  body:
+# CHECK:    %0 = COPY %w0
+# CHECK:    %1 = UBFMWri %0, 0, 7
+body:             |
+  bb.0:
+    liveins: %w0
+
+    %0(s8) = COPY %w0
+    %1(s32) = G_ZEXT %0
+...
+
+---
+# CHECK-LABEL: name: zext_s16_s8
+name:            zext_s16_s8
+legalized:       true
+regBankSelected: true
+
+# CHECK:      registers:
+# CHECK-NEXT:  - { id: 0, class: gpr32 }
+# CHECK-NEXT:  - { id: 1, class: gpr32 }
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+
+# CHECK:  body:
+# CHECK:    %0 = COPY %w0
+# CHECK:    %1 = UBFMWri %0, 0, 7
+body:             |
+  bb.0:
+    liveins: %w0
+
+    %0(s8) = COPY %w0
+    %1(s16) = G_ZEXT %0
+...
+
+---
+# CHECK-LABEL: name: sext_s64_s32
+name:            sext_s64_s32
+legalized:       true
+regBankSelected: true
+
+# CHECK:      registers:
+# CHECK-NEXT:  - { id: 0, class: gpr32 }
+# CHECK-NEXT:  - { id: 1, class: gpr64 }
+# CHECK-NEXT:  - { id: 2, class: gpr64 }
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+
+# CHECK:  body:
+# CHECK:    %0 = COPY %w0
+# CHECK:    %2 = SUBREG_TO_REG 0, %0, 15
+# CHECK:    %1 = SBFMXri %2, 0, 31
+body:             |
+  bb.0:
+    liveins: %w0
+
+    %0(s32) = COPY %w0
+    %1(s64) = G_SEXT %0
+...
+
+---
+# CHECK-LABEL: name: sext_s32_s8
+name:            sext_s32_s8
+legalized:       true
+regBankSelected: true
+
+# CHECK:      registers:
+# CHECK-NEXT:  - { id: 0, class: gpr32 }
+# CHECK-NEXT:  - { id: 1, class: gpr32 }
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+
+# CHECK:  body:
+# CHECK:    %0 = COPY %w0
+# CHECK:    %1 = SBFMWri %0, 0, 7
+body:             |
+  bb.0:
+    liveins: %w0
+
+    %0(s8) = COPY %w0
+    %1(s32) = G_SEXT %0
+...
+
+---
+# CHECK-LABEL: name: sext_s16_s8
+name:            sext_s16_s8
+legalized:       true
+regBankSelected: true
+
+# CHECK:      registers:
+# CHECK-NEXT:  - { id: 0, class: gpr32 }
+# CHECK-NEXT:  - { id: 1, class: gpr32 }
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+
+# CHECK:  body:
+# CHECK:    %0 = COPY %w0
+# CHECK:    %1 = SBFMWri %0, 0, 7
+body:             |
+  bb.0:
+    liveins: %w0
+
+    %0(s8) = COPY %w0
+    %1(s16) = G_SEXT %0
+...

Added: llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir?rev=298222&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir (added)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir Sun Mar 19 11:12:51 2017
@@ -0,0 +1,144 @@
+# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
+
+--- |
+  target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+
+  define void @inttoptr_p0_s64() { ret void }
+  define void @ptrtoint_s64_p0() { ret void }
+  define void @ptrtoint_s32_p0() { ret void }
+  define void @ptrtoint_s16_p0() { ret void }
+  define void @ptrtoint_s8_p0() { ret void }
+  define void @ptrtoint_s1_p0() { ret void }
+...
+
+---
+# CHECK-LABEL: name: inttoptr_p0_s64
+name:            inttoptr_p0_s64
+legalized:       true
+regBankSelected: true
+
+# CHECK:      registers:
+# CHECK-NEXT:  - { id: 0, class: gpr64all }
+# CHECK-NEXT:  - { id: 1, class: gpr64all }
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+# CHECK:  body:
+# CHECK:    %0 = COPY %x0
+# CHECK:    %1 = COPY %0
+body:             |
+  bb.0:
+    liveins: %x0
+    %0(s64) = COPY %x0
+    %1(p0) = G_INTTOPTR %0
+...
+
+---
+# CHECK-LABEL: name: ptrtoint_s64_p0
+name:            ptrtoint_s64_p0
+legalized:       true
+regBankSelected: true
+
+# CHECK:      registers:
+# CHECK-NEXT:  - { id: 0, class: gpr64 }
+# CHECK-NEXT:  - { id: 1, class: gpr64 }
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+# CHECK:  body:
+# CHECK:    %0 = COPY %x0
+# CHECK:    %1 = COPY %0
+body:             |
+  bb.0:
+    liveins: %x0
+    %0(p0) = COPY %x0
+    %1(s64) = G_PTRTOINT %0
+...
+
+---
+# CHECK-LABEL: name: ptrtoint_s32_p0
+name:            ptrtoint_s32_p0
+legalized:       true
+regBankSelected: true
+
+# CHECK:      registers:
+# CHECK-NEXT:  - { id: 0, class: gpr64 }
+# CHECK-NEXT:  - { id: 1, class: gpr32 }
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+# CHECK:  body:
+# CHECK:    %0 = COPY %x0
+# CHECK:    %1 = COPY %0.sub_32
+body:             |
+  bb.0:
+    liveins: %x0
+    %0(p0) = COPY %x0
+    %1(s32) = G_PTRTOINT %0
+...
+
+---
+# CHECK-LABEL: name: ptrtoint_s16_p0
+name:            ptrtoint_s16_p0
+legalized:       true
+regBankSelected: true
+
+# CHECK:      registers:
+# CHECK-NEXT:  - { id: 0, class: gpr64 }
+# CHECK-NEXT:  - { id: 1, class: gpr32 }
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+# CHECK:  body:
+# CHECK:    %0 = COPY %x0
+# CHECK:    %1 = COPY %0.sub_32
+body:             |
+  bb.0:
+    liveins: %x0
+    %0(p0) = COPY %x0
+    %1(s16) = G_PTRTOINT %0
+...
+
+---
+# CHECK-LABEL: name: ptrtoint_s8_p0
+name:            ptrtoint_s8_p0
+legalized:       true
+regBankSelected: true
+
+# CHECK:      registers:
+# CHECK-NEXT:  - { id: 0, class: gpr64 }
+# CHECK-NEXT:  - { id: 1, class: gpr32 }
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+# CHECK:  body:
+# CHECK:    %0 = COPY %x0
+# CHECK:    %1 = COPY %0.sub_32
+body:             |
+  bb.0:
+    liveins: %x0
+    %0(p0) = COPY %x0
+    %1(s8) = G_PTRTOINT %0
+...
+
+---
+# CHECK-LABEL: name: ptrtoint_s1_p0
+name:            ptrtoint_s1_p0
+legalized:       true
+regBankSelected: true
+
+# CHECK:      registers:
+# CHECK-NEXT:  - { id: 0, class: gpr64 }
+# CHECK-NEXT:  - { id: 1, class: gpr32 }
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+# CHECK:  body:
+# CHECK:    %0 = COPY %x0
+# CHECK:    %1 = COPY %0.sub_32
+body:             |
+  bb.0:
+    liveins: %x0
+    %0(p0) = COPY %x0
+    %1(s1) = G_PTRTOINT %0
+...

Added: llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-trunc.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-trunc.mir?rev=298222&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-trunc.mir (added)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-trunc.mir Sun Mar 19 11:12:51 2017
@@ -0,0 +1,78 @@
+# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
+
+--- |
+  target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+
+  define void @trunc_s32_s64() { ret void }
+  define void @trunc_s8_s64() { ret void }
+  define void @trunc_s1_s32() { ret void }
+...
+
+---
+# CHECK-LABEL: name: trunc_s32_s64
+name:            trunc_s32_s64
+legalized:       true
+regBankSelected: true
+
+# CHECK:      registers:
+# CHECK-NEXT:  - { id: 0, class: gpr64 }
+# CHECK-NEXT:  - { id: 1, class: gpr32 }
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+
+# CHECK:  body:
+# CHECK:    %1 = COPY %0.sub_32
+body:             |
+  bb.0:
+    liveins: %x0
+
+    %0(s64) = COPY %x0
+    %1(s32) = G_TRUNC %0
+...
+
+---
+# CHECK-LABEL: name: trunc_s8_s64
+name:            trunc_s8_s64
+legalized:       true
+regBankSelected: true
+
+# CHECK:      registers:
+# CHECK-NEXT:  - { id: 0, class: gpr64 }
+# CHECK-NEXT:  - { id: 1, class: gpr32 }
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+
+# CHECK:  body:
+# CHECK:    %1 = COPY %0.sub_32
+body:             |
+  bb.0:
+    liveins: %x0
+
+    %0(s64) = COPY %x0
+    %1(s8) = G_TRUNC %0
+...
+
+---
+# CHECK-LABEL: name: trunc_s1_s32
+name:            trunc_s1_s32
+legalized:       true
+regBankSelected: true
+
+# CHECK:      registers:
+# CHECK-NEXT:  - { id: 0, class: gpr32 }
+# CHECK-NEXT:  - { id: 1, class: gpr32 }
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+
+# CHECK:  body:
+# CHECK:    %1 = COPY %0
+body:             |
+  bb.0:
+    liveins: %w0
+
+    %0(s32) = COPY %w0
+    %1(s1) = G_TRUNC %0
+...




More information about the llvm-commits mailing list