[PATCH] D31081: [ARM] ScheduleDAGRRList::DelayForLiveRegsBottomUp must consider OptionalDefs

[A. Skrobov via Phabricator via llvm-commits]

tyomitch added a comment.

> This is complicated by the fact that in Thumb1, the non-S variants don't actually exist, which is why we have this particular problem.

It's slightly more complicated than this: in Thumb1, the instruction is //either// predicated //or// has the S bit, so the backend needs to be able to model both cases.


Repository:
  rL LLVM

https://reviews.llvm.org/D31081