[llvm] r298107 - [x86] avoid adc/sbb assert when both sides of add are zexted (PR32316)

[Sanjay Patel via llvm-commits]

Author: spatel
Date: Fri Mar 17 12:27:31 2017
New Revision: 298107

URL: http://llvm.org/viewvc/llvm-project?rev=298107&view=rev
Log:
[x86] avoid adc/sbb assert when both sides of add are zexted (PR32316)

As noted in the comment, we might want to account for this case,
but I didn't look at what that would mean for the asm. 

I'm also not sure why this only reproduces with avx512, but I'm 
putting a conservative fix in for now to avoid the crash. 

Also, if both sides of an add are zexted, shouldn't we shrink that add?

https://bugs.llvm.org/show_bug.cgi?id=32316

Added:
    llvm/trunk/test/CodeGen/X86/avx512-adc-sbb.ll
Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=298107&r1=298106&r2=298107&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Mar 17 12:27:31 2017
@@ -34266,12 +34266,16 @@ static SDValue combineAddOrSubToADCOrSBB
     std::swap(X, Y);
 
   // Look through a one-use zext.
-  if (Y.getOpcode() == ISD::ZERO_EXTEND && Y.hasOneUse())
+  bool PeekedThroughZext = false;
+  if (Y.getOpcode() == ISD::ZERO_EXTEND && Y.hasOneUse()) {
     Y = Y.getOperand(0);
+    PeekedThroughZext = true;
+  }
 
   // If this is an add, canonicalize a setcc operand to the RHS.
   // TODO: Incomplete? What if both sides are setcc?
-  if (!IsSub && X.getOpcode() == X86ISD::SETCC &&
+  // TODO: Should we allow peeking through a zext of the other operand?
+  if (!IsSub && !PeekedThroughZext && X.getOpcode() == X86ISD::SETCC &&
       Y.getOpcode() != X86ISD::SETCC)
     std::swap(X, Y);
 

Added: llvm/trunk/test/CodeGen/X86/avx512-adc-sbb.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-adc-sbb.ll?rev=298107&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512-adc-sbb.ll (added)
+++ llvm/trunk/test/CodeGen/X86/avx512-adc-sbb.ll Fri Mar 17 12:27:31 2017
@@ -0,0 +1,27 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=avx512f %s -o - | FileCheck %s
+
+; This asserted because we didn't account for a zext of a non-SETCC node:
+; https://bugs.llvm.org/show_bug.cgi?id=32316
+
+define i8 @PR32316(i8 %t1, i32 %t5, i8 %t8)  {
+; CHECK-LABEL: PR32316:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    xorl %eax, %eax
+; CHECK-NEXT:    testb %dil, %dil
+; CHECK-NEXT:    sete %al
+; CHECK-NEXT:    cmpl %esi, %eax
+; CHECK-NEXT:    seta %al
+; CHECK-NEXT:    cmpb $1, %dl
+; CHECK-NEXT:    sbbb $-1, %al
+; CHECK-NEXT:    retq
+  %t2 = icmp eq i8 %t1, 0
+  %t3 = zext i1 %t2 to i32
+  %t6 = icmp ugt i32 %t3, %t5
+  %t7 = zext i1 %t6 to i8
+  %t9 = icmp ne i8 %t8, 0
+  %t10 = zext i1 %t9 to i8
+  %t11 = add i8 %t7, %t10
+  ret i8 %t11
+}
+