[PATCH] D31081: [ARM] ScheduleDAGRRList::DelayForLiveRegsBottomUp must consider OptionalDefs

Javed Absar via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Mar 17 09:39:05 PDT 2017


javed.absar added a comment.

Hi : 
Please add a commit message explaining the problem you are trying to solve e.g.
"when checking for registers that are live to avoid scheduling - optional definitions such as ARM instructions which can set condition code if 's' bit is set - are mis-diagnosed"
It may be better to write the test as an mir-test, as it would illustrate the problem more clearly.
Thanks.


https://reviews.llvm.org/D31081





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