[llvm] r297925 - CodeGen: BlockPlacement: Reduce TriangleChainCount to 2
Kyle Butt via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 15 18:32:29 PDT 2017
Author: iteratee
Date: Wed Mar 15 20:32:29 2017
New Revision: 297925
URL: http://llvm.org/viewvc/llvm-project?rev=297925&view=rev
Log:
CodeGen: BlockPlacement: Reduce TriangleChainCount to 2
This produces a 1% speedup on an important internal Google benchmark
(protocol buffers), with no other regressions in google or in the llvm
test-suite. Only 5 targets in the entire llvm test-suite are affected,
and on those 5 targets the size increase is 0.027%
Modified:
llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp
llvm/trunk/test/CodeGen/Mips/llvm-ir/ashr.ll
llvm/trunk/test/CodeGen/Mips/llvm-ir/lshr.ll
llvm/trunk/test/CodeGen/Mips/llvm-ir/shl.ll
Modified: llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp?rev=297925&r1=297924&r2=297925&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp Wed Mar 15 20:32:29 2017
@@ -149,7 +149,7 @@ static cl::opt<unsigned> TriangleChainCo
"triangle-chain-count",
cl::desc("Number of triangle-shaped-CFG's that need to be in a row for the "
"triangle tail duplication heuristic to kick in. 0 to disable."),
- cl::init(3),
+ cl::init(2),
cl::Hidden);
extern cl::opt<unsigned> StaticLikelyProb;
Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/ashr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/ashr.ll?rev=297925&r1=297924&r2=297925&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/llvm-ir/ashr.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/llvm-ir/ashr.ll Wed Mar 15 20:32:29 2017
@@ -83,20 +83,23 @@ entry:
; M2: srav $[[T0:[0-9]+]], $4, $7
; M2: andi $[[T1:[0-9]+]], $7, 32
- ; M2: bnez $[[T1]], $[[BB0:BB[0-9_]+]]
+ ; M2: beqz $[[T1]], $[[BB0:BB[0-9_]+]]
; M2: move $3, $[[T0]]
+ ; M2: bnez $[[T1]], $[[BB1:BB[0-9_]+]]
+ ; M2: nop
+ ; M2: $[[EXIT:BB[0-9_]+]]:
+ ; M2: jr $ra
+ ; M2: nop
+ ; M2: $[[BB0]]:
; M2: srlv $[[T2:[0-9]+]], $5, $7
; M2: not $[[T3:[0-9]+]], $7
; M2: sll $[[T4:[0-9]+]], $4, 1
; M2: sllv $[[T5:[0-9]+]], $[[T4]], $[[T3]]
+ ; M2: beqz $[[T1]], $[[EXIT]]
; M2: or $3, $[[T3]], $[[T2]]
- ; M2: $[[BB0]]:
- ; M2: beqz $[[T1]], $[[BB1:BB[0-9_]+]]
- ; M2: nop
- ; M2: sra $2, $4, 31
; M2: $[[BB1]]:
; M2: jr $ra
- ; M2: nop
+ ; M2: sra $2, $4, 31
; 32R1-R5: srlv $[[T0:[0-9]+]], $5, $7
; 32R1-R5: not $[[T1:[0-9]+]], $7
@@ -169,20 +172,23 @@ entry:
; M3: sll $[[T0:[0-9]+]], $7, 0
; M3: dsrav $[[T1:[0-9]+]], $4, $7
; M3: andi $[[T2:[0-9]+]], $[[T0]], 64
- ; M3: bnez $[[T3:[0-9]+]], [[BB0:.LBB[0-9_]+]]
+ ; M3: beqz $[[T3:[0-9]+]], [[BB0:.LBB[0-9_]+]]
; M3: move $3, $[[T1]]
+ ; M3: bnez $[[T3]], [[BB1:.LBB[0-9_]+]]
+ ; M3: nop
+ ; M3: [[EXIT:.LBB[0-9_]+]]:
+ ; M3: jr $ra
+ ; M3: nop
+ ; M3: [[BB0]]:
; M3: dsrlv $[[T4:[0-9]+]], $5, $7
; M3: dsll $[[T5:[0-9]+]], $4, 1
; M3: not $[[T6:[0-9]+]], $[[T0]]
; M3: dsllv $[[T7:[0-9]+]], $[[T5]], $[[T6]]
+ ; M3: beqz $[[T3]], [[EXIT]]
; M3: or $3, $[[T7]], $[[T4]]
- ; M3: [[BB0]]:
- ; M3: beqz $[[T3]], [[BB1:.LBB[0-9_]+]]
- ; M3: nop
- ; M3: dsra $2, $4, 63
; M3: [[BB1]]:
; M3: jr $ra
- ; M3: nop
+ ; M3: dsra $2, $4, 63
; GP64-NOT-R6: dsrlv $[[T0:[0-9]+]], $5, $7
; GP64-NOT-R6: dsll $[[T1:[0-9]+]], $4, 1
Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/lshr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/lshr.ll?rev=297925&r1=297924&r2=297925&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/llvm-ir/lshr.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/llvm-ir/lshr.ll Wed Mar 15 20:32:29 2017
@@ -81,20 +81,24 @@ entry:
; M2: srlv $[[T0:[0-9]+]], $4, $7
; M2: andi $[[T1:[0-9]+]], $7, 32
- ; M2: bnez $[[T1]], $[[BB0:BB[0-9_]+]]
+ ; M2: beqz $[[T1]], $[[BB0:BB[0-9_]+]]
; M2: move $3, $[[T0]]
+ ; M2: beqz $[[T1]], $[[BB1:BB[0-9_]+]]
+ ; M2: addiu $2, $zero, 0
+ ; M2: $[[EXIT:BB[0-9_]+]]:
+ ; M2: jr $ra
+ ; M2: nop
+ ; M2: $[[BB0]]:
; M2: srlv $[[T2:[0-9]+]], $5, $7
; M2: not $[[T3:[0-9]+]], $7
; M2: sll $[[T4:[0-9]+]], $4, 1
; M2: sllv $[[T5:[0-9]+]], $[[T4]], $[[T3]]
; M2: or $3, $[[T3]], $[[T2]]
- ; M2: $[[BB0]]:
- ; M2: bnez $[[T1]], $[[BB1:BB[0-9_]+]]
+ ; M2: bnez $[[T1]], $[[EXIT:BB[0-9_]+]]
; M2: addiu $2, $zero, 0
- ; M2: move $2, $[[T0]]
; M2: $[[BB1]]:
; M2: jr $ra
- ; M2: nop
+ ; M2: move $2, $[[T0]]
; 32R1-R5: srlv $[[T0:[0-9]+]], $5, $7
; 32R1-R5: not $[[T1:[0-9]+]], $7
@@ -160,20 +164,24 @@ entry:
; M3: sll $[[T0:[0-9]+]], $7, 0
; M3: dsrlv $[[T1:[0-9]+]], $4, $7
; M3: andi $[[T2:[0-9]+]], $[[T0]], 64
- ; M3: bnez $[[T3:[0-9]+]], [[BB0:\.LBB[0-9_]+]]
+ ; M3: beqz $[[T3:[0-9]+]], [[BB0:\.LBB[0-9_]+]]
; M3: move $3, $[[T1]]
+ ; M3: beqz $[[T3]], [[BB1:\.LBB[0-9_]+]]
+ ; M3: daddiu $2, $zero, 0
+ ; M3: [[EXIT:\.LBB[0-9_]+]]:
+ ; M3: jr $ra
+ ; M3: nop
+ ; M3: [[BB0]]:
; M3: dsrlv $[[T4:[0-9]+]], $5, $7
; M3: dsll $[[T5:[0-9]+]], $4, 1
; M3: not $[[T6:[0-9]+]], $[[T0]]
; M3: dsllv $[[T7:[0-9]+]], $[[T5]], $[[T6]]
; M3: or $3, $[[T7]], $[[T4]]
- ; M3: [[BB0]]:
- ; M3: bnez $[[T3]], [[BB1:\.LBB[0-9_]+]]
+ ; M3: bnez $[[T3]], [[EXIT]]
; M3: daddiu $2, $zero, 0
- ; M3: move $2, $[[T1]]
; M3: [[BB1]]:
; M3: jr $ra
- ; M3: nop
+ ; M3: move $2, $[[T1]]
; GP64-NOT-R6: dsrlv $[[T0:[0-9]+]], $5, $7
; GP64-NOT-R6: dsll $[[T1:[0-9]+]], $4, 1
Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/shl.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/shl.ll?rev=297925&r1=297924&r2=297925&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/llvm-ir/shl.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/llvm-ir/shl.ll Wed Mar 15 20:32:29 2017
@@ -97,20 +97,24 @@ entry:
; M2: sllv $[[T0:[0-9]+]], $5, $7
; M2: andi $[[T1:[0-9]+]], $7, 32
- ; M2: bnez $[[T1]], $[[BB0:BB[0-9_]+]]
+ ; M2: beqz $[[T1]], $[[BB0:BB[0-9_]+]]
; M2: move $2, $[[T0]]
+ ; M2: beqz $[[T1]], $[[BB1:BB[0-9_]+]]
+ ; M2: addiu $3, $zero, 0
+ ; M2: $[[EXIT:BB[0-9_]+]]:
+ ; M2: jr $ra
+ ; M2: nop
+ ; M2: $[[BB0]]:
; M2: sllv $[[T2:[0-9]+]], $4, $7
; M2: not $[[T3:[0-9]+]], $7
; M2: srl $[[T4:[0-9]+]], $5, 1
; M2: srlv $[[T5:[0-9]+]], $[[T4]], $[[T3]]
; M2: or $2, $[[T2]], $[[T3]]
- ; M2: $[[BB0]]:
- ; M2: bnez $[[T1]], $[[BB1:BB[0-9_]+]]
+ ; M2: bnez $[[T1]], $[[EXIT]]
; M2: addiu $3, $zero, 0
- ; M2: move $3, $[[T0]]
; M2: $[[BB1]]:
; M2: jr $ra
- ; M2: nop
+ ; M2: move $3, $[[T0]]
; 32R1-R5: sllv $[[T0:[0-9]+]], $4, $7
; 32R1-R5: not $[[T1:[0-9]+]], $7
@@ -176,20 +180,24 @@ entry:
; M3: sll $[[T0:[0-9]+]], $7, 0
; M3: dsllv $[[T1:[0-9]+]], $5, $7
; M3: andi $[[T2:[0-9]+]], $[[T0]], 64
- ; M3: bnez $[[T3:[0-9]+]], [[BB0:\.LBB[0-9_]+]]
+ ; M3: beqz $[[T3:[0-9]+]], [[BB0:\.LBB[0-9_]+]]
; M3: move $2, $[[T1]]
+ ; M3: beqz $[[T3]], [[BB1:\.LBB[0-9_]+]]
+ ; M3: daddiu $3, $zero, 0
+ ; M3: [[EXIT:\.LBB[0-9_]+]]:
+ ; M3: jr $ra
+ ; M3: nop
+ ; M3: [[BB0]]:
; M3: dsllv $[[T4:[0-9]+]], $4, $7
; M3: dsrl $[[T5:[0-9]+]], $5, 1
; M3: not $[[T6:[0-9]+]], $[[T0]]
; M3: dsrlv $[[T7:[0-9]+]], $[[T5]], $[[T6]]
; M3: or $2, $[[T4]], $[[T7]]
- ; M3: [[BB0]]:
- ; M3: bnez $[[T3]], [[BB1:\.LBB[0-9_]+]]
+ ; M3: bnez $[[T3]], [[EXIT]]
; M3: daddiu $3, $zero, 0
- ; M3: move $3, $[[T1]]
; M3: [[BB1]]:
; M3: jr $ra
- ; M3: nop
+ ; M3: move $3, $[[T1]]
; GP64-NOT-R6: dsllv $[[T0:[0-9]+]], $4, $7
; GP64-NOT-R6: dsrl $[[T1:[0-9]+]], $5, 1
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