[llvm] r297849 - [PowerPC][Altivec] Add mfvrd and mffprd extended mnemonic
Nemanja Ivanovic via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 15 09:04:53 PDT 2017
Author: nemanjai
Date: Wed Mar 15 11:04:53 2017
New Revision: 297849
URL: http://llvm.org/viewvc/llvm-project?rev=297849&view=rev
Log:
[PowerPC][Altivec] Add mfvrd and mffprd extended mnemonic
mfvrd and mffprd are both alias to mfvrsd.
This patch enables correct parsing of the aliases, but we still emit a mfvrsd.
Committing on behalf of brunoalr (Bruno Rosa).
Differential Revision: https://reviews.llvm.org/D29177
Modified:
llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td
llvm/trunk/test/CodeGen/PowerPC/bitcasts-direct-move.ll
llvm/trunk/test/CodeGen/PowerPC/fp-int-conversions-direct-moves.ll
llvm/trunk/test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll
llvm/trunk/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll
llvm/trunk/test/MC/Disassembler/PowerPC/vsx.txt
llvm/trunk/test/MC/PowerPC/vsx.s
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td?rev=297849&r1=297848&r2=297849&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td Wed Mar 15 11:04:53 2017
@@ -1410,6 +1410,11 @@ let Predicates = [HasDirectMove] in {
"mfvsrd $rA, $XT", IIC_VecGeneral,
[(set i64:$rA, (PPCmfvsr f64:$XT))]>,
Requires<[In64BitMode]>;
+ let isCodeGenOnly = 1 in
+ def MFVRD : XX1_RS6_RD5_XO<31, 51, (outs g8rc:$rA), (ins vrrc:$XT),
+ "mfvsrd $rA, $XT", IIC_VecGeneral,
+ []>,
+ Requires<[In64BitMode]>;
def MFVSRWZ : XX1_RS6_RD5_XO<31, 115, (outs gprc:$rA), (ins vsfrc:$XT),
"mfvsrwz $rA, $XT", IIC_VecGeneral,
[(set i32:$rA, (PPCmfvsr f64:$XT))]>;
@@ -1440,6 +1445,13 @@ let Predicates = [IsISA3_0, HasDirectMov
} // IsISA3_0, HasDirectMove
} // UseVSXReg = 1
+// We want to parse this from asm, but we don't want to emit this as it would
+// be emitted with a VSX reg. So leave Emit = 0 here.
+def : InstAlias<"mfvrd $rA, $XT",
+ (MFVRD g8rc:$rA, vrrc:$XT), 0>;
+def : InstAlias<"mffprd $rA, $src",
+ (MFVSRD g8rc:$rA, f8rc:$src)>;
+
/* Direct moves of various widths from GPR's into VSR's. Each move lines
the value up into element 0 (both BE and LE). Namely, entities smaller than
a doubleword are shifted left and moved for BE. For LE, they're moved, then
Modified: llvm/trunk/test/CodeGen/PowerPC/bitcasts-direct-move.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/bitcasts-direct-move.ll?rev=297849&r1=297848&r2=297849&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/bitcasts-direct-move.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/bitcasts-direct-move.ll Wed Mar 15 11:04:53 2017
@@ -20,7 +20,7 @@ entry:
ret i64 %0
; CHECK-P7: stxsdx 1,
; CHECK-P7: ld 3,
-; CHECK: mfvsrd 3, 1
+; CHECK: mffprd 3, 1
}
define float @i32tof32(i32 signext %a) {
@@ -60,7 +60,7 @@ entry:
ret i64 %0
; CHECK-P7: stxsdx 1,
; CHECK-P7: ld 3,
-; CHECK: mfvsrd 3, 1
+; CHECK: mffprd 3, 1
}
define float @i32utof32(i32 zeroext %a) {
Modified: llvm/trunk/test/CodeGen/PowerPC/fp-int-conversions-direct-moves.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/fp-int-conversions-direct-moves.ll?rev=297849&r1=297848&r2=297849&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/fp-int-conversions-direct-moves.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/fp-int-conversions-direct-moves.ll Wed Mar 15 11:04:53 2017
@@ -323,7 +323,7 @@ entry:
ret i64 %conv
; CHECK-LABEL: @_Z7testllff
; CHECK: xscvdpsxds [[CONVREG13:[0-9]+]], 1
-; CHECK: mfvsrd 3, [[CONVREG13]]
+; CHECK: mffprd 3, [[CONVREG13]]
}
; Function Attrs: nounwind
@@ -349,7 +349,7 @@ entry:
ret i64 %conv
; CHECK-LABEL: @_Z7testlldd
; CHECK: xscvdpsxds [[CONVREG14:[0-9]+]], 1
-; CHECK: mfvsrd 3, [[CONVREG14]]
+; CHECK: mffprd 3, [[CONVREG14]]
}
; Function Attrs: nounwind
@@ -375,7 +375,7 @@ entry:
ret i64 %conv
; CHECK-LABEL: @_Z8testullff
; CHECK: xscvdpuxds [[CONVREG15:[0-9]+]], 1
-; CHECK: mfvsrd 3, [[CONVREG15]]
+; CHECK: mffprd 3, [[CONVREG15]]
}
; Function Attrs: nounwind
@@ -401,7 +401,7 @@ entry:
ret i64 %conv
; CHECK-LABEL: @_Z8testulldd
; CHECK: xscvdpuxds [[CONVREG16:[0-9]+]], 1
-; CHECK: mfvsrd 3, [[CONVREG16]]
+; CHECK: mffprd 3, [[CONVREG16]]
}
; Function Attrs: nounwind
Modified: llvm/trunk/test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll?rev=297849&r1=297848&r2=297849&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll Wed Mar 15 11:04:53 2017
@@ -19,8 +19,8 @@ entry:
; PPC64: blr
; PPC64-P8-LABEL: test_abs:
-; PPC64-P8-DAG: mfvsrd [[LO:[0-9]+]], 2
-; PPC64-P8-DAG: mfvsrd [[HI:[0-9]+]], 1
+; PPC64-P8-DAG: mffprd [[LO:[0-9]+]], 2
+; PPC64-P8-DAG: mffprd [[HI:[0-9]+]], 1
; PPC64-P8-DAG: rldicr [[FLIP_BIT:[0-9]+]], [[HI]], 0, 0
; PPC64-P8-DAG: xor 3, [[HI]], [[FLIP_BIT]]
; PPC64-P8-DAG: xor 4, [[LO]], [[FLIP_BIT]]
@@ -59,8 +59,8 @@ entry:
; PPC64: blr
; PPC64-P8-LABEL: test_neg:
-; PPC64-P8-DAG: mfvsrd [[LO:[0-9]+]], 2
-; PPC64-P8-DAG: mfvsrd [[HI:[0-9]+]], 1
+; PPC64-P8-DAG: mffprd [[LO:[0-9]+]], 2
+; PPC64-P8-DAG: mffprd [[HI:[0-9]+]], 1
; PPC64-P8-DAG: li [[IMM1:[0-9]+]], 1
; PPC64-P8-DAG: sldi [[FLIP_BIT:[0-9]+]], [[IMM1]], 63
; PPC64-P8-NOT: BARRIER
@@ -101,7 +101,7 @@ entry:
; PPC64: blr
; PPC64-P8-LABEL: test_copysign:
-; PPC64-P8-DAG: mfvsrd [[X_HI:[0-9]+]], 1
+; PPC64-P8-DAG: mffprd [[X_HI:[0-9]+]], 1
; PPC64-P8-DAG: li [[HI_TMP:[0-9]+]], 16399
; PPC64-P8-DAG: sldi [[CST_HI:[0-9]+]], [[HI_TMP]], 48
; PPC64-P8-DAG: li [[LO_TMP:[0-9]+]], 3019
Modified: llvm/trunk/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll?rev=297849&r1=297848&r2=297849&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll Wed Mar 15 11:04:53 2017
@@ -7,13 +7,10 @@
@d = common global double 0.000000e+00, align 8
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define <16 x i8> @buildc(i8 zeroext %a) {
entry:
- %a.addr = alloca i8, align 1
- store i8 %a, i8* %a.addr, align 1
- %0 = load i8, i8* %a.addr, align 1
- %splat.splatinsert = insertelement <16 x i8> undef, i8 %0, i32 0
+ %splat.splatinsert = insertelement <16 x i8> undef, i8 %a, i32 0
%splat.splat = shufflevector <16 x i8> %splat.splatinsert, <16 x i8> undef, <16 x i32> zeroinitializer
ret <16 x i8> %splat.splat
; CHECK: sldi [[REG1:[0-9]+]], 3, 56
@@ -22,13 +19,10 @@ entry:
; CHECK-LE: xxswapd {{[0-9]+}}, [[REG1]]
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define <8 x i16> @builds(i16 zeroext %a) {
entry:
- %a.addr = alloca i16, align 2
- store i16 %a, i16* %a.addr, align 2
- %0 = load i16, i16* %a.addr, align 2
- %splat.splatinsert = insertelement <8 x i16> undef, i16 %0, i32 0
+ %splat.splatinsert = insertelement <8 x i16> undef, i16 %a, i32 0
%splat.splat = shufflevector <8 x i16> %splat.splatinsert, <8 x i16> undef, <8 x i32> zeroinitializer
ret <8 x i16> %splat.splat
; CHECK: sldi [[REG1:[0-9]+]], 3, 48
@@ -37,13 +31,10 @@ entry:
; CHECK-LE: xxswapd {{[0-9]+}}, [[REG1]]
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define <4 x i32> @buildi(i32 zeroext %a) {
entry:
- %a.addr = alloca i32, align 4
- store i32 %a, i32* %a.addr, align 4
- %0 = load i32, i32* %a.addr, align 4
- %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0
+ %splat.splatinsert = insertelement <4 x i32> undef, i32 %a, i32 0
%splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
ret <4 x i32> %splat.splat
; CHECK: mtvsrwz [[REG1:[0-9]+]], 3
@@ -52,13 +43,10 @@ entry:
; CHECK-LE: xxspltw 34, [[REG1]]
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define <2 x i64> @buildl(i64 %a) {
entry:
- %a.addr = alloca i64, align 8
- store i64 %a, i64* %a.addr, align 8
- %0 = load i64, i64* %a.addr, align 8
- %splat.splatinsert = insertelement <2 x i64> undef, i64 %0, i32 0
+ %splat.splatinsert = insertelement <2 x i64> undef, i64 %a, i32 0
%splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
ret <2 x i64> %splat.splat
; CHECK: mtvsrd {{[0-9]+}}, 3
@@ -66,13 +54,10 @@ entry:
; CHECK-LE: xxspltd 34, [[REG1]], 0
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define <4 x float> @buildf(float %a) {
entry:
- %a.addr = alloca float, align 4
- store float %a, float* %a.addr, align 4
- %0 = load float, float* %a.addr, align 4
- %splat.splatinsert = insertelement <4 x float> undef, float %0, i32 0
+ %splat.splatinsert = insertelement <4 x float> undef, float %a, i32 0
%splat.splat = shufflevector <4 x float> %splat.splatinsert, <4 x float> undef, <4 x i32> zeroinitializer
ret <4 x float> %splat.splat
; CHECK: xscvdpspn [[REG1:[0-9]+]], 1
@@ -83,8 +68,8 @@ entry:
; The optimization to remove stack operations from PPCDAGToDAGISel::Select
; should still trigger for v2f64, producing an lxvdsx.
-; Function Attrs: nounwind
-define <2 x double> @buildd() #0 {
+; Function Attrs: norecurse nounwind readonly
+define <2 x double> @buildd() {
entry:
%0 = load double, double* @d, align 8
%splat.splatinsert = insertelement <2 x double> undef, double %0, i32 0
@@ -96,13 +81,10 @@ entry:
; CHECK-LE: lxvdsx 34, 0, [[REG1]]
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define signext i8 @getsc0(<16 x i8> %vsc) {
entry:
- %vsc.addr = alloca <16 x i8>, align 16
- store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16
- %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16
- %vecext = extractelement <16 x i8> %0, i32 0
+ %vecext = extractelement <16 x i8> %vsc, i32 0
ret i8 %vecext
; CHECK-LABEL: @getsc0
; CHECK: mfvsrd 3, 34
@@ -114,13 +96,10 @@ entry:
; CHECK-LE: extsb 3, 3
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define signext i8 @getsc1(<16 x i8> %vsc) {
entry:
- %vsc.addr = alloca <16 x i8>, align 16
- store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16
- %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16
- %vecext = extractelement <16 x i8> %0, i32 1
+ %vecext = extractelement <16 x i8> %vsc, i32 1
ret i8 %vecext
; CHECK-LABEL: @getsc1
; CHECK: mfvsrd 3, 34
@@ -132,13 +111,10 @@ entry:
; CHECK-LE: extsb 3, 3
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define signext i8 @getsc2(<16 x i8> %vsc) {
entry:
- %vsc.addr = alloca <16 x i8>, align 16
- store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16
- %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16
- %vecext = extractelement <16 x i8> %0, i32 2
+ %vecext = extractelement <16 x i8> %vsc, i32 2
ret i8 %vecext
; CHECK-LABEL: @getsc2
; CHECK: mfvsrd 3, 34
@@ -150,13 +126,10 @@ entry:
; CHECK-LE: extsb 3, 3
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define signext i8 @getsc3(<16 x i8> %vsc) {
entry:
- %vsc.addr = alloca <16 x i8>, align 16
- store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16
- %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16
- %vecext = extractelement <16 x i8> %0, i32 3
+ %vecext = extractelement <16 x i8> %vsc, i32 3
ret i8 %vecext
; CHECK-LABEL: @getsc3
; CHECK: mfvsrd 3, 34
@@ -168,13 +141,10 @@ entry:
; CHECK-LE: extsb 3, 3
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define signext i8 @getsc4(<16 x i8> %vsc) {
entry:
- %vsc.addr = alloca <16 x i8>, align 16
- store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16
- %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16
- %vecext = extractelement <16 x i8> %0, i32 4
+ %vecext = extractelement <16 x i8> %vsc, i32 4
ret i8 %vecext
; CHECK-LABEL: @getsc4
; CHECK: mfvsrd 3, 34
@@ -186,13 +156,10 @@ entry:
; CHECK-LE: extsb 3, 3
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define signext i8 @getsc5(<16 x i8> %vsc) {
entry:
- %vsc.addr = alloca <16 x i8>, align 16
- store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16
- %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16
- %vecext = extractelement <16 x i8> %0, i32 5
+ %vecext = extractelement <16 x i8> %vsc, i32 5
ret i8 %vecext
; CHECK-LABEL: @getsc5
; CHECK: mfvsrd 3, 34
@@ -204,13 +171,10 @@ entry:
; CHECK-LE: extsb 3, 3
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define signext i8 @getsc6(<16 x i8> %vsc) {
entry:
- %vsc.addr = alloca <16 x i8>, align 16
- store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16
- %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16
- %vecext = extractelement <16 x i8> %0, i32 6
+ %vecext = extractelement <16 x i8> %vsc, i32 6
ret i8 %vecext
; CHECK-LABEL: @getsc6
; CHECK: mfvsrd 3, 34
@@ -222,13 +186,10 @@ entry:
; CHECK-LE: extsb 3, 3
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define signext i8 @getsc7(<16 x i8> %vsc) {
entry:
- %vsc.addr = alloca <16 x i8>, align 16
- store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16
- %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16
- %vecext = extractelement <16 x i8> %0, i32 7
+ %vecext = extractelement <16 x i8> %vsc, i32 7
ret i8 %vecext
; CHECK-LABEL: @getsc7
; CHECK: mfvsrd 3, 34
@@ -240,13 +201,10 @@ entry:
; CHECK-LE: extsb 3, 3
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define signext i8 @getsc8(<16 x i8> %vsc) {
entry:
- %vsc.addr = alloca <16 x i8>, align 16
- store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16
- %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16
- %vecext = extractelement <16 x i8> %0, i32 8
+ %vecext = extractelement <16 x i8> %vsc, i32 8
ret i8 %vecext
; CHECK-LABEL: @getsc8
; CHECK: mfvsrd 3,
@@ -258,13 +216,10 @@ entry:
; CHECK-LE: extsb 3, 3
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define signext i8 @getsc9(<16 x i8> %vsc) {
entry:
- %vsc.addr = alloca <16 x i8>, align 16
- store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16
- %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16
- %vecext = extractelement <16 x i8> %0, i32 9
+ %vecext = extractelement <16 x i8> %vsc, i32 9
ret i8 %vecext
; CHECK-LABEL: @getsc9
; CHECK: mfvsrd 3,
@@ -276,13 +231,10 @@ entry:
; CHECK-LE: extsb 3, 3
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define signext i8 @getsc10(<16 x i8> %vsc) {
entry:
- %vsc.addr = alloca <16 x i8>, align 16
- store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16
- %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16
- %vecext = extractelement <16 x i8> %0, i32 10
+ %vecext = extractelement <16 x i8> %vsc, i32 10
ret i8 %vecext
; CHECK-LABEL: @getsc10
; CHECK: mfvsrd 3,
@@ -294,13 +246,10 @@ entry:
; CHECK-LE: extsb 3, 3
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define signext i8 @getsc11(<16 x i8> %vsc) {
entry:
- %vsc.addr = alloca <16 x i8>, align 16
- store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16
- %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16
- %vecext = extractelement <16 x i8> %0, i32 11
+ %vecext = extractelement <16 x i8> %vsc, i32 11
ret i8 %vecext
; CHECK-LABEL: @getsc11
; CHECK: mfvsrd 3,
@@ -312,13 +261,10 @@ entry:
; CHECK-LE: extsb 3, 3
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define signext i8 @getsc12(<16 x i8> %vsc) {
entry:
- %vsc.addr = alloca <16 x i8>, align 16
- store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16
- %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16
- %vecext = extractelement <16 x i8> %0, i32 12
+ %vecext = extractelement <16 x i8> %vsc, i32 12
ret i8 %vecext
; CHECK-LABEL: @getsc12
; CHECK: mfvsrd 3,
@@ -330,13 +276,10 @@ entry:
; CHECK-LE: extsb 3, 3
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define signext i8 @getsc13(<16 x i8> %vsc) {
entry:
- %vsc.addr = alloca <16 x i8>, align 16
- store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16
- %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16
- %vecext = extractelement <16 x i8> %0, i32 13
+ %vecext = extractelement <16 x i8> %vsc, i32 13
ret i8 %vecext
; CHECK-LABEL: @getsc13
; CHECK: mfvsrd 3,
@@ -348,13 +291,10 @@ entry:
; CHECK-LE: extsb 3, 3
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define signext i8 @getsc14(<16 x i8> %vsc) {
entry:
- %vsc.addr = alloca <16 x i8>, align 16
- store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16
- %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16
- %vecext = extractelement <16 x i8> %0, i32 14
+ %vecext = extractelement <16 x i8> %vsc, i32 14
ret i8 %vecext
; CHECK-LABEL: @getsc14
; CHECK: mfvsrd 3,
@@ -366,13 +306,10 @@ entry:
; CHECK-LE: extsb 3, 3
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define signext i8 @getsc15(<16 x i8> %vsc) {
entry:
- %vsc.addr = alloca <16 x i8>, align 16
- store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16
- %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16
- %vecext = extractelement <16 x i8> %0, i32 15
+ %vecext = extractelement <16 x i8> %vsc, i32 15
ret i8 %vecext
; CHECK-LABEL: @getsc15
; CHECK: mfvsrd 3,
@@ -383,13 +320,10 @@ entry:
; CHECK-LE: extsb 3, 3
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define zeroext i8 @getuc0(<16 x i8> %vuc) {
entry:
- %vuc.addr = alloca <16 x i8>, align 16
- store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16
- %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16
- %vecext = extractelement <16 x i8> %0, i32 0
+ %vecext = extractelement <16 x i8> %vuc, i32 0
ret i8 %vecext
; CHECK-LABEL: @getuc0
; CHECK: mfvsrd 3, 34
@@ -400,13 +334,10 @@ entry:
; CHECK-LE: clrldi 3, 3, 56
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define zeroext i8 @getuc1(<16 x i8> %vuc) {
entry:
- %vuc.addr = alloca <16 x i8>, align 16
- store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16
- %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16
- %vecext = extractelement <16 x i8> %0, i32 1
+ %vecext = extractelement <16 x i8> %vuc, i32 1
ret i8 %vecext
; CHECK-LABEL: @getuc1
; CHECK: mfvsrd 3, 34
@@ -418,13 +349,10 @@ entry:
; CHECK-LE: clrldi 3, 3, 56
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define zeroext i8 @getuc2(<16 x i8> %vuc) {
entry:
- %vuc.addr = alloca <16 x i8>, align 16
- store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16
- %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16
- %vecext = extractelement <16 x i8> %0, i32 2
+ %vecext = extractelement <16 x i8> %vuc, i32 2
ret i8 %vecext
; CHECK-LABEL: @getuc2
; CHECK: mfvsrd 3, 34
@@ -436,13 +364,10 @@ entry:
; CHECK-LE: clrldi 3, 3, 56
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define zeroext i8 @getuc3(<16 x i8> %vuc) {
entry:
- %vuc.addr = alloca <16 x i8>, align 16
- store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16
- %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16
- %vecext = extractelement <16 x i8> %0, i32 3
+ %vecext = extractelement <16 x i8> %vuc, i32 3
ret i8 %vecext
; CHECK-LABEL: @getuc3
; CHECK: mfvsrd 3, 34
@@ -454,13 +379,10 @@ entry:
; CHECK-LE: clrldi 3, 3, 56
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define zeroext i8 @getuc4(<16 x i8> %vuc) {
entry:
- %vuc.addr = alloca <16 x i8>, align 16
- store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16
- %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16
- %vecext = extractelement <16 x i8> %0, i32 4
+ %vecext = extractelement <16 x i8> %vuc, i32 4
ret i8 %vecext
; CHECK-LABEL: @getuc4
; CHECK: mfvsrd 3, 34
@@ -472,13 +394,10 @@ entry:
; CHECK-LE: clrldi 3, 3, 56
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define zeroext i8 @getuc5(<16 x i8> %vuc) {
entry:
- %vuc.addr = alloca <16 x i8>, align 16
- store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16
- %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16
- %vecext = extractelement <16 x i8> %0, i32 5
+ %vecext = extractelement <16 x i8> %vuc, i32 5
ret i8 %vecext
; CHECK-LABEL: @getuc5
; CHECK: mfvsrd 3, 34
@@ -490,13 +409,10 @@ entry:
; CHECK-LE: clrldi 3, 3, 56
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define zeroext i8 @getuc6(<16 x i8> %vuc) {
entry:
- %vuc.addr = alloca <16 x i8>, align 16
- store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16
- %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16
- %vecext = extractelement <16 x i8> %0, i32 6
+ %vecext = extractelement <16 x i8> %vuc, i32 6
ret i8 %vecext
; CHECK-LABEL: @getuc6
; CHECK: mfvsrd 3, 34
@@ -508,13 +424,10 @@ entry:
; CHECK-LE: clrldi 3, 3, 56
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define zeroext i8 @getuc7(<16 x i8> %vuc) {
entry:
- %vuc.addr = alloca <16 x i8>, align 16
- store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16
- %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16
- %vecext = extractelement <16 x i8> %0, i32 7
+ %vecext = extractelement <16 x i8> %vuc, i32 7
ret i8 %vecext
; CHECK-LABEL: @getuc7
; CHECK: mfvsrd 3, 34
@@ -525,13 +438,10 @@ entry:
; CHECK-LE: clrldi 3, 3, 56
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define zeroext i8 @getuc8(<16 x i8> %vuc) {
entry:
- %vuc.addr = alloca <16 x i8>, align 16
- store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16
- %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16
- %vecext = extractelement <16 x i8> %0, i32 8
+ %vecext = extractelement <16 x i8> %vuc, i32 8
ret i8 %vecext
; CHECK-LABEL: @getuc8
; CHECK: mfvsrd 3,
@@ -542,13 +452,10 @@ entry:
; CHECK-LE: clrldi 3, 3, 56
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define zeroext i8 @getuc9(<16 x i8> %vuc) {
entry:
- %vuc.addr = alloca <16 x i8>, align 16
- store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16
- %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16
- %vecext = extractelement <16 x i8> %0, i32 9
+ %vecext = extractelement <16 x i8> %vuc, i32 9
ret i8 %vecext
; CHECK-LABEL: @getuc9
; CHECK: mfvsrd 3,
@@ -560,13 +467,10 @@ entry:
; CHECK-LE: clrldi 3, 3, 56
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define zeroext i8 @getuc10(<16 x i8> %vuc) {
entry:
- %vuc.addr = alloca <16 x i8>, align 16
- store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16
- %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16
- %vecext = extractelement <16 x i8> %0, i32 10
+ %vecext = extractelement <16 x i8> %vuc, i32 10
ret i8 %vecext
; CHECK-LABEL: @getuc10
; CHECK: mfvsrd 3,
@@ -578,13 +482,10 @@ entry:
; CHECK-LE: clrldi 3, 3, 56
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define zeroext i8 @getuc11(<16 x i8> %vuc) {
entry:
- %vuc.addr = alloca <16 x i8>, align 16
- store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16
- %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16
- %vecext = extractelement <16 x i8> %0, i32 11
+ %vecext = extractelement <16 x i8> %vuc, i32 11
ret i8 %vecext
; CHECK-LABEL: @getuc11
; CHECK: mfvsrd 3,
@@ -596,13 +497,10 @@ entry:
; CHECK-LE: clrldi 3, 3, 56
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define zeroext i8 @getuc12(<16 x i8> %vuc) {
entry:
- %vuc.addr = alloca <16 x i8>, align 16
- store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16
- %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16
- %vecext = extractelement <16 x i8> %0, i32 12
+ %vecext = extractelement <16 x i8> %vuc, i32 12
ret i8 %vecext
; CHECK-LABEL: @getuc12
; CHECK: mfvsrd 3,
@@ -614,13 +512,10 @@ entry:
; CHECK-LE: clrldi 3, 3, 56
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define zeroext i8 @getuc13(<16 x i8> %vuc) {
entry:
- %vuc.addr = alloca <16 x i8>, align 16
- store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16
- %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16
- %vecext = extractelement <16 x i8> %0, i32 13
+ %vecext = extractelement <16 x i8> %vuc, i32 13
ret i8 %vecext
; CHECK-LABEL: @getuc13
; CHECK: mfvsrd 3,
@@ -632,13 +527,10 @@ entry:
; CHECK-LE: clrldi 3, 3, 56
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define zeroext i8 @getuc14(<16 x i8> %vuc) {
entry:
- %vuc.addr = alloca <16 x i8>, align 16
- store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16
- %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16
- %vecext = extractelement <16 x i8> %0, i32 14
+ %vecext = extractelement <16 x i8> %vuc, i32 14
ret i8 %vecext
; CHECK-LABEL: @getuc14
; CHECK: mfvsrd 3,
@@ -650,13 +542,10 @@ entry:
; CHECK-LE: clrldi 3, 3, 56
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define zeroext i8 @getuc15(<16 x i8> %vuc) {
entry:
- %vuc.addr = alloca <16 x i8>, align 16
- store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16
- %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16
- %vecext = extractelement <16 x i8> %0, i32 15
+ %vecext = extractelement <16 x i8> %vuc, i32 15
ret i8 %vecext
; CHECK-LABEL: @getuc15
; CHECK: mfvsrd 3,
@@ -667,16 +556,10 @@ entry:
; CHECK-LE: clrldi 3, 3, 56
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define signext i8 @getvelsc(<16 x i8> %vsc, i32 signext %i) {
entry:
- %vsc.addr = alloca <16 x i8>, align 16
- %i.addr = alloca i32, align 4
- store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16
- store i32 %i, i32* %i.addr, align 4
- %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16
- %1 = load i32, i32* %i.addr, align 4
- %vecext = extractelement <16 x i8> %0, i32 %1
+ %vecext = extractelement <16 x i8> %vsc, i32 %i
ret i8 %vecext
; CHECK-LABEL: @getvelsc
; CHECK-DAG: andi. [[ANDI:[0-9]+]], {{[0-9]+}}, 8
@@ -701,16 +584,10 @@ entry:
; CHECK-DAG-LE: extsb 3, 3
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define zeroext i8 @getveluc(<16 x i8> %vuc, i32 signext %i) {
entry:
- %vuc.addr = alloca <16 x i8>, align 16
- %i.addr = alloca i32, align 4
- store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16
- store i32 %i, i32* %i.addr, align 4
- %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16
- %1 = load i32, i32* %i.addr, align 4
- %vecext = extractelement <16 x i8> %0, i32 %1
+ %vecext = extractelement <16 x i8> %vuc, i32 %i
ret i8 %vecext
; CHECK-LABEL: @getveluc
; CHECK-DAG: andi. [[ANDI:[0-9]+]], {{[0-9]+}}, 8
@@ -735,13 +612,10 @@ entry:
; CHECK-DAG-LE: clrldi 3, 3, 56
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define signext i16 @getss0(<8 x i16> %vss) {
entry:
- %vss.addr = alloca <8 x i16>, align 16
- store <8 x i16> %vss, <8 x i16>* %vss.addr, align 16
- %0 = load <8 x i16>, <8 x i16>* %vss.addr, align 16
- %vecext = extractelement <8 x i16> %0, i32 0
+ %vecext = extractelement <8 x i16> %vss, i32 0
ret i16 %vecext
; CHECK-LABEL: @getss0
; CHECK: mfvsrd 3, 34
@@ -753,13 +627,10 @@ entry:
; CHECK-LE: extsh 3, 3
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define signext i16 @getss1(<8 x i16> %vss) {
entry:
- %vss.addr = alloca <8 x i16>, align 16
- store <8 x i16> %vss, <8 x i16>* %vss.addr, align 16
- %0 = load <8 x i16>, <8 x i16>* %vss.addr, align 16
- %vecext = extractelement <8 x i16> %0, i32 1
+ %vecext = extractelement <8 x i16> %vss, i32 1
ret i16 %vecext
; CHECK-LABEL: @getss1
; CHECK: mfvsrd 3, 34
@@ -771,13 +642,10 @@ entry:
; CHECK-LE: extsh 3, 3
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define signext i16 @getss2(<8 x i16> %vss) {
entry:
- %vss.addr = alloca <8 x i16>, align 16
- store <8 x i16> %vss, <8 x i16>* %vss.addr, align 16
- %0 = load <8 x i16>, <8 x i16>* %vss.addr, align 16
- %vecext = extractelement <8 x i16> %0, i32 2
+ %vecext = extractelement <8 x i16> %vss, i32 2
ret i16 %vecext
; CHECK-LABEL: @getss2
; CHECK: mfvsrd 3, 34
@@ -789,13 +657,10 @@ entry:
; CHECK-LE: extsh 3, 3
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define signext i16 @getss3(<8 x i16> %vss) {
entry:
- %vss.addr = alloca <8 x i16>, align 16
- store <8 x i16> %vss, <8 x i16>* %vss.addr, align 16
- %0 = load <8 x i16>, <8 x i16>* %vss.addr, align 16
- %vecext = extractelement <8 x i16> %0, i32 3
+ %vecext = extractelement <8 x i16> %vss, i32 3
ret i16 %vecext
; CHECK-LABEL: @getss3
; CHECK: mfvsrd 3, 34
@@ -807,13 +672,10 @@ entry:
; CHECK-LE: extsh 3, 3
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define signext i16 @getss4(<8 x i16> %vss) {
entry:
- %vss.addr = alloca <8 x i16>, align 16
- store <8 x i16> %vss, <8 x i16>* %vss.addr, align 16
- %0 = load <8 x i16>, <8 x i16>* %vss.addr, align 16
- %vecext = extractelement <8 x i16> %0, i32 4
+ %vecext = extractelement <8 x i16> %vss, i32 4
ret i16 %vecext
; CHECK-LABEL: @getss4
; CHECK: mfvsrd 3,
@@ -825,13 +687,10 @@ entry:
; CHECK-LE: extsh 3, 3
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define signext i16 @getss5(<8 x i16> %vss) {
entry:
- %vss.addr = alloca <8 x i16>, align 16
- store <8 x i16> %vss, <8 x i16>* %vss.addr, align 16
- %0 = load <8 x i16>, <8 x i16>* %vss.addr, align 16
- %vecext = extractelement <8 x i16> %0, i32 5
+ %vecext = extractelement <8 x i16> %vss, i32 5
ret i16 %vecext
; CHECK-LABEL: @getss5
; CHECK: mfvsrd 3,
@@ -843,13 +702,10 @@ entry:
; CHECK-LE: extsh 3, 3
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define signext i16 @getss6(<8 x i16> %vss) {
entry:
- %vss.addr = alloca <8 x i16>, align 16
- store <8 x i16> %vss, <8 x i16>* %vss.addr, align 16
- %0 = load <8 x i16>, <8 x i16>* %vss.addr, align 16
- %vecext = extractelement <8 x i16> %0, i32 6
+ %vecext = extractelement <8 x i16> %vss, i32 6
ret i16 %vecext
; CHECK-LABEL: @getss6
; CHECK: mfvsrd 3,
@@ -861,13 +717,10 @@ entry:
; CHECK-LE: extsh 3, 3
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define signext i16 @getss7(<8 x i16> %vss) {
entry:
- %vss.addr = alloca <8 x i16>, align 16
- store <8 x i16> %vss, <8 x i16>* %vss.addr, align 16
- %0 = load <8 x i16>, <8 x i16>* %vss.addr, align 16
- %vecext = extractelement <8 x i16> %0, i32 7
+ %vecext = extractelement <8 x i16> %vss, i32 7
ret i16 %vecext
; CHECK-LABEL: @getss7
; CHECK: mfvsrd 3,
@@ -878,13 +731,10 @@ entry:
; CHECK-LE: extsh 3, 3
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define zeroext i16 @getus0(<8 x i16> %vus) {
entry:
- %vus.addr = alloca <8 x i16>, align 16
- store <8 x i16> %vus, <8 x i16>* %vus.addr, align 16
- %0 = load <8 x i16>, <8 x i16>* %vus.addr, align 16
- %vecext = extractelement <8 x i16> %0, i32 0
+ %vecext = extractelement <8 x i16> %vus, i32 0
ret i16 %vecext
; CHECK-LABEL: @getus0
; CHECK: mfvsrd 3, 34
@@ -895,13 +745,10 @@ entry:
; CHECK-LE: clrldi 3, 3, 48
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define zeroext i16 @getus1(<8 x i16> %vus) {
entry:
- %vus.addr = alloca <8 x i16>, align 16
- store <8 x i16> %vus, <8 x i16>* %vus.addr, align 16
- %0 = load <8 x i16>, <8 x i16>* %vus.addr, align 16
- %vecext = extractelement <8 x i16> %0, i32 1
+ %vecext = extractelement <8 x i16> %vus, i32 1
ret i16 %vecext
; CHECK-LABEL: @getus1
; CHECK: mfvsrd 3, 34
@@ -913,13 +760,10 @@ entry:
; CHECK-LE: clrldi 3, 3, 48
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define zeroext i16 @getus2(<8 x i16> %vus) {
entry:
- %vus.addr = alloca <8 x i16>, align 16
- store <8 x i16> %vus, <8 x i16>* %vus.addr, align 16
- %0 = load <8 x i16>, <8 x i16>* %vus.addr, align 16
- %vecext = extractelement <8 x i16> %0, i32 2
+ %vecext = extractelement <8 x i16> %vus, i32 2
ret i16 %vecext
; CHECK-LABEL: @getus2
; CHECK: mfvsrd 3, 34
@@ -931,13 +775,10 @@ entry:
; CHECK-LE: clrldi 3, 3, 48
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define zeroext i16 @getus3(<8 x i16> %vus) {
entry:
- %vus.addr = alloca <8 x i16>, align 16
- store <8 x i16> %vus, <8 x i16>* %vus.addr, align 16
- %0 = load <8 x i16>, <8 x i16>* %vus.addr, align 16
- %vecext = extractelement <8 x i16> %0, i32 3
+ %vecext = extractelement <8 x i16> %vus, i32 3
ret i16 %vecext
; CHECK-LABEL: @getus3
; CHECK: mfvsrd 3, 34
@@ -948,13 +789,10 @@ entry:
; CHECK-LE: clrldi 3, 3, 48
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define zeroext i16 @getus4(<8 x i16> %vus) {
entry:
- %vus.addr = alloca <8 x i16>, align 16
- store <8 x i16> %vus, <8 x i16>* %vus.addr, align 16
- %0 = load <8 x i16>, <8 x i16>* %vus.addr, align 16
- %vecext = extractelement <8 x i16> %0, i32 4
+ %vecext = extractelement <8 x i16> %vus, i32 4
ret i16 %vecext
; CHECK-LABEL: @getus4
; CHECK: mfvsrd 3,
@@ -965,13 +803,10 @@ entry:
; CHECK-LE: clrldi 3, 3, 48
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define zeroext i16 @getus5(<8 x i16> %vus) {
entry:
- %vus.addr = alloca <8 x i16>, align 16
- store <8 x i16> %vus, <8 x i16>* %vus.addr, align 16
- %0 = load <8 x i16>, <8 x i16>* %vus.addr, align 16
- %vecext = extractelement <8 x i16> %0, i32 5
+ %vecext = extractelement <8 x i16> %vus, i32 5
ret i16 %vecext
; CHECK-LABEL: @getus5
; CHECK: mfvsrd 3,
@@ -983,13 +818,10 @@ entry:
; CHECK-LE: clrldi 3, 3, 48
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define zeroext i16 @getus6(<8 x i16> %vus) {
entry:
- %vus.addr = alloca <8 x i16>, align 16
- store <8 x i16> %vus, <8 x i16>* %vus.addr, align 16
- %0 = load <8 x i16>, <8 x i16>* %vus.addr, align 16
- %vecext = extractelement <8 x i16> %0, i32 6
+ %vecext = extractelement <8 x i16> %vus, i32 6
ret i16 %vecext
; CHECK-LABEL: @getus6
; CHECK: mfvsrd 3,
@@ -1001,13 +833,10 @@ entry:
; CHECK-LE: clrldi 3, 3, 48
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define zeroext i16 @getus7(<8 x i16> %vus) {
entry:
- %vus.addr = alloca <8 x i16>, align 16
- store <8 x i16> %vus, <8 x i16>* %vus.addr, align 16
- %0 = load <8 x i16>, <8 x i16>* %vus.addr, align 16
- %vecext = extractelement <8 x i16> %0, i32 7
+ %vecext = extractelement <8 x i16> %vus, i32 7
ret i16 %vecext
; CHECK-LABEL: @getus7
; CHECK: mfvsrd 3,
@@ -1018,16 +847,10 @@ entry:
; CHECK-LE: clrldi 3, 3, 48
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define signext i16 @getvelss(<8 x i16> %vss, i32 signext %i) {
entry:
- %vss.addr = alloca <8 x i16>, align 16
- %i.addr = alloca i32, align 4
- store <8 x i16> %vss, <8 x i16>* %vss.addr, align 16
- store i32 %i, i32* %i.addr, align 4
- %0 = load <8 x i16>, <8 x i16>* %vss.addr, align 16
- %1 = load i32, i32* %i.addr, align 4
- %vecext = extractelement <8 x i16> %0, i32 %1
+ %vecext = extractelement <8 x i16> %vss, i32 %i
ret i16 %vecext
; CHECK-LABEL: @getvelss
; CHECK-DAG: andi. [[ANDI:[0-9]+]], {{[0-9]+}}, 4
@@ -1054,16 +877,10 @@ entry:
; CHECK-DAG-LE: extsh 3, 3
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define zeroext i16 @getvelus(<8 x i16> %vus, i32 signext %i) {
entry:
- %vus.addr = alloca <8 x i16>, align 16
- %i.addr = alloca i32, align 4
- store <8 x i16> %vus, <8 x i16>* %vus.addr, align 16
- store i32 %i, i32* %i.addr, align 4
- %0 = load <8 x i16>, <8 x i16>* %vus.addr, align 16
- %1 = load i32, i32* %i.addr, align 4
- %vecext = extractelement <8 x i16> %0, i32 %1
+ %vecext = extractelement <8 x i16> %vus, i32 %i
ret i16 %vecext
; CHECK-LABEL: @getvelus
; CHECK-DAG: andi. [[ANDI:[0-9]+]], {{[0-9]+}}, 4
@@ -1090,13 +907,10 @@ entry:
; CHECK-DAG-LE: clrldi 3, 3, 48
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define signext i32 @getsi0(<4 x i32> %vsi) {
entry:
- %vsi.addr = alloca <4 x i32>, align 16
- store <4 x i32> %vsi, <4 x i32>* %vsi.addr, align 16
- %0 = load <4 x i32>, <4 x i32>* %vsi.addr, align 16
- %vecext = extractelement <4 x i32> %0, i32 0
+ %vecext = extractelement <4 x i32> %vsi, i32 0
ret i32 %vecext
; CHECK-LABEL: @getsi0
; CHECK: xxsldwi [[SHL:[0-9]+]], 34, 34, 3
@@ -1108,13 +922,10 @@ entry:
; CHECK-LE: extsw 3, 3
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define signext i32 @getsi1(<4 x i32> %vsi) {
entry:
- %vsi.addr = alloca <4 x i32>, align 16
- store <4 x i32> %vsi, <4 x i32>* %vsi.addr, align 16
- %0 = load <4 x i32>, <4 x i32>* %vsi.addr, align 16
- %vecext = extractelement <4 x i32> %0, i32 1
+ %vecext = extractelement <4 x i32> %vsi, i32 1
ret i32 %vecext
; CHECK-LABEL: @getsi1
; CHECK: mfvsrwz 3, 34
@@ -1125,13 +936,10 @@ entry:
; CHECK-LE: extsw 3, 3
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define signext i32 @getsi2(<4 x i32> %vsi) {
entry:
- %vsi.addr = alloca <4 x i32>, align 16
- store <4 x i32> %vsi, <4 x i32>* %vsi.addr, align 16
- %0 = load <4 x i32>, <4 x i32>* %vsi.addr, align 16
- %vecext = extractelement <4 x i32> %0, i32 2
+ %vecext = extractelement <4 x i32> %vsi, i32 2
ret i32 %vecext
; CHECK-LABEL: @getsi2
; CHECK: xxsldwi [[SHL:[0-9]+]], 34, 34, 1
@@ -1142,13 +950,10 @@ entry:
; CHECK-LE: extsw 3, 3
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define signext i32 @getsi3(<4 x i32> %vsi) {
entry:
- %vsi.addr = alloca <4 x i32>, align 16
- store <4 x i32> %vsi, <4 x i32>* %vsi.addr, align 16
- %0 = load <4 x i32>, <4 x i32>* %vsi.addr, align 16
- %vecext = extractelement <4 x i32> %0, i32 3
+ %vecext = extractelement <4 x i32> %vsi, i32 3
ret i32 %vecext
; CHECK-LABEL: @getsi3
; CHECK: xxswapd [[SHL:[0-9]+]], 34
@@ -1160,13 +965,10 @@ entry:
; CHECK-LE: extsw 3, 3
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define zeroext i32 @getui0(<4 x i32> %vui) {
entry:
- %vui.addr = alloca <4 x i32>, align 16
- store <4 x i32> %vui, <4 x i32>* %vui.addr, align 16
- %0 = load <4 x i32>, <4 x i32>* %vui.addr, align 16
- %vecext = extractelement <4 x i32> %0, i32 0
+ %vecext = extractelement <4 x i32> %vui, i32 0
ret i32 %vecext
; CHECK-LABEL: @getui0
; CHECK: xxsldwi [[SHL:[0-9]+]], 34, 34, 3
@@ -1178,13 +980,10 @@ entry:
; CHECK-LE: clrldi 3, 3, 32
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define zeroext i32 @getui1(<4 x i32> %vui) {
entry:
- %vui.addr = alloca <4 x i32>, align 16
- store <4 x i32> %vui, <4 x i32>* %vui.addr, align 16
- %0 = load <4 x i32>, <4 x i32>* %vui.addr, align 16
- %vecext = extractelement <4 x i32> %0, i32 1
+ %vecext = extractelement <4 x i32> %vui, i32 1
ret i32 %vecext
; CHECK-LABEL: @getui1
; CHECK: mfvsrwz 3, 34
@@ -1195,13 +994,10 @@ entry:
; CHECK-LE: clrldi 3, 3, 32
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define zeroext i32 @getui2(<4 x i32> %vui) {
entry:
- %vui.addr = alloca <4 x i32>, align 16
- store <4 x i32> %vui, <4 x i32>* %vui.addr, align 16
- %0 = load <4 x i32>, <4 x i32>* %vui.addr, align 16
- %vecext = extractelement <4 x i32> %0, i32 2
+ %vecext = extractelement <4 x i32> %vui, i32 2
ret i32 %vecext
; CHECK-LABEL: @getui2
; CHECK: xxsldwi [[SHL:[0-9]+]], 34, 34, 1
@@ -1212,13 +1008,10 @@ entry:
; CHECK-LE: clrldi 3, 3, 32
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define zeroext i32 @getui3(<4 x i32> %vui) {
entry:
- %vui.addr = alloca <4 x i32>, align 16
- store <4 x i32> %vui, <4 x i32>* %vui.addr, align 16
- %0 = load <4 x i32>, <4 x i32>* %vui.addr, align 16
- %vecext = extractelement <4 x i32> %0, i32 3
+ %vecext = extractelement <4 x i32> %vui, i32 3
ret i32 %vecext
; CHECK-LABEL: @getui3
; CHECK: xxswapd [[SHL:[0-9]+]], 34
@@ -1230,45 +1023,30 @@ entry:
; CHECK-LE: clrldi 3, 3, 32
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define signext i32 @getvelsi(<4 x i32> %vsi, i32 signext %i) {
entry:
- %vsi.addr = alloca <4 x i32>, align 16
- %i.addr = alloca i32, align 4
- store <4 x i32> %vsi, <4 x i32>* %vsi.addr, align 16
- store i32 %i, i32* %i.addr, align 4
- %0 = load <4 x i32>, <4 x i32>* %vsi.addr, align 16
- %1 = load i32, i32* %i.addr, align 4
- %vecext = extractelement <4 x i32> %0, i32 %1
+ %vecext = extractelement <4 x i32> %vsi, i32 %i
ret i32 %vecext
; CHECK-LABEL: @getvelsi
; CHECK-LE-LABEL: @getvelsi
; FIXME: add check patterns when variable element extraction is implemented
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define zeroext i32 @getvelui(<4 x i32> %vui, i32 signext %i) {
entry:
- %vui.addr = alloca <4 x i32>, align 16
- %i.addr = alloca i32, align 4
- store <4 x i32> %vui, <4 x i32>* %vui.addr, align 16
- store i32 %i, i32* %i.addr, align 4
- %0 = load <4 x i32>, <4 x i32>* %vui.addr, align 16
- %1 = load i32, i32* %i.addr, align 4
- %vecext = extractelement <4 x i32> %0, i32 %1
+ %vecext = extractelement <4 x i32> %vui, i32 %i
ret i32 %vecext
; CHECK-LABEL: @getvelui
; CHECK-LE-LABEL: @getvelui
; FIXME: add check patterns when variable element extraction is implemented
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define i64 @getsl0(<2 x i64> %vsl) {
entry:
- %vsl.addr = alloca <2 x i64>, align 16
- store <2 x i64> %vsl, <2 x i64>* %vsl.addr, align 16
- %0 = load <2 x i64>, <2 x i64>* %vsl.addr, align 16
- %vecext = extractelement <2 x i64> %0, i32 0
+ %vecext = extractelement <2 x i64> %vsl, i32 0
ret i64 %vecext
; CHECK-LABEL: @getsl0
; CHECK: mfvsrd 3, 34
@@ -1277,13 +1055,10 @@ entry:
; CHECK-LE: mfvsrd 3, [[SWP]]
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define i64 @getsl1(<2 x i64> %vsl) {
entry:
- %vsl.addr = alloca <2 x i64>, align 16
- store <2 x i64> %vsl, <2 x i64>* %vsl.addr, align 16
- %0 = load <2 x i64>, <2 x i64>* %vsl.addr, align 16
- %vecext = extractelement <2 x i64> %0, i32 1
+ %vecext = extractelement <2 x i64> %vsl, i32 1
ret i64 %vecext
; CHECK-LABEL: @getsl1
; CHECK: xxswapd [[SWP:[0-9]+]], 34
@@ -1292,13 +1067,10 @@ entry:
; CHECK-LE: mfvsrd 3, 34
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define i64 @getul0(<2 x i64> %vul) {
entry:
- %vul.addr = alloca <2 x i64>, align 16
- store <2 x i64> %vul, <2 x i64>* %vul.addr, align 16
- %0 = load <2 x i64>, <2 x i64>* %vul.addr, align 16
- %vecext = extractelement <2 x i64> %0, i32 0
+ %vecext = extractelement <2 x i64> %vul, i32 0
ret i64 %vecext
; CHECK-LABEL: @getul0
; CHECK: mfvsrd 3, 34
@@ -1307,13 +1079,10 @@ entry:
; CHECK-LE: mfvsrd 3, [[SWP]]
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define i64 @getul1(<2 x i64> %vul) {
entry:
- %vul.addr = alloca <2 x i64>, align 16
- store <2 x i64> %vul, <2 x i64>* %vul.addr, align 16
- %0 = load <2 x i64>, <2 x i64>* %vul.addr, align 16
- %vecext = extractelement <2 x i64> %0, i32 1
+ %vecext = extractelement <2 x i64> %vul, i32 1
ret i64 %vecext
; CHECK-LABEL: @getul1
; CHECK: xxswapd [[SWP:[0-9]+]], 34
@@ -1322,45 +1091,30 @@ entry:
; CHECK-LE: mfvsrd 3, 34
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define i64 @getvelsl(<2 x i64> %vsl, i32 signext %i) {
entry:
- %vsl.addr = alloca <2 x i64>, align 16
- %i.addr = alloca i32, align 4
- store <2 x i64> %vsl, <2 x i64>* %vsl.addr, align 16
- store i32 %i, i32* %i.addr, align 4
- %0 = load <2 x i64>, <2 x i64>* %vsl.addr, align 16
- %1 = load i32, i32* %i.addr, align 4
- %vecext = extractelement <2 x i64> %0, i32 %1
+ %vecext = extractelement <2 x i64> %vsl, i32 %i
ret i64 %vecext
; CHECK-LABEL: @getvelsl
; CHECK-LE-LABEL: @getvelsl
; FIXME: add check patterns when variable element extraction is implemented
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define i64 @getvelul(<2 x i64> %vul, i32 signext %i) {
entry:
- %vul.addr = alloca <2 x i64>, align 16
- %i.addr = alloca i32, align 4
- store <2 x i64> %vul, <2 x i64>* %vul.addr, align 16
- store i32 %i, i32* %i.addr, align 4
- %0 = load <2 x i64>, <2 x i64>* %vul.addr, align 16
- %1 = load i32, i32* %i.addr, align 4
- %vecext = extractelement <2 x i64> %0, i32 %1
+ %vecext = extractelement <2 x i64> %vul, i32 %i
ret i64 %vecext
; CHECK-LABEL: @getvelul
; CHECK-LE-LABEL: @getvelul
; FIXME: add check patterns when variable element extraction is implemented
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define float @getf0(<4 x float> %vf) {
entry:
- %vf.addr = alloca <4 x float>, align 16
- store <4 x float> %vf, <4 x float>* %vf.addr, align 16
- %0 = load <4 x float>, <4 x float>* %vf.addr, align 16
- %vecext = extractelement <4 x float> %0, i32 0
+ %vecext = extractelement <4 x float> %vf, i32 0
ret float %vecext
; CHECK-LABEL: @getf0
; CHECK: xscvspdpn 1, 34
@@ -1369,13 +1123,10 @@ entry:
; CHECK-LE: xscvspdpn 1, [[SHL]]
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define float @getf1(<4 x float> %vf) {
entry:
- %vf.addr = alloca <4 x float>, align 16
- store <4 x float> %vf, <4 x float>* %vf.addr, align 16
- %0 = load <4 x float>, <4 x float>* %vf.addr, align 16
- %vecext = extractelement <4 x float> %0, i32 1
+ %vecext = extractelement <4 x float> %vf, i32 1
ret float %vecext
; CHECK-LABEL: @getf1
; CHECK: xxsldwi [[SHL:[0-9]+]], 34, 34, 1
@@ -1385,13 +1136,10 @@ entry:
; CHECK-LE: xscvspdpn 1, [[SHL]]
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define float @getf2(<4 x float> %vf) {
entry:
- %vf.addr = alloca <4 x float>, align 16
- store <4 x float> %vf, <4 x float>* %vf.addr, align 16
- %0 = load <4 x float>, <4 x float>* %vf.addr, align 16
- %vecext = extractelement <4 x float> %0, i32 2
+ %vecext = extractelement <4 x float> %vf, i32 2
ret float %vecext
; CHECK-LABEL: @getf2
; CHECK: xxswapd [[SHL:[0-9]+]], 34
@@ -1401,13 +1149,10 @@ entry:
; CHECK-LE: xscvspdpn 1, [[SHL]]
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define float @getf3(<4 x float> %vf) {
entry:
- %vf.addr = alloca <4 x float>, align 16
- store <4 x float> %vf, <4 x float>* %vf.addr, align 16
- %0 = load <4 x float>, <4 x float>* %vf.addr, align 16
- %vecext = extractelement <4 x float> %0, i32 3
+ %vecext = extractelement <4 x float> %vf, i32 3
ret float %vecext
; CHECK-LABEL: @getf3
; CHECK: xxsldwi [[SHL:[0-9]+]], 34, 34, 3
@@ -1416,29 +1161,20 @@ entry:
; CHECK-LE: xscvspdpn 1, 34
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define float @getvelf(<4 x float> %vf, i32 signext %i) {
entry:
- %vf.addr = alloca <4 x float>, align 16
- %i.addr = alloca i32, align 4
- store <4 x float> %vf, <4 x float>* %vf.addr, align 16
- store i32 %i, i32* %i.addr, align 4
- %0 = load <4 x float>, <4 x float>* %vf.addr, align 16
- %1 = load i32, i32* %i.addr, align 4
- %vecext = extractelement <4 x float> %0, i32 %1
+ %vecext = extractelement <4 x float> %vf, i32 %i
ret float %vecext
; CHECK-LABEL: @getvelf
; CHECK-LE-LABEL: @getvelf
; FIXME: add check patterns when variable element extraction is implemented
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define double @getd0(<2 x double> %vd) {
entry:
- %vd.addr = alloca <2 x double>, align 16
- store <2 x double> %vd, <2 x double>* %vd.addr, align 16
- %0 = load <2 x double>, <2 x double>* %vd.addr, align 16
- %vecext = extractelement <2 x double> %0, i32 0
+ %vecext = extractelement <2 x double> %vd, i32 0
ret double %vecext
; CHECK-LABEL: @getd0
; CHECK: xxlor 1, 34, 34
@@ -1446,13 +1182,10 @@ entry:
; CHECK-LE: xxswapd 1, 34
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define double @getd1(<2 x double> %vd) {
entry:
- %vd.addr = alloca <2 x double>, align 16
- store <2 x double> %vd, <2 x double>* %vd.addr, align 16
- %0 = load <2 x double>, <2 x double>* %vd.addr, align 16
- %vecext = extractelement <2 x double> %0, i32 1
+ %vecext = extractelement <2 x double> %vd, i32 1
ret double %vecext
; CHECK-LABEL: @getd1
; CHECK: xxswapd 1, 34
@@ -1460,16 +1193,10 @@ entry:
; CHECK-LE: xxlor 1, 34, 34
}
-; Function Attrs: nounwind
+; Function Attrs: norecurse nounwind readnone
define double @getveld(<2 x double> %vd, i32 signext %i) {
entry:
- %vd.addr = alloca <2 x double>, align 16
- %i.addr = alloca i32, align 4
- store <2 x double> %vd, <2 x double>* %vd.addr, align 16
- store i32 %i, i32* %i.addr, align 4
- %0 = load <2 x double>, <2 x double>* %vd.addr, align 16
- %1 = load i32, i32* %i.addr, align 4
- %vecext = extractelement <2 x double> %0, i32 %1
+ %vecext = extractelement <2 x double> %vd, i32 %i
ret double %vecext
; CHECK-LABEL: @getveld
; CHECK-LE-LABEL: @getveld
Modified: llvm/trunk/test/MC/Disassembler/PowerPC/vsx.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/PowerPC/vsx.txt?rev=297849&r1=297848&r2=297849&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/PowerPC/vsx.txt (original)
+++ llvm/trunk/test/MC/Disassembler/PowerPC/vsx.txt Wed Mar 15 11:04:53 2017
@@ -525,8 +525,8 @@
# CHECK: xxswapd 7, 63
0xf0 0xff 0xfa 0x56
-# CHECK: mfvsrd 3, 0
-0x7c 0x03 0x00 0x66
+# CHECK: mfvsrd 3, 40
+0x7d 0x03 0x00 0x67
# CHECK: mfvsrwz 5, 0
0x7c 0x05 0x00 0xe6
Modified: llvm/trunk/test/MC/PowerPC/vsx.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/PowerPC/vsx.s?rev=297849&r1=297848&r2=297849&view=diff
==============================================================================
--- llvm/trunk/test/MC/PowerPC/vsx.s (original)
+++ llvm/trunk/test/MC/PowerPC/vsx.s Wed Mar 15 11:04:53 2017
@@ -532,9 +532,12 @@
xxswapd 7, 63
# Move to/from VSR
-# CHECK-BE: mfvsrd 3, 0 # encoding: [0x7c,0x03,0x00,0x66]
-# CHECK-LE: mfvsrd 3, 0 # encoding: [0x66,0x00,0x03,0x7c]
- mfvsrd 3, 0
+# CHECK-BE: mfvsrd 3, 40 # encoding: [0x7d,0x03,0x00,0x67]
+# CHECK-LE: mfvsrd 3, 40 # encoding: [0x67,0x00,0x03,0x7d]
+ mfvsrd 3, 40
+# CHECK-BE: mfvsrd 3, 40 # encoding: [0x7d,0x03,0x00,0x67]
+# CHECK-LE: mfvsrd 3, 40 # encoding: [0x67,0x00,0x03,0x7d]
+ mfvrd 3, 8
# CHECK-BE: mfvsrwz 5, 0 # encoding: [0x7c,0x05,0x00,0xe6]
# CHECK-LE: mfvsrwz 5, 0 # encoding: [0xe6,0x00,0x05,0x7c]
mfvsrwz 5, 0
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