[PATCH] D30968: [AVX-512] WIP patch for fixing accidental uses of AH/BH/CH/DH after copies to/from mask registers

Craig Topper via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Mar 14 23:59:58 PDT 2017


craig.topper created this revision.

We've had several bugs(PR32256, PR32241) recently that resulted from usages of AH/BH/CH/DH either before or after a copy to/from a mask register.

This ultimately occurs because we create COPY_TO_REGCLASS with VK1 and GR8. Then in CopyToFromAsymmetricReg in X86InstrInfo we find a 32-bit super register for the GR8 to emit the KMOV with. But as these tests are demonstrating, its possible for the GR8 register to be a high register and we end up doing an accidental extra or insert from bits 15:8.

I made several attempts to fix this, but after the last test case that reopened PR32256, I think the best way forward is to stop making copies directly between mask registers and GR8/GR16. Instead I think we should restrict to only copies between mask registers and GR32/GR64 and use EXTRACT_SUBREG/INSERT_SUBREG to handle the conversion from GR32 to GR16/8 or vice versa.

Unfortunately, this complicates fastisel a bit more now to create the subreg extracts where we used to create GR8 copies. We can probably make a helper function to bring down the repitition.

This does result in KMOVD being used for copies when BWI is available because we don't know the original mask register size. This will cause a lot of deltas on tests because we have to split the checks for KMOVD vs KMOVW based on BWI.

This patch is a work in progress that I wanted to get feed back on. I still need to finish regenerating the rest of the ll test files. I also plan to clean up the formatting in the isel patterns.


https://reviews.llvm.org/D30968

Files:
  lib/Target/X86/X86FastISel.cpp
  lib/Target/X86/X86InstrAVX512.td
  lib/Target/X86/X86InstrInfo.cpp
  test/CodeGen/X86/vector-shuffle-128-v16.ll
  test/CodeGen/X86/vector-shuffle-256-v16.ll
  test/CodeGen/X86/vector-shuffle-256-v32.ll
  test/CodeGen/X86/vector-shuffle-512-v16.ll
  test/CodeGen/X86/vector-shuffle-combining-avx512bw.ll
  test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll
  test/CodeGen/X86/vector-shuffle-combining-avx512vbmi.ll
  test/CodeGen/X86/vector-shuffle-masked.ll
  test/CodeGen/X86/vector-shuffle-v1.ll

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