[llvm] r297745 - [Hexagon] Fix a condition in HexagonEarlyIfConv.cpp

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Tue Mar 14 10:21:33 2017
New Revision: 297745

URL: http://llvm.org/viewvc/llvm-project?rev=297745&view=rev
Log:
[Hexagon] Fix a condition in HexagonEarlyIfConv.cpp

This fixes llvm.org/PR32265.

Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonEarlyIfConv.cpp

Modified: llvm/trunk/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonEarlyIfConv.cpp?rev=297745&r1=297744&r2=297745&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonEarlyIfConv.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonEarlyIfConv.cpp Tue Mar 14 10:21:33 2017
@@ -482,7 +482,7 @@ unsigned HexagonEarlyIfConversion::compu
     const MachineOperand &RB = MI.getOperand(3);
     assert(RA.isReg() && RB.isReg());
     // Must have a MUX if the phi uses a subregister.
-    if (RA.getSubReg() != 0 || RA.getSubReg() != 0) {
+    if (RA.getSubReg() != 0 || RB.getSubReg() != 0) {
       Cost++;
       continue;
     }