[llvm] r297603 - [AVX-512] Add EVEX2VEX test cases for the cvt instructions fixed in r297599 and r297600.
Galina Kistanova via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 13 23:00:26 PDT 2017
It was an incremental build artifact. The test passes just fine after I
forced a clean build.
Thanks for taking a look, Craig.
http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/77
Thanks
Galina
On Mon, Mar 13, 2017 at 1:30 PM, Craig Topper <craig.topper at gmail.com>
wrote:
> I enabled expensive checks and I'm still unable to reproduce this locally.
> Any chance you can get the errors from the test?
>
> ~Craig
>
> On Mon, Mar 13, 2017 at 12:18 PM, Galina Kistanova <gkistanova at gmail.com>
> wrote:
>
>> Hello Craig,
>>
>> It look like one your recent commits broke one of our builders:
>>
>> http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensiv
>> e-checks-win/builds/61/steps/test-check-all/logs/stdio
>>
>> Failing Tests (1):
>> LLVM :: CodeGen/X86/evex-to-vex-compress.mir
>>
>> Please have a look at this?
>>
>> Thanks
>>
>> Galina
>>
>> On Sun, Mar 12, 2017 at 10:47 PM, Craig Topper via llvm-commits <
>> llvm-commits at lists.llvm.org> wrote:
>>
>>> Author: ctopper
>>> Date: Mon Mar 13 00:47:56 2017
>>> New Revision: 297603
>>>
>>> URL: http://llvm.org/viewvc/llvm-project?rev=297603&view=rev
>>> Log:
>>> [AVX-512] Add EVEX2VEX test cases for the cvt instructions fixed in
>>> r297599 and r297600.
>>>
>>> Modified:
>>> llvm/trunk/test/CodeGen/X86/evex-to-vex-compress.mir
>>>
>>> Modified: llvm/trunk/test/CodeGen/X86/evex-to-vex-compress.mir
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/
>>> X86/evex-to-vex-compress.mir?rev=297603&r1=297602&r2=297603&view=diff
>>> ============================================================
>>> ==================
>>> --- llvm/trunk/test/CodeGen/X86/evex-to-vex-compress.mir (original)
>>> +++ llvm/trunk/test/CodeGen/X86/evex-to-vex-compress.mir Mon Mar 13
>>> 00:47:56 2017
>>> @@ -2130,8 +2130,12 @@ body: |
>>> %edi = VCVTSD2SIZrr %xmm0
>>> ; CHECK: %xmm0 = VCVTSD2SSrm %xmm0, %rdi, 1, _, 0, _
>>> %xmm0 = VCVTSD2SSZrm %xmm0, %rdi, 1, _, 0, _
>>> + ; CHECK: %xmm0 = Int_VCVTSD2SSrm %xmm0, %rdi, 1, _, 0, _
>>> + %xmm0 = VCVTSD2SSZrm_Int %xmm0, %rdi, 1, _, 0, _
>>> ; CHECK: %xmm0 = VCVTSD2SSrr %xmm0, _
>>> %xmm0 = VCVTSD2SSZrr %xmm0, _
>>> + ; CHECK: %xmm0 = Int_VCVTSD2SSrr %xmm0, _
>>> + %xmm0 = VCVTSD2SSZrr_Int %xmm0, _
>>> ; CHECK: %xmm0 = VCVTSI2SDrm %xmm0, %rdi, 1, _, 0, _
>>> %xmm0 = VCVTSI2SDZrm %xmm0, %rdi, 1, _, 0, _
>>> ; CHECK: %xmm0 = Int_VCVTSI2SDrm %xmm0, %rdi, 1, _, 0, _
>>> @@ -2166,10 +2170,18 @@ body: |
>>> %xmm0 = VCVTSI642SSZrr_Int %xmm0, _
>>> ; CHECK: %xmm0 = VCVTSS2SDrm %xmm0, %rdi, 1, _, 0, _
>>> %xmm0 = VCVTSS2SDZrm %xmm0, %rdi, 1, _, 0, _
>>> + ; CHECK: %xmm0 = Int_VCVTSS2SDrm %xmm0, %rdi, 1, _, 0, _
>>> + %xmm0 = VCVTSS2SDZrm_Int %xmm0, %rdi, 1, _, 0, _
>>> ; CHECK: %xmm0 = VCVTSS2SDrr %xmm0, _
>>> %xmm0 = VCVTSS2SDZrr %xmm0, _
>>> + ; CHECK: %xmm0 = Int_VCVTSS2SDrr %xmm0, _
>>> + %xmm0 = VCVTSS2SDZrr_Int %xmm0, _
>>> + ; CHECK: %rdi = VCVTSS2SI64rm %rdi, %xmm0, 1, _, 0
>>> + %rdi = VCVTSS2SI64Zrm %rdi, %xmm0, 1, _, 0
>>> ; CHECK: %rdi = VCVTSS2SI64rr %xmm0
>>> %rdi = VCVTSS2SI64Zrr %xmm0
>>> + ; CHECK: %edi = VCVTSS2SIrm %rdi, %xmm0, 1, _, 0
>>> + %edi = VCVTSS2SIZrm %rdi, %xmm0, 1, _, 0
>>> ; CHECK: %edi = VCVTSS2SIrr %xmm0
>>> %edi = VCVTSS2SIZrr %xmm0
>>> ; CHECK: %rdi = VCVTTSD2SI64rm %rdi, %xmm0, 1, _, 0
>>> @@ -4438,8 +4450,12 @@ body: |
>>> %edi = VCVTSD2SIZrr %xmm16
>>> ; CHECK: %xmm16 = VCVTSD2SSZrm %xmm16, %rdi, 1, _, 0, _
>>> %xmm16 = VCVTSD2SSZrm %xmm16, %rdi, 1, _, 0, _
>>> + ; CHECK: %xmm16 = VCVTSD2SSZrm_Int %xmm16, %rdi, 1, _, 0, _
>>> + %xmm16 = VCVTSD2SSZrm_Int %xmm16, %rdi, 1, _, 0, _
>>> ; CHECK: %xmm16 = VCVTSD2SSZrr %xmm16, _
>>> %xmm16 = VCVTSD2SSZrr %xmm16, _
>>> + ; CHECK: %xmm16 = VCVTSD2SSZrr_Int %xmm16, _
>>> + %xmm16 = VCVTSD2SSZrr_Int %xmm16, _
>>> ; CHECK: %xmm16 = VCVTSI2SDZrm %xmm16, %rdi, 1, _, 0, _
>>> %xmm16 = VCVTSI2SDZrm %xmm16, %rdi, 1, _, 0, _
>>> ; CHECK: %xmm16 = VCVTSI2SDZrm_Int %xmm16, %rdi, 1, _, 0, _
>>> @@ -4474,8 +4490,12 @@ body: |
>>> %xmm16 = VCVTSI642SSZrr_Int %xmm16, _
>>> ; CHECK: %xmm16 = VCVTSS2SDZrm %xmm16, %rdi, 1, _, 0, _
>>> %xmm16 = VCVTSS2SDZrm %xmm16, %rdi, 1, _, 0, _
>>> + ; CHECK: %xmm16 = VCVTSS2SDZrm_Int %xmm16, %rdi, 1, _, 0, _
>>> + %xmm16 = VCVTSS2SDZrm_Int %xmm16, %rdi, 1, _, 0, _
>>> ; CHECK: %xmm16 = VCVTSS2SDZrr %xmm16, _
>>> %xmm16 = VCVTSS2SDZrr %xmm16, _
>>> + ; CHECK: %xmm16 = VCVTSS2SDZrr_Int %xmm16, _
>>> + %xmm16 = VCVTSS2SDZrr_Int %xmm16, _
>>> ; CHECK: %rdi = VCVTSS2SI64Zrm %rdi, %xmm16, 1, _, 0
>>> %rdi = VCVTSS2SI64Zrm %rdi, %xmm16, 1, _, 0
>>> ; CHECK: %rdi = VCVTSS2SI64Zrr %xmm16
>>>
>>>
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