[PATCH] D30833: [X86][MMX] Fix folding of shift value loads to cover whole 64-bits

[Andrea Di Biagio via Phabricator via llvm-commits]

andreadb accepted this revision.
andreadb added a comment.
This revision is now accepted and ready to land.

Looks good to me.

I agree that reverting the original commit is the right thing to do. All those mmx patterns were incorrectly bypassing the zeroing of the upper half of the shift count. 
The original shift count came from a MMX_MOVW2D node (which is equivalent to a cast from v2i32 to x86mmx of a BUILD_VECTOR that explicitly zeroes the second element).


Repository:
  rL LLVM

https://reviews.llvm.org/D30833