[PATCH] D30833: [X86][MMX] Fix folding of shift value loads to cover whole 64-bits

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.

https://reviews.llvm.org/rL230225 made the assumption that only the lower 32-bits of an MMX register load is used as a shift value, when in fact the whole 64-bits are reloaded and treated as a i64 to determine the shift value.

This patch reverts https://reviews.llvm.org/rL230225 to ensure that the whole 64-bits of memory are folded and ensures that the upper 32-bit are zero'd for cases where the shift value has come from a scalar source.

Found during fuzz testing.


Repository:
  rL LLVM

https://reviews.llvm.org/D30833

Files:
  lib/Target/X86/X86InstrFragmentsSIMD.td
  lib/Target/X86/X86InstrMMX.td
  test/CodeGen/X86/bitcast-mmx.ll
  test/CodeGen/X86/mmx-fold-load.ll

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