[PATCH] D30744: Improve machine schedulers for in-order processors

[Andrew Trick via llvm-commits]

I'm not looking at the source right now. But I'm thinking you should mark your instruction as begin and endGroup. Make sure the scheduler does the right thing. There maybe bugs. If so you can add a single issue flag that just sets both those flags. 

Sent from my iPhone

> On Mar 10, 2017, at 3:46 AM, Javed Absar via Phabricator <reviews at reviews.llvm.org> wrote:
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> javed.absar added a comment.
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> In https://reviews.llvm.org/D30744#696730, @atrick wrote:
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>> This feature was added to model issue constraints that were too awkward to model with resources. It's the most straightforward way to model single issue. Adding syntactic sugar to tablegen's machine model should be trivial.
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> 
> Can you please elaborate on this a bit so I can try to develop a patch to add this.  Thanks.
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> 
> https://reviews.llvm.org/D30744
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>