[PATCH] D30744: Improve machine schedulers for in-order processors

[Javed Absar via Phabricator via llvm-commits]

javed.absar created this revision.

This patch enables schedulers for in-order processors to specify instructions that 
cannot be issued with any other instructions.

Schedulers for such sub-targets can now attach ‘let SingleIssue = 1; // single issue ‘
to any general sched class or individual instruction. The scheduler then does not
 allow those instructions to be issued in same cycle with any other instruction. 
In this way, the scheduler models more accurately the real pipeline behavior.
Some partial out-of-order processors may also benefit from this.


https://reviews.llvm.org/D30744

Files:
  include/llvm/CodeGen/TargetSchedule.h
  include/llvm/MC/MCSchedule.h
  include/llvm/Target/TargetSchedule.td
  lib/CodeGen/MachineScheduler.cpp
  lib/CodeGen/TargetSchedule.cpp
  lib/Target/ARM/ARMScheduleR52.td
  test/CodeGen/ARM/single-issue-r52.mir
  utils/TableGen/SubtargetEmitter.cpp

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