[llvm] r297273 - [ARM] Split up lsl-zero test into two tests
John Brawn via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 8 04:49:18 PST 2017
Author: john.brawn
Date: Wed Mar 8 06:49:18 2017
New Revision: 297273
URL: http://llvm.org/viewvc/llvm-project?rev=297273&view=rev
Log:
[ARM] Split up lsl-zero test into two tests
On Windows stderr and stdout happen to get interleaved in a way that causes the
test to fail, so split it up into a test that checks for errors and a test that
doesn't.
Added:
llvm/trunk/test/MC/ARM/lsl-zero-errors.s
Modified:
llvm/trunk/test/MC/ARM/lsl-zero.s
Added: llvm/trunk/test/MC/ARM/lsl-zero-errors.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/lsl-zero-errors.s?rev=297273&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM/lsl-zero-errors.s (added)
+++ llvm/trunk/test/MC/ARM/lsl-zero-errors.s Wed Mar 8 06:49:18 2017
@@ -0,0 +1,103 @@
+// RUN: not llvm-mc -triple=thumbv7 -show-encoding < %s 2>&1 | FileCheck --check-prefix=CHECK --check-prefix=CHECK-NONARM --check-prefix=CHECK-THUMBV7 %s
+// RUN: not llvm-mc -triple=thumbv8 -show-encoding < %s 2>&1 | FileCheck --check-prefix=CHECK --check-prefix=CHECK-NONARM --check-prefix=CHECK-THUMBV8 %s
+// RUN: llvm-mc -triple=armv7 -show-encoding < %s 2>&1 | FileCheck --check-prefix=CHECK --check-prefix=CHECK-ARM %s
+
+ // lsl #0 is actually mov, so here we check that it behaves the same as
+ // mov with regards to the permitted registers
+
+ // Using PC is invalid in thumb
+ lsl pc, r0, #0
+ lsl r0, pc, #0
+ lsl pc, pc, #0
+ lsls pc, r0, #0
+ lsls r0, pc, #0
+ lsls pc, pc, #0
+
+// CHECK-NONARM: error: instruction requires: arm-mode
+// CHECK-NONARM-NEXT: lsl pc, r0, #0
+// CHECK-NONARM: error: instruction requires: arm-mode
+// CHECK-NONARM-NEXT: lsl r0, pc, #0
+// CHECK-NONARM: error: instruction requires: arm-mode
+// CHECK-NONARM-NEXT: lsl pc, pc, #0
+// CHECK-NONARM: error: instruction requires: arm-mode
+// CHECK-NONARM-NEXT: lsls pc, r0, #0
+// CHECK-NONARM: error: instruction requires: arm-mode
+// CHECK-NONARM-NEXT: lsls r0, pc, #0
+// CHECK-NONARM: error: instruction requires: arm-mode
+// CHECK-NONARM-NEXT: lsls pc, pc, #0
+
+// CHECK-ARM: mov pc, r0 @ encoding: [0x00,0xf0,0xa0,0xe1]
+// CHECK-ARM: mov r0, pc @ encoding: [0x0f,0x00,0xa0,0xe1]
+// CHECK-ARM: mov pc, pc @ encoding: [0x0f,0xf0,0xa0,0xe1]
+// CHECK-ARM: movs pc, r0 @ encoding: [0x00,0xf0,0xb0,0xe1]
+// CHECK-ARM: movs r0, pc @ encoding: [0x0f,0x00,0xb0,0xe1]
+// CHECK-ARM: movs pc, pc @ encoding: [0x0f,0xf0,0xb0,0xe1]
+
+ mov pc, r0, lsl #0
+ mov r0, pc, lsl #0
+ mov pc, pc, lsl #0
+ movs pc, r0, lsl #0
+ movs r0, pc, lsl #0
+ movs pc, pc, lsl #0
+
+// FIXME: Really the error we should be giving is "requires: arm-mode"
+// CHECK-NONARM: error: invalid operand for instruction
+// CHECK-NONARM-NEXT: mov pc, r0, lsl #0
+// CHECK-NONARM: error: invalid operand for instruction
+// CHECK-NONARM-NEXT: mov r0, pc, lsl #0
+// CHECK-NONARM: error: invalid operand for instruction
+// CHECK-NONARM-NEXT: mov pc, pc, lsl #0
+// CHECK-NONARM: error: invalid operand for instruction
+// CHECK-NONARM-NEXT: movs pc, r0, lsl #0
+// CHECK-NONARM: error: invalid operand for instruction
+// CHECK-NONARM-NEXT: movs r0, pc, lsl #0
+// CHECK-NONARM: error: invalid operand for instruction
+// CHECK-NONARM-NEXT: movs pc, pc, lsl #0
+
+// CHECK-ARM: mov pc, r0 @ encoding: [0x00,0xf0,0xa0,0xe1]
+// CHECK-ARM: mov r0, pc @ encoding: [0x0f,0x00,0xa0,0xe1]
+// CHECK-ARM: mov pc, pc @ encoding: [0x0f,0xf0,0xa0,0xe1]
+// CHECK-ARM: movs pc, r0 @ encoding: [0x00,0xf0,0xb0,0xe1]
+// CHECK-ARM: movs r0, pc @ encoding: [0x0f,0x00,0xb0,0xe1]
+// CHECK-ARM: movs pc, pc @ encoding: [0x0f,0xf0,0xb0,0xe1]
+
+ // Using SP is invalid before ARMv8 in thumb unless non-flags-setting
+ // and one of the source and destination is not SP
+ lsl sp, sp, #0
+ lsls sp, sp, #0
+ lsls r0, sp, #0
+ lsls sp, r0, #0
+
+// CHECK-THUMBV7: error: instruction variant requires ARMv8 or later
+// CHECK-THUMBV7-NEXT: lsl sp, sp, #0
+// CHECK-THUMBV7: error: instruction variant requires ARMv8 or later
+// CHECK-THUMBV7-NEXT: lsls sp, sp, #0
+// CHECK-THUMBV7: error: instruction variant requires ARMv8 or later
+// CHECK-THUMBV7-NEXT: lsls r0, sp, #0
+// CHECK-THUMBV7: error: instruction variant requires ARMv8 or later
+// CHECK-THUMBV7-NEXT: lsls sp, r0, #0
+
+// CHECK-ARM: mov sp, sp @ encoding: [0x0d,0xd0,0xa0,0xe1]
+// CHECK-ARM: movs sp, sp @ encoding: [0x0d,0xd0,0xb0,0xe1]
+// CHECK-ARM: movs r0, sp @ encoding: [0x0d,0x00,0xb0,0xe1]
+// CHECK-ARM: movs sp, r0 @ encoding: [0x00,0xd0,0xb0,0xe1]
+
+ mov sp, sp, lsl #0
+ movs sp, sp, lsl #0
+ movs r0, sp, lsl #0
+ movs sp, r0, lsl #0
+
+// FIXME: We should consistently have the "requires ARMv8" error here
+// CHECK-THUMBV7: error: invalid operand for instruction
+// CHECK-THUMBV7-NEXT: mov sp, sp, lsl #0
+// CHECK-THUMBV7: error: invalid operand for instruction
+// CHECK-THUMBV7-NEXT: movs sp, sp, lsl #0
+// CHECK-THUMBV7: error: instruction variant requires ARMv8 or later
+// CHECK-THUMBV7-NEXT: movs r0, sp, lsl #0
+// CHECK-THUMBV7: error: invalid operand for instruction
+// CHECK-THUMBV7-NEXT: movs sp, r0, lsl #0
+
+// CHECK-ARM: mov sp, sp @ encoding: [0x0d,0xd0,0xa0,0xe1]
+// CHECK-ARM: movs sp, sp @ encoding: [0x0d,0xd0,0xb0,0xe1]
+// CHECK-ARM: movs r0, sp @ encoding: [0x0d,0x00,0xb0,0xe1]
+// CHECK-ARM: movs sp, r0 @ encoding: [0x00,0xd0,0xb0,0xe1]
Modified: llvm/trunk/test/MC/ARM/lsl-zero.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/lsl-zero.s?rev=297273&r1=297272&r2=297273&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/lsl-zero.s (original)
+++ llvm/trunk/test/MC/ARM/lsl-zero.s Wed Mar 8 06:49:18 2017
@@ -1,108 +1,11 @@
-// RUN: not llvm-mc -triple=thumbv7 -show-encoding < %s 2>&1 | FileCheck --check-prefix=CHECK --check-prefix=CHECK-NONARM --check-prefix=CHECK-THUMBV7 %s
-// RUN: not llvm-mc -triple=thumbv8 -show-encoding < %s 2>&1 | FileCheck --check-prefix=CHECK --check-prefix=CHECK-NONARM --check-prefix=CHECK-THUMBV8 %s
+// RUN: llvm-mc -triple=thumbv7 -show-encoding < %s 2>&1 | FileCheck --check-prefix=CHECK --check-prefix=CHECK-NONARM --check-prefix=CHECK-THUMBV7 %s
+// RUN: llvm-mc -triple=thumbv8 -show-encoding < %s 2>&1 | FileCheck --check-prefix=CHECK --check-prefix=CHECK-NONARM --check-prefix=CHECK-THUMBV8 %s
// RUN: llvm-mc -triple=armv7 -show-encoding < %s 2>&1 | FileCheck --check-prefix=CHECK --check-prefix=CHECK-ARM %s
// lsl #0 is actually mov, so here we check that it behaves the same as
// mov with regards to the permitted registers and how it behaves in an
// IT block.
- // Using PC is invalid in thumb
- lsl pc, r0, #0
- lsl r0, pc, #0
- lsl pc, pc, #0
- lsls pc, r0, #0
- lsls r0, pc, #0
- lsls pc, pc, #0
-
-// CHECK-NONARM: error: instruction requires: arm-mode
-// CHECK-NONARM-NEXT: lsl pc, r0, #0
-// CHECK-NONARM: error: instruction requires: arm-mode
-// CHECK-NONARM-NEXT: lsl r0, pc, #0
-// CHECK-NONARM: error: instruction requires: arm-mode
-// CHECK-NONARM-NEXT: lsl pc, pc, #0
-// CHECK-NONARM: error: instruction requires: arm-mode
-// CHECK-NONARM-NEXT: lsls pc, r0, #0
-// CHECK-NONARM: error: instruction requires: arm-mode
-// CHECK-NONARM-NEXT: lsls r0, pc, #0
-// CHECK-NONARM: error: instruction requires: arm-mode
-// CHECK-NONARM-NEXT: lsls pc, pc, #0
-
-// CHECK-ARM: mov pc, r0 @ encoding: [0x00,0xf0,0xa0,0xe1]
-// CHECK-ARM: mov r0, pc @ encoding: [0x0f,0x00,0xa0,0xe1]
-// CHECK-ARM: mov pc, pc @ encoding: [0x0f,0xf0,0xa0,0xe1]
-// CHECK-ARM: movs pc, r0 @ encoding: [0x00,0xf0,0xb0,0xe1]
-// CHECK-ARM: movs r0, pc @ encoding: [0x0f,0x00,0xb0,0xe1]
-// CHECK-ARM: movs pc, pc @ encoding: [0x0f,0xf0,0xb0,0xe1]
-
- mov pc, r0, lsl #0
- mov r0, pc, lsl #0
- mov pc, pc, lsl #0
- movs pc, r0, lsl #0
- movs r0, pc, lsl #0
- movs pc, pc, lsl #0
-
-// FIXME: Really the error we should be giving is "requires: arm-mode"
-// CHECK-NONARM: error: invalid operand for instruction
-// CHECK-NONARM-NEXT: mov pc, r0, lsl #0
-// CHECK-NONARM: error: invalid operand for instruction
-// CHECK-NONARM-NEXT: mov r0, pc, lsl #0
-// CHECK-NONARM: error: invalid operand for instruction
-// CHECK-NONARM-NEXT: mov pc, pc, lsl #0
-// CHECK-NONARM: error: invalid operand for instruction
-// CHECK-NONARM-NEXT: movs pc, r0, lsl #0
-// CHECK-NONARM: error: invalid operand for instruction
-// CHECK-NONARM-NEXT: movs r0, pc, lsl #0
-// CHECK-NONARM: error: invalid operand for instruction
-// CHECK-NONARM-NEXT: movs pc, pc, lsl #0
-
-// CHECK-ARM: mov pc, r0 @ encoding: [0x00,0xf0,0xa0,0xe1]
-// CHECK-ARM: mov r0, pc @ encoding: [0x0f,0x00,0xa0,0xe1]
-// CHECK-ARM: mov pc, pc @ encoding: [0x0f,0xf0,0xa0,0xe1]
-// CHECK-ARM: movs pc, r0 @ encoding: [0x00,0xf0,0xb0,0xe1]
-// CHECK-ARM: movs r0, pc @ encoding: [0x0f,0x00,0xb0,0xe1]
-// CHECK-ARM: movs pc, pc @ encoding: [0x0f,0xf0,0xb0,0xe1]
-
- // Using SP is invalid before ARMv8 in thumb unless non-flags-setting
- // and one of the source and destination is not SP
- lsl sp, sp, #0
- lsls sp, sp, #0
- lsls r0, sp, #0
- lsls sp, r0, #0
-
-// CHECK-THUMBV7: error: instruction variant requires ARMv8 or later
-// CHECK-THUMBV7-NEXT: lsl sp, sp, #0
-// CHECK-THUMBV7: error: instruction variant requires ARMv8 or later
-// CHECK-THUMBV7-NEXT: lsls sp, sp, #0
-// CHECK-THUMBV7: error: instruction variant requires ARMv8 or later
-// CHECK-THUMBV7-NEXT: lsls r0, sp, #0
-// CHECK-THUMBV7: error: instruction variant requires ARMv8 or later
-// CHECK-THUMBV7-NEXT: lsls sp, r0, #0
-
-// CHECK-ARM: mov sp, sp @ encoding: [0x0d,0xd0,0xa0,0xe1]
-// CHECK-ARM: movs sp, sp @ encoding: [0x0d,0xd0,0xb0,0xe1]
-// CHECK-ARM: movs r0, sp @ encoding: [0x0d,0x00,0xb0,0xe1]
-// CHECK-ARM: movs sp, r0 @ encoding: [0x00,0xd0,0xb0,0xe1]
-
- mov sp, sp, lsl #0
- movs sp, sp, lsl #0
- movs r0, sp, lsl #0
- movs sp, r0, lsl #0
-
-// FIXME: We should consistently have the "requires ARMv8" error here
-// CHECK-THUMBV7: error: invalid operand for instruction
-// CHECK-THUMBV7-NEXT: mov sp, sp, lsl #0
-// CHECK-THUMBV7: error: invalid operand for instruction
-// CHECK-THUMBV7-NEXT: movs sp, sp, lsl #0
-// CHECK-THUMBV7: error: instruction variant requires ARMv8 or later
-// CHECK-THUMBV7-NEXT: movs r0, sp, lsl #0
-// CHECK-THUMBV7: error: invalid operand for instruction
-// CHECK-THUMBV7-NEXT: movs sp, r0, lsl #0
-
-// CHECK-ARM: mov sp, sp @ encoding: [0x0d,0xd0,0xa0,0xe1]
-// CHECK-ARM: movs sp, sp @ encoding: [0x0d,0xd0,0xb0,0xe1]
-// CHECK-ARM: movs r0, sp @ encoding: [0x0d,0x00,0xb0,0xe1]
-// CHECK-ARM: movs sp, r0 @ encoding: [0x00,0xd0,0xb0,0xe1]
-
// Non-flags-setting with only one of source and destination SP should
// be OK
lsl sp, r0, #0
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