[PATCH] D30400: For Thumb1, lower ADDC/ADDE/SUBC/SUBE via the glueless ARMISD nodes, same as already done for ARM and Thumb2.

[A. Skrobov via Phabricator via llvm-commits]

tyomitch added inline comments.


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Comment at: test/CodeGen/Thumb/long.ll:56
+; CHECK: movs r1, #0
+; CHECK: adcs r1, r3
+}
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Now I see that lowering an `(ADDE x, y, (ADDC z, t))` into a chain of `(CopyFromReg CPSR, (tADD z, t)), (CopyFromReg CPSR, (tADC x, y, (CopyToReg CPSR)))`, with the CPSR-copying nodes glued to the arithmetic nodes, -- doesn't prevent LLVM from scheduling CPSR-clobbering operations in between the converted ADDC and the converted ADDE, -- such as in this test case, where a flag-setting tMOVi8 is inserted in the middle.

An ugly patch is certainly better than an incorrect one, so I decided to go back and finish the "hybrid implementation" using tPseudoInsts with two integer outputs each for tADDS / tSUBS, and custom C++ lowering for tADC / tSBC.


https://reviews.llvm.org/D30400