[llvm] r297134 - In Thumb1, materialize a move between low registers as a `movs`, if CPSR isn't live.
Artyom Skrobov via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 7 01:38:16 PST 2017
Author: askrobov
Date: Tue Mar 7 03:38:16 2017
New Revision: 297134
URL: http://llvm.org/viewvc/llvm-project?rev=297134&view=rev
Log:
In Thumb1, materialize a move between low registers as a `movs`, if CPSR isn't live.
Summary: Previously, it had always been materialized as a push/pop sequence.
Reviewers: labrinea, jroelofs
Reviewed By: jroelofs
Subscribers: llvm-commits, rengolin
Differential Revision: https://reviews.llvm.org/D30648
Modified:
llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp
llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll
llvm/trunk/test/CodeGen/ARM/atomic-cmpxchg.ll
llvm/trunk/test/CodeGen/ARM/smml.ll
llvm/trunk/test/CodeGen/Thumb/copy_thumb.ll
llvm/trunk/test/CodeGen/Thumb/thumb-shrink-wrapping.ll
Modified: llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp?rev=297134&r1=297133&r2=297134&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp Tue Mar 7 03:38:16 2017
@@ -54,11 +54,17 @@ void Thumb1InstrInfo::copyPhysReg(Machin
.addReg(SrcReg, getKillRegState(KillSrc))
.add(predOps(ARMCC::AL));
else {
- // FIXME: The performance consequences of this are going to be atrocious.
- // Some things to try that should be better:
- // * 'mov hi, $src; mov $dst, hi', with hi as either r10 or r11
- // * 'movs $dst, $src' if cpsr isn't live
- // See: http://lists.llvm.org/pipermail/llvm-dev/2014-August/075998.html
+ // FIXME: Can also use 'mov hi, $src; mov $dst, hi',
+ // with hi as either r10 or r11.
+
+ const TargetRegisterInfo *RegInfo = st.getRegisterInfo();
+ if (MBB.computeRegisterLiveness(RegInfo, ARM::CPSR, I)
+ == MachineBasicBlock::LQR_Dead) {
+ BuildMI(MBB, I, DL, get(ARM::tMOVSr), DestReg)
+ .addReg(SrcReg, getKillRegState(KillSrc))
+ ->addRegisterDead(ARM::CPSR, RegInfo);
+ return;
+ }
// 'MOV lo, lo' is unpredictable on < v6, so use the stack to do it
BuildMI(MBB, I, DL, get(ARM::tPUSH))
Modified: llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll?rev=297134&r1=297133&r2=297134&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll Tue Mar 7 03:38:16 2017
@@ -150,16 +150,14 @@ define i32 @test_tst_assessment(i32 %a,
;
; THUMB-LABEL: test_tst_assessment:
; THUMB: @ BB#0:
-; THUMB-NEXT: push {r0}
-; THUMB-NEXT: pop {r2}
+; THUMB-NEXT: movs r2, r0
; THUMB-NEXT: movs r0, #1
; THUMB-NEXT: ands r0, r2
; THUMB-NEXT: subs r2, r0, #1
; THUMB-NEXT: lsls r1, r1, #31
; THUMB-NEXT: beq .LBB2_2
; THUMB-NEXT: @ BB#1:
-; THUMB-NEXT: push {r2}
-; THUMB-NEXT: pop {r0}
+; THUMB-NEXT: movs r0, r2
; THUMB-NEXT: .LBB2_2:
; THUMB-NEXT: bx lr
;
Modified: llvm/trunk/test/CodeGen/ARM/atomic-cmpxchg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/atomic-cmpxchg.ll?rev=297134&r1=297133&r2=297134&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/atomic-cmpxchg.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/atomic-cmpxchg.ll Tue Mar 7 03:38:16 2017
@@ -24,14 +24,12 @@ entry:
; CHECK-THUMB-LABEL: test_cmpxchg_res_i8
; CHECK-THUMB: bl __sync_val_compare_and_swap_1
; CHECK-THUMB-NOT: mov [[R1:r[0-7]]], r0
-; CHECK-THUMB: push {r0}
-; CHECK-THUMB: pop {[[R1:r[0-7]]]}
+; CHECK-THUMB: movs [[R1:r[0-7]]], r0
; CHECK-THUMB: movs r0, #1
; CHECK-THUMB: movs [[R2:r[0-9]+]], #0
; CHECK-THUMB: cmp [[R1]], {{r[0-9]+}}
; CHECK-THUMB: beq
-; CHECK-THUMB: push {[[R2]]}
-; CHECK-THUMB: pop {r0}
+; CHECK-THUMB: movs r0, [[R2]]
; CHECK-ARMV6-LABEL: test_cmpxchg_res_i8:
; CHECK-ARMV6-NEXT: .fnstart
Modified: llvm/trunk/test/CodeGen/ARM/smml.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/smml.ll?rev=297134&r1=297133&r2=297134&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/smml.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/smml.ll Tue Mar 7 03:38:16 2017
@@ -1,20 +1,15 @@
-; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
-; RUN: llc -mtriple=armv6-eabi %s -o - | FileCheck %s -check-prefix=CHECK-V6
-; RUN: llc -mtriple=armv7-eabi %s -o - | FileCheck %s -check-prefix=CHECK-V7
-; RUN: llc -mtriple=thumb-eabi %s -o - | FileCheck %s -check-prefix=CHECK-THUMB
-; RUN: llc -mtriple=thumbv6-eabi %s -o - | FileCheck %s -check-prefix=CHECK-THUMB
-; RUN: llc -mtriple=thumbv6t2-eabi %s -o - | FileCheck %s -check-prefix=CHECK-THUMBV6T2
-; RUN: llc -mtriple=thumbv7-eabi %s -o - | FileCheck %s -check-prefix=CHECK-THUMBV7
+; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-V4
+; RUN: llc -mtriple=armv6-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-V6
+; RUN: llc -mtriple=armv7-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-V6
+; RUN: llc -mtriple=thumb-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-THUMB
+; RUN: llc -mtriple=thumbv6-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-THUMBV6
+; RUN: llc -mtriple=thumbv6t2-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-THUMBV6T2
+; RUN: llc -mtriple=thumbv7-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-THUMBV6T2
define i32 @Test0(i32 %a, i32 %b, i32 %c) nounwind readnone ssp {
entry:
; CHECK-LABEL: Test0
; CHECK-NOT: smmls
-; CHECK-V6-NOT: smmls
-; CHECK-V7-NOT: smmls
-; CHECK_THUMB-NOT: smmls
-; CHECK-THUMBV6T2-NOT: smmls
-; CHECK-THUMBV7-NOT: smmls
%conv4 = zext i32 %a to i64
%conv1 = sext i32 %b to i64
%conv2 = sext i32 %c to i64
@@ -27,12 +22,11 @@ entry:
define i32 @Test1(i32 %a, i32 %b, i32 %c) {
;CHECK-LABEL: Test1
-;CHECK-NOT: smmls
+;CHECK-V4-NOT: smmls
;CHECK-THUMB-NOT: smmls
+;CHECK-THUMBV6-NOT: smmls
;CHECK-V6: smmls r0, [[Rn:r[1-2]]], [[Rm:r[1-2]]], r0
-;CHECK-V7: smmls r0, [[Rn:r[1-2]]], [[Rm:r[1-2]]], r0
;CHECK-THUMBV6T2: smmls r0, [[Rn:r[1-2]]], [[Rm:r[1-2]]], r0
-;CHECK-THUMBV7: smmls r0, [[Rn:r[1-2]]], [[Rm:r[1-2]]], r0
entry:
%conv = sext i32 %b to i64
%conv1 = sext i32 %c to i64
@@ -47,10 +41,21 @@ entry:
declare void @opaque(i32)
define void @test_used_flags(i32 %in1, i32 %in2) {
-; CHECK-V7-LABEL: test_used_flags:
-; CHECK-V7: smull [[PROD_LO:r[0-9]+]], [[PROD_HI:r[0-9]+]], r0, r1
-; CHECK-V7: rsbs {{.*}}, [[PROD_LO]], #0
-; CHECK-V7: rscs {{.*}}, [[PROD_HI]], #0
+; CHECK-LABEL: test_used_flags:
+; CHECK-THUMB: cmp r1, #0
+; CHECK-THUMB: push {r2}
+; CHECK-THUMB: pop {r3}
+; CHECK-THUMB: ble
+; CHECK-THUMBV6: cmp r1, #0
+; CHECK-THUMBV6: mov r3, r2
+; CHECK-THUMBV6: ble
+; CHECK-V6: smull [[PROD_LO:r[0-9]+]], [[PROD_HI:r[0-9]+]], r0, r1
+; CHECK-V6: rsbs {{.*}}, [[PROD_LO]], #0
+; CHECK-V6: rscs {{.*}}, [[PROD_HI]], #0
+; CHECK-THUMBV6T2: smull [[PROD_LO:r[0-9]+]], [[PROD_HI:r[0-9]+]], r0, r1
+; CHECK-THUMBV6T2: movs [[ZERO:r[0-9]+]], #0
+; CHECK-THUMBV6T2: rsbs {{.*}}, [[PROD_LO]], #0
+; CHECK-THUMBV6T2: sbcs.w {{.*}}, [[ZERO]], [[PROD_HI]]
%in1.64 = sext i32 %in1 to i64
%in2.64 = sext i32 %in2 to i64
%mul = mul nsw i64 %in1.64, %in2.64
Modified: llvm/trunk/test/CodeGen/Thumb/copy_thumb.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/copy_thumb.ll?rev=297134&r1=297133&r2=297134&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb/copy_thumb.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb/copy_thumb.ll Tue Mar 7 03:38:16 2017
@@ -16,15 +16,9 @@
; RUN: llc -mtriple=thumbv4t-none--eabi < %s | FileCheck %s --check-prefix=CHECK-NOLOLOMOV
; RUN: llc -mtriple=thumbv5-none--eabi < %s | FileCheck %s --check-prefix=CHECK-NOLOLOMOV
; CHECK-NOLOLOMOV-LABEL: foo
-; CHECK-NOLOLOMOV-NOT: mov [[TMP:r[0-7]]], [[SRC1:r[01]]]
-; CHECK-NOLOLOMOV: push {[[SRC1:r[01]]]}
-; CHECK-NOLOLOMOV-NEXT: pop {[[TMP:r[0-7]]]}
-; CHECK-NOLOLOMOV-NOT: mov [[TMP:r[0-7]]], [[SRC1:r[01]]]
-; CHECK-NOLOLOMOV: push {[[SRC2:r[01]]]}
-; CHECK-NOLOLOMOV-NEXT: pop {[[SRC1]]}
-; CHECK-NOLOLOMOV-NOT: mov [[TMP:r[0-7]]], [[SRC1:r[01]]]
-; CHECK-NOLOLOMOV: push {[[TMP]]}
-; CHECK-NOLOLOMOV-NEXT: pop {[[SRC2]]}
+; CHECK-NOLOLOMOV: movs [[TMP:r[0-7]]], [[SRC1:r[01]]]
+; CHECK-NOLOLOMOV-NEXT: movs [[SRC1]], [[SRC2:r[01]]]
+; CHECK-NOLOLOMOV-NEXT: movs [[SRC2]], [[TMP]]
; CHECK-NOLOLOMOV-LABEL: bar
; CHECK-NOLOLOMOV-LABEL: fnend
Modified: llvm/trunk/test/CodeGen/Thumb/thumb-shrink-wrapping.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/thumb-shrink-wrapping.ll?rev=297134&r1=297133&r2=297134&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb/thumb-shrink-wrapping.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb/thumb-shrink-wrapping.ll Tue Mar 7 03:38:16 2017
@@ -505,14 +505,9 @@ if.end:
; CHECK-NEXT: str r1, {{\[}}[[TMP_SP]]]
; CHECK-NEXT: str r1, {{\[}}[[TMP_SP]], #4]
; CHECK-NEXT: str r1, {{\[}}[[TMP_SP]], #8]
-; Thumb has quite a strange way for moving stuff
-; in around. Oh well, match the current sequence.
-; CHECK: push {r1}
-; CHECK-NEXT: pop {r0}
-; CHECK: push {r1}
-; CHECK-NEXT: pop {r2}
-; CHECK: push {r1}
-; CHECK-NEXT: pop {r3}
+; CHECK: movs r0, r1
+; CHECK-NEXT: movs r2, r1
+; CHECK-NEXT: movs r3, r1
; CHECK-NEXT: bl
; CHECK-NEXT: lsls r0, r0, #3
;
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