[PATCH] D30665: [InstSimplify] vector div/rem with any zero element in divisor is undef

[Michael Kuperstein via Phabricator via llvm-commits]

mkuper added a comment.

Would that mean that this transformation (very naive SLP vectorization) would become illegal:

  %z1 = urem i8 %x1, %y1
  %z2 = urem i8 %x2, %y2
  ret i8 %z1

Into:

  %vx1 = insertelement <2 x i8> undef, i8 %x1, i32 0
  %vx2 = insertelement <2 x i8> %vx1, i8 %x2, i32 1
  %vy1 = insertelement <2 x i8> undef, i8 %y1, i32 0
  %vy2 = insertelement <2 x i8> %vy1, i8 %y2, i32 1
  %vz = urem <2 x i8> %vx2, %vy2
  %z = extractelement <2 x i8>%vz, i32 0
  ret i8 %z

?

I'm not sure this is something we want.


https://reviews.llvm.org/D30665