[llvm] r296881 - [x86] regenerate checks; NFC
Sanjay Patel via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 3 08:45:58 PST 2017
Author: spatel
Date: Fri Mar 3 10:45:57 2017
New Revision: 296881
URL: http://llvm.org/viewvc/llvm-project?rev=296881&view=rev
Log:
[x86] regenerate checks; NFC
Modified:
llvm/trunk/test/CodeGen/X86/peep-setb.ll
Modified: llvm/trunk/test/CodeGen/X86/peep-setb.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/peep-setb.ll?rev=296881&r1=296880&r2=296881&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/peep-setb.ll (original)
+++ llvm/trunk/test/CodeGen/X86/peep-setb.ll Fri Mar 3 10:45:57 2017
@@ -1,82 +1,120 @@
-; RUN: llc -march=x86-64 < %s | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=x86_64-unknown-unknown < %s | FileCheck %s
define i8 @test1(i8 %a, i8 %b) nounwind {
+; CHECK-LABEL: test1:
+; CHECK: # BB#0:
+; CHECK-NEXT: cmpb %sil, %dil
+; CHECK-NEXT: adcb $0, %sil
+; CHECK-NEXT: movl %esi, %eax
+; CHECK-NEXT: retq
%cmp = icmp ult i8 %a, %b
%cond = zext i1 %cmp to i8
%add = add i8 %cond, %b
ret i8 %add
-; CHECK-LABEL: test1:
-; CHECK: adcb $0
}
define i32 @test2(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: test2:
+; CHECK: # BB#0:
+; CHECK-NEXT: cmpl %esi, %edi
+; CHECK-NEXT: adcl $0, %esi
+; CHECK-NEXT: movl %esi, %eax
+; CHECK-NEXT: retq
%cmp = icmp ult i32 %a, %b
%cond = zext i1 %cmp to i32
%add = add i32 %cond, %b
ret i32 %add
-; CHECK-LABEL: test2:
-; CHECK: adcl $0
}
define i64 @test3(i64 %a, i64 %b) nounwind {
+; CHECK-LABEL: test3:
+; CHECK: # BB#0:
+; CHECK-NEXT: cmpq %rsi, %rdi
+; CHECK-NEXT: adcq $0, %rsi
+; CHECK-NEXT: movq %rsi, %rax
+; CHECK-NEXT: retq
%cmp = icmp ult i64 %a, %b
%conv = zext i1 %cmp to i64
%add = add i64 %conv, %b
ret i64 %add
-; CHECK-LABEL: test3:
-; CHECK: adcq $0
}
define i8 @test4(i8 %a, i8 %b) nounwind {
+; CHECK-LABEL: test4:
+; CHECK: # BB#0:
+; CHECK-NEXT: cmpb %sil, %dil
+; CHECK-NEXT: sbbb $0, %sil
+; CHECK-NEXT: movl %esi, %eax
+; CHECK-NEXT: retq
%cmp = icmp ult i8 %a, %b
%cond = zext i1 %cmp to i8
%sub = sub i8 %b, %cond
ret i8 %sub
-; CHECK-LABEL: test4:
-; CHECK: sbbb $0
}
define i32 @test5(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: test5:
+; CHECK: # BB#0:
+; CHECK-NEXT: cmpl %esi, %edi
+; CHECK-NEXT: sbbl $0, %esi
+; CHECK-NEXT: movl %esi, %eax
+; CHECK-NEXT: retq
%cmp = icmp ult i32 %a, %b
%cond = zext i1 %cmp to i32
%sub = sub i32 %b, %cond
ret i32 %sub
-; CHECK-LABEL: test5:
-; CHECK: sbbl $0
}
define i64 @test6(i64 %a, i64 %b) nounwind {
+; CHECK-LABEL: test6:
+; CHECK: # BB#0:
+; CHECK-NEXT: cmpq %rsi, %rdi
+; CHECK-NEXT: sbbq $0, %rsi
+; CHECK-NEXT: movq %rsi, %rax
+; CHECK-NEXT: retq
%cmp = icmp ult i64 %a, %b
%conv = zext i1 %cmp to i64
%sub = sub i64 %b, %conv
ret i64 %sub
-; CHECK-LABEL: test6:
-; CHECK: sbbq $0
}
define i8 @test7(i8 %a, i8 %b) nounwind {
+; CHECK-LABEL: test7:
+; CHECK: # BB#0:
+; CHECK-NEXT: cmpb %sil, %dil
+; CHECK-NEXT: adcb $0, %sil
+; CHECK-NEXT: movl %esi, %eax
+; CHECK-NEXT: retq
%cmp = icmp ult i8 %a, %b
%cond = sext i1 %cmp to i8
%sub = sub i8 %b, %cond
ret i8 %sub
-; CHECK-LABEL: test7:
-; CHECK: adcb $0
}
define i32 @test8(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: test8:
+; CHECK: # BB#0:
+; CHECK-NEXT: cmpl %esi, %edi
+; CHECK-NEXT: adcl $0, %esi
+; CHECK-NEXT: movl %esi, %eax
+; CHECK-NEXT: retq
%cmp = icmp ult i32 %a, %b
%cond = sext i1 %cmp to i32
%sub = sub i32 %b, %cond
ret i32 %sub
-; CHECK-LABEL: test8:
-; CHECK: adcl $0
}
define i64 @test9(i64 %a, i64 %b) nounwind {
+; CHECK-LABEL: test9:
+; CHECK: # BB#0:
+; CHECK-NEXT: cmpq %rsi, %rdi
+; CHECK-NEXT: adcq $0, %rsi
+; CHECK-NEXT: movq %rsi, %rax
+; CHECK-NEXT: retq
%cmp = icmp ult i64 %a, %b
%conv = sext i1 %cmp to i64
%sub = sub i64 %b, %conv
ret i64 %sub
-; CHECK-LABEL: test9:
-; CHECK: adcq $0
}
+
More information about the llvm-commits
mailing list