[PATCH] D30571: [ARM] [Assembler] Extend implicit substitutions

[Sanne Wouda via Phabricator via llvm-commits]

sanwou01 created this revision.
Herald added a subscriber: aemerson.

Implicit substitutions change an instruction that cannot be encoded to
an equivalent but different instruction.  For example,
"ADD r0, r1, #FFFFFFFF" cannot be encoded as an ADD instruction.  However,
"SUB r0, r1, #1" is equivalent.

These substitutions are different from instruction aliases.  An alias
maps several assembler instructions onto one encoding.  An implicit
substitution, however, maps an *invalid* instruction--e.g. with an
immediate that cannot be represented in the encoding--to a different
(but equivalent) instruction.

Several instructions were substituted already, but this was not
systematically tested, nor did it cover the full set of possible
substitutions.

This patch implements all possible substitutions for ARM, Thumb and
Thumb1 assembler and adds tests.  It also adds a feature flag
(-mattr=+no-implicit-subs) to turn these substitutions off.


https://reviews.llvm.org/D30571

Files:
  lib/Target/ARM/ARM.td
  lib/Target/ARM/ARMInstrFormats.td
  lib/Target/ARM/ARMInstrInfo.td
  lib/Target/ARM/ARMInstrThumb.td
  lib/Target/ARM/ARMInstrThumb2.td
  lib/Target/ARM/ARMSubtarget.h
  lib/Target/ARM/AsmParser/ARMAsmParser.cpp
  test/MC/ARM/implicit-substitutions-fail.s
  test/MC/ARM/implicit-substitutions-thumb1-fail.s
  test/MC/ARM/implicit-substitutions-thumb1.s
  test/MC/ARM/implicit-substitutions.s

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