[PATCH] D30400: For Thumb1, lower ADDC/ADDE/SUBC/SUBE via the glueless ARMISD nodes, same as already done for ARM and Thumb2.

[A. Skrobov via Phabricator via llvm-commits]

tyomitch added a comment.

//clobbering CPSR when we don't need to// is the least of the problems; what we have in ARM and Thumb2 is that ADD and ADDS are defined separately, the former producing one result (to match an ADD node), and the latter producing two (to match an ADDC node). In Thumb1, we cannot define them separately, so tADD MIs are defined with an OptionalDef for CPSR. The ISel patterns won't let me match an MI with one result value (and an OptionalDef) to an ISD node producing two results. Redefining tADD to always produce two results doesn't work either, because it's assumed, by many layers including AsmParser / AsmPrinter, to still have the OptionalDef for CPSR; and the InstrEmitter won't let me have CPSR as both an OptionalDef and an actual result in the same MI.
Handwave handwave, I cannot really prove that it cannot be done, but I mean I had tried, and I couldn't.



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Comment at: test/CodeGen/Thumb/long.ll:80
+; CHECK: adcs r1, r3
 }
 
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efriedma wrote:
> I'd also like to see some tests here for subtraction with an immediate amount. ("add i64 %y, -10" etc.)
Indeed, subtracting immediates wasn't handled well; I'll upload the updated patch.


https://reviews.llvm.org/D30400