[PATCH] D30416: [InstCombine] Redo reduceLoadOpStoreWidth in instcombine for bitfield store optimization.

[Wei Mi via Phabricator via llvm-commits]

wmi created this revision.

reduceLoadOpStoreWidth is a useful optimization already existing in DAGCombiner. It can shrink the bitfield store in the following testcase:

class A {
public:
  unsigned long f1:16;
  unsigned long f2:3;
};
A a;

void foo() {
  // if (a.f1 == 2) return;
  a.f1 = a.f1 + 3;
}

For a.f2 = a.f2 + 3, without reduceLoadOpStoreWidth in DAGCombiner, the code will be:
        movl    a(%rip), %eax
        leal    3(%rax), %ecx
        movzwl  %cx, %ecx
        andl    $-65536, %eax           # imm = 0xFFFF0000
        orl     %ecx, %eax
        movl    %eax, a(%rip)

with reduceLoadOpStoreWidth, the code will be:
        movl    a(%rip), %eax
        addl    $3, %eax
        movw    %ax, a(%rip)

However, if we remove the comment above, the load of a.f2 and the store of a.f2 will stay in two different BasicBlocks and reduceLoadOpStoreWidth in DAGCombiner cannot work.

The patch is redoing the same optimization in InstCombine, so the optimization will not be limited by the BasicBlock boundary.




Repository:
  rL LLVM

https://reviews.llvm.org/D30416

Files:
  include/llvm/IR/PatternMatch.h
  lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
  test/Transforms/InstCombine/bitfield-store.ll

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