[llvm] r295859 - MIRTests: Remove unnecessary 2>&1 redirection

Matthias Braun via llvm-commits llvm-commits at lists.llvm.org
Wed Feb 22 10:47:43 PST 2017


Author: matze
Date: Wed Feb 22 12:47:41 2017
New Revision: 295859

URL: http://llvm.org/viewvc/llvm-project?rev=295859&view=rev
Log:
MIRTests: Remove unnecessary 2>&1 redirection

llc mir output goes to stdout nowadays, so the 2>&1 is not necessary
anymore for most tests.

Modified:
    llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-add.mir
    llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-and.mir
    llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir
    llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-combines.mir
    llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir
    llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-div.mir
    llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir
    llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-fcmp.mir
    llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-fptoi.mir
    llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-gep.mir
    llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir
    llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir
    llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
    llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
    llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-or.mir
    llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-pow.mir
    llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir
    llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
    llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir
    llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir
    llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir
    llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir
    llvm/trunk/test/CodeGen/AArch64/arm64-regress-opt-cmp.mir
    llvm/trunk/test/CodeGen/AArch64/ldst-opt.mir
    llvm/trunk/test/CodeGen/AArch64/movimm-wzr.mir
    llvm/trunk/test/CodeGen/AVR/pseudo/ADCWRdRr.mir
    llvm/trunk/test/CodeGen/AVR/pseudo/ADDWRdRr.mir
    llvm/trunk/test/CodeGen/AVR/pseudo/ANDIWRdK.mir
    llvm/trunk/test/CodeGen/AVR/pseudo/ANDWRdRr.mir
    llvm/trunk/test/CodeGen/AVR/pseudo/ASRWRd.mir
    llvm/trunk/test/CodeGen/AVR/pseudo/COMWRd.mir
    llvm/trunk/test/CodeGen/AVR/pseudo/CPCWRdRr.mir
    llvm/trunk/test/CodeGen/AVR/pseudo/CPWRdRr.mir
    llvm/trunk/test/CodeGen/AVR/pseudo/EORWRdRr.mir
    llvm/trunk/test/CodeGen/AVR/pseudo/FRMIDX.mir
    llvm/trunk/test/CodeGen/AVR/pseudo/INWRdA.mir
    llvm/trunk/test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir
    llvm/trunk/test/CodeGen/AVR/pseudo/LDDWRdYQ.mir
    llvm/trunk/test/CodeGen/AVR/pseudo/LDIWRdK.mir
    llvm/trunk/test/CodeGen/AVR/pseudo/LDSWRdK.mir
    llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtr.mir
    llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir
    llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir
    llvm/trunk/test/CodeGen/AVR/pseudo/LSLWRd.mir
    llvm/trunk/test/CodeGen/AVR/pseudo/LSRWRd.mir
    llvm/trunk/test/CodeGen/AVR/pseudo/ORIWRdK.mir
    llvm/trunk/test/CodeGen/AVR/pseudo/ORWRdRr.mir
    llvm/trunk/test/CodeGen/AVR/pseudo/OUTWARr.mir
    llvm/trunk/test/CodeGen/AVR/pseudo/POPWRd.mir
    llvm/trunk/test/CodeGen/AVR/pseudo/PUSHWRr.mir
    llvm/trunk/test/CodeGen/AVR/pseudo/SBCIWRdK.mir
    llvm/trunk/test/CodeGen/AVR/pseudo/SBCWRdRr.mir
    llvm/trunk/test/CodeGen/AVR/pseudo/SEXT.mir
    llvm/trunk/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir
    llvm/trunk/test/CodeGen/AVR/pseudo/STSWKRr.mir
    llvm/trunk/test/CodeGen/AVR/pseudo/STWPtrPdRr.mir
    llvm/trunk/test/CodeGen/AVR/pseudo/STWPtrPiRr.mir
    llvm/trunk/test/CodeGen/AVR/pseudo/STWPtrRr.mir
    llvm/trunk/test/CodeGen/AVR/pseudo/SUBIWRdK.mir
    llvm/trunk/test/CodeGen/AVR/pseudo/SUBWRdRr.mir
    llvm/trunk/test/CodeGen/AVR/pseudo/ZEXT.mir
    llvm/trunk/test/CodeGen/AVR/pseudo/expand-lddw-dst-src-same.mir
    llvm/trunk/test/CodeGen/AVR/relax-mem/STDWPtrQRr.mir
    llvm/trunk/test/CodeGen/Hexagon/expand-condsets-rm-reg.mir
    llvm/trunk/test/CodeGen/MIR/Generic/llvmIRMissing.mir
    llvm/trunk/test/CodeGen/MIR/Generic/machine-basic-block-ir-block-reference.mir
    llvm/trunk/test/CodeGen/MIR/Generic/runPass.mir
    llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir
    llvm/trunk/test/CodeGen/X86/implicit-use-spill.mir

Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-add.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-add.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-add.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-add.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
 
 --- |
   target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"

Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-and.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-and.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-and.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-and.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
 
 --- |
   target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"

Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
 
 --- |
   target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"

Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-combines.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-combines.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-combines.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-combines.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
 
 --- |
   target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"

Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
 
 --- |
   target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"

Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-div.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-div.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-div.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-div.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
 
 --- |
   target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"

Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
 
 --- |
   target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"

Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-fcmp.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-fcmp.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-fcmp.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-fcmp.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
 
 --- |
   target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"

Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-fptoi.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-fptoi.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-fptoi.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-fptoi.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
 
 --- |
   target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"

Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-gep.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-gep.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-gep.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-gep.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
 
 --- |
   target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"

Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
 
 --- |
   target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"

Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
 
 --- |
   target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"

Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
 
 --- |
   target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"

Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
 
 --- |
   target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"

Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-or.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-or.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-or.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-or.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
 
 --- |
   target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"

Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-pow.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-pow.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-pow.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-pow.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
 
 --- |
   target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"

Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
 
 --- |
   target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"

Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
 
 --- |
   target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"

Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
 
 --- |
   target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"

Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
 
 --- |
   target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"

Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
 
 --- |
   target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"

Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
 
 --- |
   target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"

Modified: llvm/trunk/test/CodeGen/AArch64/arm64-regress-opt-cmp.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-regress-opt-cmp.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-regress-opt-cmp.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-regress-opt-cmp.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=aarch64-linux-gnu -run-pass peephole-opt -o - %s 2>&1 | FileCheck %s
+# RUN: llc -mtriple=aarch64-linux-gnu -run-pass peephole-opt -o - %s | FileCheck %s
 # CHECK: %1 = ANDWri {{.*}}
 # CHECK-NEXT: %wzr = SUBSWri {{.*}}
 --- |

Modified: llvm/trunk/test/CodeGen/AArch64/ldst-opt.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/ldst-opt.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/ldst-opt.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/ldst-opt.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=aarch64--linux-gnu -run-pass=aarch64-ldst-opt %s -verify-machineinstrs -o - 2>&1 | FileCheck %s
+# RUN: llc -mtriple=aarch64--linux-gnu -run-pass=aarch64-ldst-opt %s -verify-machineinstrs -o - | FileCheck %s
 ---
 name: promote-load-from-store
 tracksRegLiveness: true

Modified: llvm/trunk/test/CodeGen/AArch64/movimm-wzr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/movimm-wzr.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/movimm-wzr.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/movimm-wzr.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -run-pass=aarch64-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -run-pass=aarch64-expand-pseudo %s -o - | FileCheck %s
 
 --- |
   ; ModuleID = 'simple.ll'

Modified: llvm/trunk/test/CodeGen/AVR/pseudo/ADCWRdRr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/ADCWRdRr.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/ADCWRdRr.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/ADCWRdRr.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit add with carry pseudo instruction.
 

Modified: llvm/trunk/test/CodeGen/AVR/pseudo/ADDWRdRr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/ADDWRdRr.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/ADDWRdRr.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/ADDWRdRr.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit add pseudo instruction.
 

Modified: llvm/trunk/test/CodeGen/AVR/pseudo/ANDIWRdK.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/ANDIWRdK.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/ANDIWRdK.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/ANDIWRdK.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit ANDO pseudo instruction.
 

Modified: llvm/trunk/test/CodeGen/AVR/pseudo/ANDWRdRr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/ANDWRdRr.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/ANDWRdRr.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/ANDWRdRr.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit AND pseudo instruction.
 

Modified: llvm/trunk/test/CodeGen/AVR/pseudo/ASRWRd.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/ASRWRd.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/ASRWRd.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/ASRWRd.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 --- |
   target triple = "avr--"

Modified: llvm/trunk/test/CodeGen/AVR/pseudo/COMWRd.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/COMWRd.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/COMWRd.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/COMWRd.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit COM pseudo instruction.
 

Modified: llvm/trunk/test/CodeGen/AVR/pseudo/CPCWRdRr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/CPCWRdRr.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/CPCWRdRr.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/CPCWRdRr.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit CPCW pseudo instruction.
 

Modified: llvm/trunk/test/CodeGen/AVR/pseudo/CPWRdRr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/CPWRdRr.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/CPWRdRr.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/CPWRdRr.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit CPW pseudo instruction.
 

Modified: llvm/trunk/test/CodeGen/AVR/pseudo/EORWRdRr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/EORWRdRr.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/EORWRdRr.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/EORWRdRr.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit EOR pseudo instruction.
 

Modified: llvm/trunk/test/CodeGen/AVR/pseudo/FRMIDX.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/FRMIDX.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/FRMIDX.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/FRMIDX.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # TODO: Write this test.
 # This instruction isn't expanded by the pseudo expansion passs, but

Modified: llvm/trunk/test/CodeGen/AVR/pseudo/INWRdA.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/INWRdA.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/INWRdA.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/INWRdA.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 --- |
   target triple = "avr--"

Modified: llvm/trunk/test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -O0  %s -o - 2>&1 -march=avr | FileCheck %s
+# RUN: llc -O0  %s -o - -march=avr | FileCheck %s
 
 # This test checks the expansion of the 16-bit 'LDDWRdPtrQ' pseudo instruction.
 

Modified: llvm/trunk/test/CodeGen/AVR/pseudo/LDDWRdYQ.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/LDDWRdYQ.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/LDDWRdYQ.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/LDDWRdYQ.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -O0  %s -o - 2>&1 -march=avr | FileCheck %s
+# RUN: llc -O0  %s -o - -march=avr | FileCheck %s
 
 # This test checks the expansion of the 16-bit 'LDDWRdYQ instruction
 

Modified: llvm/trunk/test/CodeGen/AVR/pseudo/LDIWRdK.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/LDIWRdK.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/LDIWRdK.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/LDIWRdK.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit LDIWRdK pseudo instruction.
 

Modified: llvm/trunk/test/CodeGen/AVR/pseudo/LDSWRdK.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/LDSWRdK.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/LDSWRdK.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/LDSWRdK.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit LDSWRdK pseudo instruction.
 

Modified: llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtr.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtr.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtr.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit LDWRdPtr pseudo instruction.
 

Modified: llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit LDWRdPtrPd pseudo instruction.
 

Modified: llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit LDWRdPtrPi pseudo instruction.
 

Modified: llvm/trunk/test/CodeGen/AVR/pseudo/LSLWRd.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/LSLWRd.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/LSLWRd.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/LSLWRd.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 --- |
   target triple = "avr--"

Modified: llvm/trunk/test/CodeGen/AVR/pseudo/LSRWRd.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/LSRWRd.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/LSRWRd.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/LSRWRd.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 --- |
   target triple = "avr--"

Modified: llvm/trunk/test/CodeGen/AVR/pseudo/ORIWRdK.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/ORIWRdK.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/ORIWRdK.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/ORIWRdK.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit OR pseudo instruction.
 

Modified: llvm/trunk/test/CodeGen/AVR/pseudo/ORWRdRr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/ORWRdRr.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/ORWRdRr.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/ORWRdRr.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit OR pseudo instruction.
 

Modified: llvm/trunk/test/CodeGen/AVR/pseudo/OUTWARr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/OUTWARr.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/OUTWARr.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/OUTWARr.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 --- |
   target triple = "avr--"

Modified: llvm/trunk/test/CodeGen/AVR/pseudo/POPWRd.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/POPWRd.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/POPWRd.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/POPWRd.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 --- |
   target triple = "avr--"

Modified: llvm/trunk/test/CodeGen/AVR/pseudo/PUSHWRr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/PUSHWRr.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/PUSHWRr.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/PUSHWRr.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 --- |
   target triple = "avr--"

Modified: llvm/trunk/test/CodeGen/AVR/pseudo/SBCIWRdK.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/SBCIWRdK.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/SBCIWRdK.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/SBCIWRdK.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit subtraction with carry pseudo instruction.
 

Modified: llvm/trunk/test/CodeGen/AVR/pseudo/SBCWRdRr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/SBCWRdRr.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/SBCWRdRr.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/SBCWRdRr.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit subtraction with carry pseudo instruction.
 

Modified: llvm/trunk/test/CodeGen/AVR/pseudo/SEXT.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/SEXT.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/SEXT.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/SEXT.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 --- |
   target triple = "avr--"

Modified: llvm/trunk/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo  %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo  %s -o - | FileCheck %s
 
 --- |
   target triple = "avr--"

Modified: llvm/trunk/test/CodeGen/AVR/pseudo/STSWKRr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/STSWKRr.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/STSWKRr.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/STSWKRr.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit STSWRdK pseudo instruction.
 

Modified: llvm/trunk/test/CodeGen/AVR/pseudo/STWPtrPdRr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/STWPtrPdRr.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/STWPtrPdRr.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/STWPtrPdRr.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 --- |
   target triple = "avr--"

Modified: llvm/trunk/test/CodeGen/AVR/pseudo/STWPtrPiRr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/STWPtrPiRr.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/STWPtrPiRr.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/STWPtrPiRr.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 --- |
   target triple = "avr--"

Modified: llvm/trunk/test/CodeGen/AVR/pseudo/STWPtrRr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/STWPtrRr.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/STWPtrRr.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/STWPtrRr.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit STSWRdK pseudo instruction.
 

Modified: llvm/trunk/test/CodeGen/AVR/pseudo/SUBIWRdK.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/SUBIWRdK.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/SUBIWRdK.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/SUBIWRdK.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit subtraction pseudo instruction.
 

Modified: llvm/trunk/test/CodeGen/AVR/pseudo/SUBWRdRr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/SUBWRdRr.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/SUBWRdRr.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/SUBWRdRr.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit subtraction pseudo instruction.
 

Modified: llvm/trunk/test/CodeGen/AVR/pseudo/ZEXT.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/ZEXT.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/ZEXT.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/ZEXT.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 --- |
   target triple = "avr--"

Modified: llvm/trunk/test/CodeGen/AVR/pseudo/expand-lddw-dst-src-same.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/expand-lddw-dst-src-same.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/expand-lddw-dst-src-same.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/expand-lddw-dst-src-same.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -O0 %s -o - 2>&1 -march=avr | FileCheck %s
+# RUN: llc -O0 %s -o - -march=avr | FileCheck %s
 
 # This test ensures that the pseudo expander can correctly handle the case
 # where we are expanding a 16-bit LDD instruction where the source and

Modified: llvm/trunk/test/CodeGen/AVR/relax-mem/STDWPtrQRr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/relax-mem/STDWPtrQRr.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/relax-mem/STDWPtrQRr.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/relax-mem/STDWPtrQRr.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-relax-mem %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-relax-mem %s -o - | FileCheck %s
 
 --- |
   target triple = "avr--"

Modified: llvm/trunk/test/CodeGen/Hexagon/expand-condsets-rm-reg.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/expand-condsets-rm-reg.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/expand-condsets-rm-reg.mir (original)
+++ llvm/trunk/test/CodeGen/Hexagon/expand-condsets-rm-reg.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -march=hexagon -run-pass expand-condsets -o - 2>&1 %s -verify-machineinstrs -debug-only=expand-condsets | FileCheck %s
+# RUN: llc -march=hexagon -run-pass expand-condsets -o - %s -verify-machineinstrs -debug-only=expand-condsets | FileCheck %s
 # REQUIRES: asserts
 
 # Check that coalesced registers are removed from live intervals.

Modified: llvm/trunk/test/CodeGen/MIR/Generic/llvmIRMissing.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Generic/llvmIRMissing.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/Generic/llvmIRMissing.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/Generic/llvmIRMissing.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -run-pass none -o - %s 2>&1 | FileCheck %s
+# RUN: llc -run-pass none -o - %s | FileCheck %s
 # This test ensures that the MIR parser accepts files without the LLVM IR.
 
 ---

Modified: llvm/trunk/test/CodeGen/MIR/Generic/machine-basic-block-ir-block-reference.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Generic/machine-basic-block-ir-block-reference.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/Generic/machine-basic-block-ir-block-reference.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/Generic/machine-basic-block-ir-block-reference.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -run-pass none -o - %s 2>&1 | FileCheck %s
+# RUN: llc -run-pass none -o - %s | FileCheck %s
 # This test ensures that the MIR parser preserves unnamed LLVM IR block
 # references.
 

Modified: llvm/trunk/test/CodeGen/MIR/Generic/runPass.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Generic/runPass.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/Generic/runPass.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/Generic/runPass.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -run-pass=greedy -debug-pass=Arguments -o - %s 2>&1 | FileCheck %s
+# RUN: llc -run-pass=greedy -debug-pass=Arguments -o - %s | FileCheck %s
 
 # Check that passes are initialized correctly, so that it's possible to
 # use -run-pass.

Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -march=x86-64 -run-pass none -o - %s 2>&1 | FileCheck %s
+# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
 
 --- |
 

Modified: llvm/trunk/test/CodeGen/X86/implicit-use-spill.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/implicit-use-spill.mir?rev=295859&r1=295858&r2=295859&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/implicit-use-spill.mir (original)
+++ llvm/trunk/test/CodeGen/X86/implicit-use-spill.mir Wed Feb 22 12:47:41 2017
@@ -1,4 +1,4 @@
-# RUN: llc -run-pass=greedy -mtriple=x86_64-apple-macosx -o - %s 2>&1 | FileCheck %s
+# RUN: llc -run-pass=greedy -mtriple=x86_64-apple-macosx -o - %s | FileCheck %s
 
 # Make sure we don't assert when we try to reload a value that is just implicitly used.
 ---




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