[PATCH] D29813: [DAGCombiner] Fix DebugLoc propagation when folding !(x cc y) -> (x !cc y)

[Taewook Oh via Phabricator via llvm-commits]

twoh added inline comments.


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Comment at: test/CodeGen/X86/avx512-fsel.ll:15
 ; CHECK-NEXT:    vucomiss %xmm1, %xmm0
-; CHECK-NEXT:    setnp %cl
-; CHECK-NEXT:    sete %dl
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mkuper wrote:
> A drive-by comment: please don't manually change auto-generate tests - rather, rerun the script. You shouldn't need CHECK-DAG here anyway, since the scheduling is supposed to be deterministic.
> 
> (Also, I'm a bit confused. I can understand SDLoc changes affecting scheduling if we do source-order scheduling, but why would this make a difference for IR input that doesn't have any line info to begin with?)
Sorry, I missed the note. Thanks for the comments, and I will update the test again.

Even if there's no line info, SelectionDAGBuilder::SDNodeOrder is still maintained during the process (https://github.com/llvm-mirror/llvm/blob/master/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp#L942), and used to set SDNode::IROrder. For example, here (https://github.com/llvm-mirror/llvm/blob/master/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp#L1009) getCurSDLoc generates SDLoc that takes SelectionDAGBuilder::SDNodeOrder as its IROrder, and this values eventually passed to the SDNode constructor for IROrder. 


https://reviews.llvm.org/D29813