[llvm] r295336 - [DAGCombiner] Support {a|s}ext, {a|z|s}ext load nodes in load combine

Artur Pilipenko via llvm-commits llvm-commits at lists.llvm.org
Mon Feb 20 06:09:46 PST 2017


I’m currently on vacation until Feb 27. Can you please revert the change for now and I will take a look at the failures once I return.

Artur

On 20 Feb 2017, at 08:51, Bill Seurer <seurer at linux.vnet.ibm.com<mailto:seurer at linux.vnet.ibm.com>> wrote:


This causes numerous failures when a bootstrapped clang is used to compile the tests on a powerpc BE (but not LE) system.

see http://lab.llvm.org:8011/builders/clang-ppc64be-linux-multistage/builds/2315

One example:

FAILED: projects/compiler-rt/lib/tsan/tests/unit/tsan_clock_test.cc.powerpc64.o
cd /home/buildbots/ppc64be-clang-multistage-test/clang-ppc64be-multistage/stage2/projects/compiler-rt/lib/tsan/tests/unit && /home/buildbots/ppc64be-clang-multistage-test/clang-ppc64be-multistage/stage2/./bin/clang -fPIC -fvisibility-inlines-hidden -Wall -W -Wno-unused-parameter -Wwrite-strings -Wcast-qual -Wmissing-field-initializers -pedantic -Wno-long-long -Wcovered-switch-default -Wnon-virtual-dtor -Wdelete-non-virtual-dtor -Wstring-conversion -Werror=date-time -std=c++11 -fcolor-diagnostics -ffunction-sections -fdata-sections -Wall -std=c++11 -Wno-unused-parameter -Wno-unknown-warning-option -fPIC -fno-builtin -fno-exceptions -fomit-frame-pointer -funwind-tables -fno-stack-protector -fno-sanitize=safe-stack -fvisibility=hidden -fvisibility-inlines-hidden -fno-lto -O3 -gline-tables-only -Wno-gnu -Wno-variadic-macros -Wno-c99-extensions -Wno-non-virtual-dtor -fPIE -fno-rtti -Wno-covered-switch-default -DGTEST_NO_LLVM_RAW_OSTREAM=1 -DGTEST_HAS_RTTI=0 -I/home/buildbots/ppc64be-clang-multistage-test/clang-ppc64be-multistage/llvm/utils/unittest/googletest/include -I/home/buildbots/ppc64be-clang-multistage-test/clang-ppc64be-multistage/llvm/utils/unittest/googletest -I/home/buildbots/ppc64be-clang-multistage-test/clang-ppc64be-multistage/llvm/projects/compiler-rt/lib -I/home/buildbots/ppc64be-clang-multistage-test/clang-ppc64be-multistage/llvm/projects/compiler-rt/lib/tsan/rtl -DGTEST_HAS_RTTI=0 -m64 -c -o tsan_clock_test.cc.powerpc64.o /home/buildbots/ppc64be-clang-multistage-test/clang-ppc64be-multistage/llvm/projects/compiler-rt/lib/tsan/tests/unit/tsan_clock_test.cc
In file included from /home/buildbots/ppc64be-clang-multistage-test/clang-ppc64be-multistage/llvm/projects/compiler-rt/lib/tsan/tests/unit/tsan_clock_test.cc:13:
/home/buildbots/ppc64be-clang-multistage-test/clang-ppc64be-multistage/llvm/projects/compiler-rt/lib/tsan/rtl/tsan_clock.h:15:1: error: expected unqualified-id
^
clang-5.0: /home/buildbots/ppc64be-clang-multistage-test/clang-ppc64be-multistage/llvm/tools/clang/include/clang/Lex/Lexer.h:189: void clang::Lexer::SetCommentRetentionState(bool): Assertion `!isKeepWhitespaceMode() && "Can't play with comment retention state when retaining whitespace"' failed.
#0 0x0000000011adc818 PrintStackTraceSignalHandler(void*) (/home/buildbots/ppc64be-clang-multistage-test/clang-ppc64be-multistage/stage2/bin/clang-5.0+0x11adc818)
#1 0x0000000011adcc8c SignalHandler(int) (/home/buildbots/ppc64be-clang-multistage-test/clang-ppc64be-multistage/stage2/bin/clang-5.0+0x11adcc8c)
#2 0x00003fff971a04d8 (linux-vdso64.so.1+0x4d8)
#3 0x00003fff96b0f988 __GI_raise (/lib64/power7/libc.so.6+0x5f988)
#4 0x00003fff96b1213c __GI_abort (/lib64/power7/libc.so.6+0x6213c)
#5 0x00003fff96b05028 __assert_fail_base (/lib64/power7/libc.so.6+0x55028)
#6 0x00003fff96b0511c __GI___assert_fail (/lib64/power7/libc.so.6+0x5511c)
#7 0x00000000139ee2d0 clang::Lexer::resetExtendedTokenMode() (/home/buildbots/ppc64be-clang-multistage-test/clang-ppc64be-multistage/stage2/bin/clang-5.0+0x139ee2d0)
#8 0x0000000013a26070 clang::Preprocessor::SkipExcludedConditionalBlock(clang::SourceLocation, bool, bool, clang::SourceLocation) (/home/buildbots/ppc64be-clang-multistage-test/clang-ppc64be-multistage/stage2/bin/clang-5.0+0x13a26070)
#9 0x0000000013a294a0 clang::Preprocessor::HandleIfDirective(clang::Token&, bool) (/home/buildbots/ppc64be-clang-multistage-test/clang-ppc64be-multistage/stage2/bin/clang-5.0+0x13a294a0)
#10 0x0000000013a283b0 clang::Preprocessor::HandleDirective(clang::Token&) (/home/buildbots/ppc64be-clang-multistage-test/clang-ppc64be-multistage/stage2/bin/clang-5.0+0x13a283b0)
#11 0x00000000139fd484 clang::Lexer::LexTokenInternal(clang::Token&, bool) (/home/buildbots/ppc64be-clang-multistage-test/clang-ppc64be-multistage/stage2/bin/clang-5.0+0x139fd484)
#12 0x00000000139f92ac clang::Lexer::Lex(clang::Token&) (/home/buildbots/ppc64be-clang-multistage-test/clang-ppc64be-multistage/stage2/bin/clang-5.0+0x139f92ac)
#13 0x0000000013a6498c clang::Preprocessor::Lex(clang::Token&) (/home/buildbots/ppc64be-clang-multistage-test/clang-ppc64be-multistage/stage2/bin/clang-5.0+0x13a6498c)
#14 0x0000000012a23dc0 clang::Parser::ConsumeAnyToken(bool) (/home/buildbots/ppc64be-clang-multistage-test/clang-ppc64be-multistage/stage2/bin/clang-5.0+0x12a23dc0)
#15 0x0000000012a46b94 clang::Parser::SkipMalformedDecl() (/home/buildbots/ppc64be-clang-multistage-test/clang-ppc64be-multistage/stage2/bin/clang-5.0+0x12a46b94)
#16 0x0000000012a456c4 clang::Parser::ParseDeclGroup(clang::ParsingDeclSpec&, unsigned int, clang::SourceLocation*, clang::Parser::ForRangeInit*) (/home/buildbots/ppc64be-clang-multistage-test/clang-ppc64be-multistage/stage2/bin/clang-5.0+0x12a456c4)
#17 0x0000000012a2a488 clang::Parser::ParseDeclOrFunctionDefInternal(clang::Parser::ParsedAttributesWithRange&, clang::ParsingDeclSpec&, clang::AccessSpecifier) (/home/buildbots/ppc64be-clang-multistage-test/clang-ppc64be-multistage/stage2/bin/clang-5.0+0x12a2a488)
#18 0x0000000012a29c08 clang::Parser::ParseDeclarationOrFunctionDefinition(clang::Parser::ParsedAttributesWithRange&, clang::ParsingDeclSpec*, clang::AccessSpecifier) (/home/buildbots/ppc64be-clang-multistage-test/clang-ppc64be-multistage/stage2/bin/clang-5.0+0x12a29c08)
#19 0x0000000012a28bd0 clang::Parser::ParseExternalDeclaration(clang::Parser::ParsedAttributesWithRange&, clang::ParsingDeclSpec*) (/home/buildbots/ppc64be-clang-multistage-test/clang-ppc64be-multistage/stage2/bin/clang-5.0+0x12a28bd0)
#20 0x0000000012a27b94 clang::Parser::ParseTopLevelDecl(clang::OpaquePtr<clang::DeclGroupRef>&) (/home/buildbots/ppc64be-clang-multistage-test/clang-ppc64be-multistage/stage2/bin/clang-5.0+0x12a27b94)
#21 0x0000000012a272f0 clang::Parser::ParseFirstTopLevelDecl(clang::OpaquePtr<clang::DeclGroupRef>&) (/home/buildbots/ppc64be-clang-multistage-test/clang-ppc64be-multistage/stage2/bin/clang-5.0+0x12a272f0)
#22 0x0000000012a221a0 clang::ParseAST(clang::Sema&, bool, bool) (/home/buildbots/ppc64be-clang-multistage-test/clang-ppc64be-multistage/stage2/bin/clang-5.0+0x12a221a0)
#23 0x00000000120f4f40 clang::ASTFrontendAction::ExecuteAction() (/home/buildbots/ppc64be-clang-multistage-test/clang-ppc64be-multistage/stage2/bin/clang-5.0+0x120f4f40)
#24 0x00000000124ab67c clang::CodeGenAction::ExecuteAction() (/home/buildbots/ppc64be-clang-multistage-test/clang-ppc64be-multistage/stage2/bin/clang-5.0+0x124ab67c)
#25 0x00000000120f4548 clang::FrontendAction::Execute() (/home/buildbots/ppc64be-clang-multistage-test/clang-ppc64be-multistage/stage2/bin/clang-5.0+0x120f4548)
#26 0x00000000120af8dc clang::CompilerInstance::ExecuteAction(clang::FrontendAction&) (/home/buildbots/ppc64be-clang-multistage-test/clang-ppc64be-multistage/stage2/bin/clang-5.0+0x120af8dc)
#27 0x00000000121a3ae0 clang::ExecuteCompilerInvocation(clang::CompilerInstance*) (/home/buildbots/ppc64be-clang-multistage-test/clang-ppc64be-multistage/stage2/bin/clang-5.0+0x121a3ae0)
#28 0x0000000010418bb0 cc1_main(llvm::ArrayRef<char const*>, char const*, void*) (/home/buildbots/ppc64be-clang-multistage-test/clang-ppc64be-multistage/stage2/bin/clang-5.0+0x10418bb0)
#29 0x0000000010416bb0 main (/home/buildbots/ppc64be-clang-multistage-test/clang-ppc64be-multistage/stage2/bin/clang-5.0+0x10416bb0)
#30 0x00003fff96af4ea8 generic_start_main.isra.0 (/lib64/power7/libc.so.6+0x44ea8)
#31 0x00003fff96af50d8 __libc_start_main (/lib64/power7/libc.so.6+0x450d8)
Stack dump:
0.      Program arguments: /home/buildbots/ppc64be-clang-multistage-test/clang-ppc64be-multistage/stage2/bin/clang-5.0 -cc1 -triple powerpc64-unknown-linux-gnu -emit-obj -disable-free -main-file-name tsan_clock_test.cc -mrelocation-model pic -pic-level 2 -pic-is-pie -mthread-model posix -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu ppc64 -mfloat-abi hard -target-abi elfv1 -dwarf-column-info -debug-info-kind=line-tables-only -dwarf-version=4 -debugger-tuning=gdb -ffunction-sections -fdata-sections -coverage-notes-file /home/buildbots/ppc64be-clang-multistage-test/clang-ppc64be-multistage/stage2/projects/compiler-rt/lib/tsan/tests/unit/tsan_clock_test.cc.powerpc64.gcno -resource-dir /home/buildbots/ppc64be-clang-multistage-test/clang-ppc64be-multistage/stage2/bin/../lib/clang/5.0.0 -D GTEST_NO_LLVM_RAW_OSTREAM=1 -D GTEST_HAS_RTTI=0 -I /home/buildbots/ppc64be-clang-multistage-test/clang-ppc64be-multistage/llvm/utils/unittest/googletest/include -I /home/buildbots/ppc64be-clang-multistage-test/clang-ppc64be-multistage/llvm/utils/unittest/googletest -I /home/buildbots/ppc64be-clang-multistage-test/clang-ppc64be-multistage/llvm/projects/compiler-rt/lib -I /home/buildbots/ppc64be-clang-multistage-test/clang-ppc64be-multistage/llvm/projects/compiler-rt/lib/tsan/rtl -D GTEST_HAS_RTTI=0 -internal-isystem /usr/lib/gcc/ppc64-redhat-linux/6.2.1/../../../../include/c++/6.2.1 -internal-isystem /usr/lib/gcc/ppc64-redhat-linux/6.2.1/../../../../include/c++/6.2.1/ppc64-redhat-linux -internal-isystem /usr/lib/gcc/ppc64-redhat-linux/6.2.1/../../../../include/c++/6.2.1/backward -internal-isystem /usr/local/include -internal-isystem /home/buildbots/ppc64be-clang-multistage-test/clang-ppc64be-multistage/stage2/bin/../lib/clang/5.0.0/include -internal-externc-isystem /include -internal-externc-isystem /usr/include -O3 -Wall -W -Wno-unused-parameter -Wwrite-strings -Wcast-qual -Wmissing-field-initializers -Wno-long-long -Wcovered-switch-default -Wnon-virtual-dtor -Wdelete-non-virtual-dtor -Wstring-conversion -Werror=date-time -Wall -Wno-unused-parameter -Wno-unknown-warning-option -Wno-gnu -Wno-variadic-macros -Wno-c99-extensions -Wno-non-virtual-dtor -Wno-covered-switch-default -pedantic -std=c++11 -fdeprecated-macro -fdebug-compilation-dir /home/buildbots/ppc64be-clang-multistage-test/clang-ppc64be-multistage/stage2/projects/compiler-rt/lib/tsan/tests/unit -ferror-limit 19 -fmessage-length 0 -fvisibility hidden -fvisibility-inlines-hidden -fno-builtin -fno-rtti -fno-signed-char -fobjc-runtime=gcc -fdiagnostics-show-option -fcolor-diagnostics -vectorize-loops -vectorize-slp -o tsan_clock_test.cc.powerpc64.o -x c++ /home/buildbots/ppc64be-clang-multistage-test/clang-ppc64be-multistage/llvm/projects/compiler-rt/lib/tsan/tests/unit/tsan_clock_test.cc
1.      /home/buildbots/ppc64be-clang-multistage-test/clang-ppc64be-multistage/llvm/projects/compiler-rt/lib/sanitizer_common/sanitizer_platform.h:33:2: current parser token 'if'
clang-5.0: error: unable to execute command: Aborted
clang-5.0: error: clang frontend command failed due to signal (use -v to see invocation)
clang version 5.0.0 (trunk 295336)
Target: powerpc64-unknown-linux-gnu
Thread model: posix
InstalledDir: /home/buildbots/ppc64be-clang-multistage-test/clang-ppc64be-multistage/stage2/./bin
clang-5.0: note: diagnostic msg: PLEASE submit a bug report to http://llvm.org/bugs/ and include the crash backtrace, preprocessed source, and associated run script.
clang-5.0: error: unable to execute command: Aborted
clang-5.0: note: diagnostic msg: Error generating preprocessed source(s).


On 02/16/2017 11:07 AM, Artur Pilipenko via llvm-commits wrote:

Author: apilipenko
Date: Thu Feb 16 11:07:27 2017
New Revision: 295336

URL: http://llvm.org/viewvc/llvm-project?rev=295336&view=rev
Log:
[DAGCombiner] Support {a|s}ext, {a|z|s}ext load nodes in load combine

Resubmit -r295314 with PowerPC and AMDGPU tests updated.

Support {a|s}ext, {a|z|s}ext load nodes as a part of load combine patters.

Reviewed By: filcab

Differential Revision: https://reviews.llvm.org/D29591

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/trunk/test/CodeGen/AArch64/load-combine-big-endian.ll
    llvm/trunk/test/CodeGen/AArch64/load-combine.ll
    llvm/trunk/test/CodeGen/AMDGPU/insert_vector_elt.ll
    llvm/trunk/test/CodeGen/ARM/fp16-promote.ll
    llvm/trunk/test/CodeGen/ARM/load-combine-big-endian.ll
    llvm/trunk/test/CodeGen/ARM/load-combine.ll
    llvm/trunk/test/CodeGen/PowerPC/ppc64le-aggregates.ll
    llvm/trunk/test/CodeGen/X86/load-combine.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=295336&r1=295335&r2=295336&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Feb 16 11:07:27 2017
@@ -4446,6 +4446,8 @@ const Optional<ByteProvider> calculateBy
                : calculateByteProvider(Op->getOperand(0), Index - ByteShift,
                                        Depth + 1);
   }
+  case ISD::ANY_EXTEND:
+  case ISD::SIGN_EXTEND:
   case ISD::ZERO_EXTEND: {
     SDValue NarrowOp = Op->getOperand(0);
     unsigned NarrowBitWidth = NarrowOp.getScalarValueSizeInBits();
@@ -4453,22 +4455,32 @@ const Optional<ByteProvider> calculateBy
       return None;
     uint64_t NarrowByteWidth = NarrowBitWidth / 8;

-    return Index >= NarrowByteWidth
-               ? ByteProvider::getConstantZero()
-               : calculateByteProvider(NarrowOp, Index, Depth + 1);
+    if (Index >= NarrowByteWidth)
+      return Op.getOpcode() == ISD::ZERO_EXTEND
+                 ? Optional<ByteProvider>(ByteProvider::getConstantZero())
+                 : None;
+    else
+      return calculateByteProvider(NarrowOp, Index, Depth + 1);
   }
   case ISD::BSWAP:
     return calculateByteProvider(Op->getOperand(0), ByteWidth - Index - 1,
                                  Depth + 1);
   case ISD::LOAD: {
     auto L = cast<LoadSDNode>(Op.getNode());
+    if (L->isVolatile() || L->isIndexed())
+      return None;

-    // TODO: support ext loads
-    if (L->isVolatile() || L->isIndexed() ||
-        L->getExtensionType() != ISD::NON_EXTLOAD)
+    unsigned NarrowBitWidth = L->getMemoryVT().getSizeInBits();
+    if (NarrowBitWidth % 8 != 0)
       return None;
+    uint64_t NarrowByteWidth = NarrowBitWidth / 8;

-    return ByteProvider::getMemory(L, Index);
+    if (Index >= NarrowByteWidth)
+      return L->getExtensionType() == ISD::ZEXTLOAD
+                 ? Optional<ByteProvider>(ByteProvider::getConstantZero())
+                 : None;
+    else
+      return ByteProvider::getMemory(L, Index);
   }
   }

@@ -4548,7 +4560,6 @@ SDValue DAGCombiner::MatchLoadCombine(SD

     LoadSDNode *L = P->Load;
     assert(L->hasNUsesOfValue(1, 0) && !L->isVolatile() && !L->isIndexed() &&
-           (L->getExtensionType() == ISD::NON_EXTLOAD) &&
            "Must be enforced by calculateByteProvider");
     assert(L->getOffset().isUndef() && "Unindexed load must have undef offset");


Modified: llvm/trunk/test/CodeGen/AArch64/load-combine-big-endian.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/load-combine-big-endian.ll?rev=295336&r1=295335&r2=295336&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/load-combine-big-endian.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/load-combine-big-endian.ll Thu Feb 16 11:07:27 2017
@@ -336,11 +336,8 @@ define i32 @load_i32_by_bswap_i16(i32* %
 ; (i32) p[1] | (sext(p[0] << 16) to i32)
 define i32 @load_i32_by_sext_i16(i32* %arg) {
 ; CHECK-LABEL: load_i32_by_sext_i16:
-; CHECK: ldrh    w8, [x0]
-; CHECK-NEXT: ldrh  w0, [x0, #2]
-; CHECK-NEXT: bfi w0, w8, #16, #16
+; CHECK: ldr   w0, [x0]
 ; CHECK-NEXT: ret
-
   %tmp = bitcast i32* %arg to i16*
   %tmp1 = load i16, i16* %tmp, align 4
   %tmp2 = sext i16 %tmp1 to i32
@@ -399,7 +396,6 @@ define i32 @load_i32_by_i8_base_offset_i
 ; CHECK-NEXT: ldur  w8, [x8, #13]
 ; CHECK-NEXT: rev w0, w8
 ; CHECK-NEXT: ret
-
   %tmp = add nuw nsw i32 %i, 4
   %tmp2 = add nuw nsw i32 %i, 3
   %tmp3 = add nuw nsw i32 %i, 2

Modified: llvm/trunk/test/CodeGen/AArch64/load-combine.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/load-combine.ll?rev=295336&r1=295335&r2=295336&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/load-combine.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/load-combine.ll Thu Feb 16 11:07:27 2017
@@ -324,12 +324,8 @@ define i32 @load_i32_by_bswap_i16(i32* %
 ; (i32) p[0] | (sext(p[1] << 16) to i32)
 define i32 @load_i32_by_sext_i16(i32* %arg) {
 ; CHECK-LABEL: load_i32_by_sext_i16:
-; CHECK: ldrh    w8, [x0]
-; CHECK-NEXT: ldrh  w9, [x0, #2]
-; CHECK-NEXT: bfi w8, w9, #16, #16
-; CHECK-NEXT: mov  w0, w8
+; CHECK: ldr   w0, [x0]
 ; CHECK-NEXT: ret
-
   %tmp = bitcast i32* %arg to i16*
   %tmp1 = load i16, i16* %tmp, align 4
   %tmp2 = zext i16 %tmp1 to i32
@@ -386,7 +382,6 @@ define i32 @load_i32_by_i8_base_offset_i
 ; CHECK: add x8, x0, w1, uxtw
 ; CHECK-NEXT: ldur  w0, [x8, #13]
 ; CHECK-NEXT: ret
-
   %tmp = add nuw nsw i32 %i, 4
   %tmp2 = add nuw nsw i32 %i, 3
   %tmp3 = add nuw nsw i32 %i, 2

Modified: llvm/trunk/test/CodeGen/AMDGPU/insert_vector_elt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/insert_vector_elt.ll?rev=295336&r1=295335&r2=295336&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/insert_vector_elt.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/insert_vector_elt.ll Thu Feb 16 11:07:27 2017
@@ -1,5 +1,5 @@
-; RUN: llc -verify-machineinstrs -march=amdgcn -mattr=+max-private-element-size-16 < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
-; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -mattr=+max-private-element-size-16 < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
+; RUN: llc -verify-machineinstrs -march=amdgcn -mattr=+max-private-element-size-16 < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=GCN-NO-TONGA %s
+; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -mattr=+max-private-element-size-16 < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=GCN-TONGA %s

 ; FIXME: Broken on evergreen
 ; FIXME: For some reason the 8 and 16 vectors are being stored as
@@ -219,10 +219,7 @@ define void @dynamic_insertelement_v3i16

 ; GCN: s_waitcnt

-; GCN: buffer_load_ushort
-; GCN: buffer_load_ushort
-; GCN: buffer_load_ushort
-; GCN: buffer_load_ushort
+; GCN: buffer_load_dwordx2

 ; GCN: buffer_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, off
 define void @dynamic_insertelement_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %a, i32 %b) nounwind {
@@ -240,8 +237,9 @@ define void @dynamic_insertelement_v4i16

 ; GCN: buffer_store_byte v{{[0-9]+}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen{{$}}

-; GCN: buffer_load_ubyte
-; GCN: buffer_load_ubyte
+; GCN-NO-TONGA: buffer_load_ubyte
+; GCN-NO-TONGA: buffer_load_ubyte
+; GCN-TONGA: buffer_load_ushort

 ; GCN: buffer_store_short v{{[0-9]+}}, off
 define void @dynamic_insertelement_v2i8(<2 x i8> addrspace(1)* %out, <2 x i8> %a, i32 %b) nounwind {
@@ -261,9 +259,11 @@ define void @dynamic_insertelement_v2i8(

 ; GCN: buffer_store_byte v{{[0-9]+}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen{{$}}

-; GCN: buffer_load_ubyte
-; GCN: buffer_load_ubyte
-; GCN: buffer_load_ubyte
+; GCN-NO-TONGA: buffer_load_ubyte
+; GCN-NO-TONGA: buffer_load_ubyte
+; GCN-NO-TONGA: buffer_load_ubyte
+; GCN-TONGA: buffer_load_ushort
+; GCN-TONGA: buffer_load_ubyte

 ; GCN-DAG: buffer_store_byte v{{[0-9]+}}, off
 ; GCN-DAG: buffer_store_short v{{[0-9]+}}, off
@@ -286,10 +286,11 @@ define void @dynamic_insertelement_v3i8(

 ; GCN: buffer_store_byte v{{[0-9]+}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen{{$}}

-; GCN: buffer_load_ubyte
-; GCN: buffer_load_ubyte
-; GCN: buffer_load_ubyte
-; GCN: buffer_load_ubyte
+; GCN-NO-TONGA: buffer_load_ubyte
+; GCN-NO-TONGA: buffer_load_ubyte
+; GCN-NO-TONGA: buffer_load_ubyte
+; GCN-NO-TONGA: buffer_load_ubyte
+; GCN-TONGA: buffer_load_dword

 ; GCN: buffer_store_dword v{{[0-9]+}}, off
 define void @dynamic_insertelement_v4i8(<4 x i8> addrspace(1)* %out, <4 x i8> %a, i32 %b) nounwind {

Modified: llvm/trunk/test/CodeGen/ARM/fp16-promote.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fp16-promote.ll?rev=295336&r1=295335&r2=295336&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fp16-promote.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fp16-promote.ll Thu Feb 16 11:07:27 2017
@@ -847,21 +847,15 @@ define void @test_insertelement(half* %p
 }

 ; CHECK-ALL-LABEL: test_extractelement:
+; CHECK-VFP: push {{{.*}}, lr}
 ; CHECK-VFP: sub sp, sp, #8
-; CHECK-VFP: ldrh
-; CHECK-VFP: ldrh
-; CHECK-VFP: orr
-; CHECK-VFP: str
-; CHECK-VFP: ldrh
-; CHECK-VFP: ldrh
-; CHECK-VFP: orr
-; CHECK-VFP: str
+; CHECK-VFP: ldrd
 ; CHECK-VFP: mov
 ; CHECK-VFP: orr
 ; CHECK-VFP: ldrh
 ; CHECK-VFP: strh
 ; CHECK-VFP: add sp, sp, #8
-; CHECK-VFP: bx lr
+; CHECK-VFP: pop {{{.*}}, pc}
 ; CHECK-NOVFP: ldrh
 ; CHECK-NOVFP: strh
 ; CHECK-NOVFP: ldrh

Modified: llvm/trunk/test/CodeGen/ARM/load-combine-big-endian.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/load-combine-big-endian.ll?rev=295336&r1=295335&r2=295336&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/load-combine-big-endian.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/load-combine-big-endian.ll Thu Feb 16 11:07:27 2017
@@ -456,17 +456,12 @@ define i32 @load_i32_by_bswap_i16(i32* %
 ; (i32) p[1] | (sext(p[0] << 16) to i32)
 define i32 @load_i32_by_sext_i16(i32* %arg) {
 ; CHECK-LABEL: load_i32_by_sext_i16:
-; CHECK: ldrh  r1, [r0]
-; CHECK-NEXT: ldrh  r0, [r0, #2]
-; CHECK-NEXT: orr r0, r0, r1, lsl #16
+; CHECK: ldr  r0, [r0]
 ; CHECK-NEXT: mov pc, lr
-
+;
 ; CHECK-ARMv6-LABEL: load_i32_by_sext_i16:
-; CHECK-ARMv6: ldrh  r1, [r0]
-; CHECK-ARMv6-NEXT: ldrh  r0, [r0, #2]
-; CHECK-ARMv6-NEXT: orr r0, r0, r1, lsl #16
+; CHECK-ARMv6: ldr r0, [r0]
 ; CHECK-ARMv6-NEXT: bx  lr
-
   %tmp = bitcast i32* %arg to i16*
   %tmp1 = load i16, i16* %tmp, align 4
   %tmp2 = sext i16 %tmp1 to i32

Modified: llvm/trunk/test/CodeGen/ARM/load-combine.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/load-combine.ll?rev=295336&r1=295335&r2=295336&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/load-combine.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/load-combine.ll Thu Feb 16 11:07:27 2017
@@ -414,17 +414,12 @@ define i32 @load_i32_by_bswap_i16(i32* %
 ; (i32) p[0] | (sext(p[1] << 16) to i32)
 define i32 @load_i32_by_sext_i16(i32* %arg) {
 ; CHECK-LABEL: load_i32_by_sext_i16:
-; CHECK: ldrh  r1, [r0, #2]
-; CHECK-NEXT: ldrh  r0, [r0]
-; CHECK-NEXT: orr r0, r0, r1, lsl #16
+; CHECK: ldr  r0, [r0]
 ; CHECK-NEXT: mov pc, lr
 ;
 ; CHECK-ARMv6-LABEL: load_i32_by_sext_i16:
-; CHECK-ARMv6: ldrh  r1, [r0, #2]
-; CHECK-ARMv6-NEXT: ldrh  r0, [r0]
-; CHECK-ARMv6-NEXT: orr r0, r0, r1, lsl #16
-; CHECK-ARMv6-NEXT: bx  lr
-
+; CHECK-ARMv6: ldr  r0, [r0]
+; CHECK-ARMv6-NEXT: bx lr
   %tmp = bitcast i32* %arg to i16*
   %tmp1 = load i16, i16* %tmp, align 4
   %tmp2 = zext i16 %tmp1 to i32
@@ -492,7 +487,6 @@ define i32 @load_i32_by_i8_base_offset_i
 ; CHECK-ARMv6: add r0, r0, r1
 ; CHECK-ARMv6-NEXT: ldr r0, [r0, #13]
 ; CHECK-ARMv6-NEXT: bx  lr
-
   %tmp = add nuw nsw i32 %i, 4
   %tmp2 = add nuw nsw i32 %i, 3
   %tmp3 = add nuw nsw i32 %i, 2

Modified: llvm/trunk/test/CodeGen/PowerPC/ppc64le-aggregates.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/ppc64le-aggregates.ll?rev=295336&r1=295335&r2=295336&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/ppc64le-aggregates.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/ppc64le-aggregates.ll Thu Feb 16 11:07:27 2017
@@ -284,10 +284,7 @@ entry:
 ; CHECK-DAG: lfs 12, 12({{[0-9]+}})
 ; CHECK-DAG: lfs 13, 16({{[0-9]+}})

-; CHECK-DAG: lwz [[REG0:[0-9]+]], 0({{[0-9]+}})
-; CHECK-DAG: lwz [[REG1:[0-9]+]], 4({{[0-9]+}})
-; CHECK-DAG: sldi [[REG2:[0-9]+]], [[REG1]], 32
-; CHECK-DAG: or 10, [[REG0]], [[REG2]]
+; CHECK-DAG: ld 10, 0({{[0-9]+}})
 ; CHECK: bl test2

 declare void @test2([8 x float], [5 x float], [2 x float])

Modified: llvm/trunk/test/CodeGen/X86/load-combine.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/load-combine.ll?rev=295336&r1=295335&r2=295336&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/load-combine.ll (original)
+++ llvm/trunk/test/CodeGen/X86/load-combine.ll Thu Feb 16 11:07:27 2017
@@ -733,16 +733,8 @@ define i32 @load_i32_by_i8_bswap_base_in
 ; CHECK64-LABEL: load_i32_by_i8_bswap_base_index_offset:
 ; CHECK64:       # BB#0:
 ; CHECK64-NEXT:    movslq %esi, %rax
-; CHECK64-NEXT:    movzbl (%rdi,%rax), %ecx
-; CHECK64-NEXT:    shll $24, %ecx
-; CHECK64-NEXT:    movzbl 1(%rdi,%rax), %edx
-; CHECK64-NEXT:    shll $16, %edx
-; CHECK64-NEXT:    orl %ecx, %edx
-; CHECK64-NEXT:    movzbl 2(%rdi,%rax), %ecx
-; CHECK64-NEXT:    shll $8, %ecx
-; CHECK64-NEXT:    orl %edx, %ecx
-; CHECK64-NEXT:    movzbl 3(%rdi,%rax), %eax
-; CHECK64-NEXT:    orl %ecx, %eax
+; CHECK64-NEXT:    movl (%rdi,%rax), %eax
+; CHECK64-NEXT:    bswapl %eax
 ; CHECK64-NEXT:    retq
   %tmp = bitcast i32* %arg to i8*
   %tmp2 = getelementptr inbounds i8, i8* %tmp, i32 %arg1
@@ -835,18 +827,12 @@ define i32 @load_i32_by_sext_i16(i32* %a
 ; CHECK-LABEL: load_i32_by_sext_i16:
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; CHECK-NEXT:    movzwl (%eax), %ecx
-; CHECK-NEXT:    movzwl 2(%eax), %eax
-; CHECK-NEXT:    shll $16, %eax
-; CHECK-NEXT:    orl %ecx, %eax
+; CHECK-NEXT:    movl (%eax), %eax
 ; CHECK-NEXT:    retl
 ;
 ; CHECK64-LABEL: load_i32_by_sext_i16:
 ; CHECK64:       # BB#0:
-; CHECK64-NEXT:    movzwl (%rdi), %ecx
-; CHECK64-NEXT:    movzwl 2(%rdi), %eax
-; CHECK64-NEXT:    shll $16, %eax
-; CHECK64-NEXT:    orl %ecx, %eax
+; CHECK64-NEXT:    movl (%rdi), %eax
 ; CHECK64-NEXT:    retq
   %tmp = bitcast i32* %arg to i16*
   %tmp1 = load i16, i16* %tmp, align 1
@@ -865,24 +851,9 @@ define i32 @load_i32_by_sext_i16(i32* %a
 define i32 @load_i32_by_i8_base_offset_index(i8* %arg, i32 %i) {
 ; CHECK-LABEL: load_i32_by_i8_base_offset_index:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    pushl %esi
-; CHECK-NEXT:  .Lcfi4:
-; CHECK-NEXT:    .cfi_def_cfa_offset 8
-; CHECK-NEXT:  .Lcfi5:
-; CHECK-NEXT:    .cfi_offset %esi, -8
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %ecx
-; CHECK-NEXT:    movzbl 12(%eax,%ecx), %edx
-; CHECK-NEXT:    movzbl 13(%eax,%ecx), %esi
-; CHECK-NEXT:    shll $8, %esi
-; CHECK-NEXT:    orl %edx, %esi
-; CHECK-NEXT:    movzbl 14(%eax,%ecx), %edx
-; CHECK-NEXT:    shll $16, %edx
-; CHECK-NEXT:    orl %esi, %edx
-; CHECK-NEXT:    movzbl 15(%eax,%ecx), %eax
-; CHECK-NEXT:    shll $24, %eax
-; CHECK-NEXT:    orl %edx, %eax
-; CHECK-NEXT:    popl %esi
+; CHECK-NEXT:    movl 12(%eax,%ecx), %eax
 ; CHECK-NEXT:    retl
 ;
 ; CHECK64-LABEL: load_i32_by_i8_base_offset_index:
@@ -925,24 +896,9 @@ define i32 @load_i32_by_i8_base_offset_i
 define i32 @load_i32_by_i8_base_offset_index_2(i8* %arg, i32 %i) {
 ; CHECK-LABEL: load_i32_by_i8_base_offset_index_2:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    pushl %esi
-; CHECK-NEXT:  .Lcfi6:
-; CHECK-NEXT:    .cfi_def_cfa_offset 8
-; CHECK-NEXT:  .Lcfi7:
-; CHECK-NEXT:    .cfi_offset %esi, -8
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %ecx
-; CHECK-NEXT:    movzbl 13(%eax,%ecx), %edx
-; CHECK-NEXT:    movzbl 14(%eax,%ecx), %esi
-; CHECK-NEXT:    shll $8, %esi
-; CHECK-NEXT:    orl %edx, %esi
-; CHECK-NEXT:    movzbl 15(%eax,%ecx), %edx
-; CHECK-NEXT:    shll $16, %edx
-; CHECK-NEXT:    orl %esi, %edx
-; CHECK-NEXT:    movzbl 16(%eax,%ecx), %eax
-; CHECK-NEXT:    shll $24, %eax
-; CHECK-NEXT:    orl %edx, %eax
-; CHECK-NEXT:    popl %esi
+; CHECK-NEXT:    movl 13(%eax,%ecx), %eax
 ; CHECK-NEXT:    retl
 ;
 ; CHECK64-LABEL: load_i32_by_i8_base_offset_index_2:
@@ -996,39 +952,15 @@ define i32 @load_i32_by_i8_base_offset_i
 define i32 @load_i32_by_i8_zaext_loads(i8* %arg, i32 %arg1) {
 ; CHECK-LABEL: load_i32_by_i8_zaext_loads:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    pushl %esi
-; CHECK-NEXT:  .Lcfi8:
-; CHECK-NEXT:    .cfi_def_cfa_offset 8
-; CHECK-NEXT:  .Lcfi9:
-; CHECK-NEXT:    .cfi_offset %esi, -8
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %ecx
-; CHECK-NEXT:    movzbl 12(%eax,%ecx), %edx
-; CHECK-NEXT:    movzbl 13(%eax,%ecx), %esi
-; CHECK-NEXT:    shll $8, %esi
-; CHECK-NEXT:    orl %edx, %esi
-; CHECK-NEXT:    movzbl 14(%eax,%ecx), %edx
-; CHECK-NEXT:    shll $16, %edx
-; CHECK-NEXT:    orl %esi, %edx
-; CHECK-NEXT:    movzbl 15(%eax,%ecx), %eax
-; CHECK-NEXT:    shll $24, %eax
-; CHECK-NEXT:    orl %edx, %eax
-; CHECK-NEXT:    popl %esi
+; CHECK-NEXT:    movl 12(%eax,%ecx), %eax
 ; CHECK-NEXT:    retl
 ;
 ; CHECK64-LABEL: load_i32_by_i8_zaext_loads:
 ; CHECK64:       # BB#0:
 ; CHECK64-NEXT:    movl %esi, %eax
-; CHECK64-NEXT:    movzbl 12(%rdi,%rax), %ecx
-; CHECK64-NEXT:    movzbl 13(%rdi,%rax), %edx
-; CHECK64-NEXT:    shll $8, %edx
-; CHECK64-NEXT:    orl %ecx, %edx
-; CHECK64-NEXT:    movzbl 14(%rdi,%rax), %ecx
-; CHECK64-NEXT:    shll $16, %ecx
-; CHECK64-NEXT:    orl %edx, %ecx
-; CHECK64-NEXT:    movzbl 15(%rdi,%rax), %eax
-; CHECK64-NEXT:    shll $24, %eax
-; CHECK64-NEXT:    orl %ecx, %eax
+; CHECK64-NEXT:    movl 12(%rdi,%rax), %eax
 ; CHECK64-NEXT:    retq
   %tmp = add nuw nsw i32 %arg1, 3
   %tmp2 = add nuw nsw i32 %arg1, 2
@@ -1076,39 +1008,15 @@ define i32 @load_i32_by_i8_zaext_loads(i
 define i32 @load_i32_by_i8_zsext_loads(i8* %arg, i32 %arg1) {
 ; CHECK-LABEL: load_i32_by_i8_zsext_loads:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    pushl %esi
-; CHECK-NEXT:  .Lcfi10:
-; CHECK-NEXT:    .cfi_def_cfa_offset 8
-; CHECK-NEXT:  .Lcfi11:
-; CHECK-NEXT:    .cfi_offset %esi, -8
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %ecx
-; CHECK-NEXT:    movzbl 12(%eax,%ecx), %edx
-; CHECK-NEXT:    movzbl 13(%eax,%ecx), %esi
-; CHECK-NEXT:    shll $8, %esi
-; CHECK-NEXT:    orl %edx, %esi
-; CHECK-NEXT:    movzbl 14(%eax,%ecx), %edx
-; CHECK-NEXT:    shll $16, %edx
-; CHECK-NEXT:    orl %esi, %edx
-; CHECK-NEXT:    movsbl 15(%eax,%ecx), %eax
-; CHECK-NEXT:    shll $24, %eax
-; CHECK-NEXT:    orl %edx, %eax
-; CHECK-NEXT:    popl %esi
+; CHECK-NEXT:    movl 12(%eax,%ecx), %eax
 ; CHECK-NEXT:    retl
 ;
 ; CHECK64-LABEL: load_i32_by_i8_zsext_loads:
 ; CHECK64:       # BB#0:
 ; CHECK64-NEXT:    movl %esi, %eax
-; CHECK64-NEXT:    movzbl 12(%rdi,%rax), %ecx
-; CHECK64-NEXT:    movzbl 13(%rdi,%rax), %edx
-; CHECK64-NEXT:    shll $8, %edx
-; CHECK64-NEXT:    orl %ecx, %edx
-; CHECK64-NEXT:    movzbl 14(%rdi,%rax), %ecx
-; CHECK64-NEXT:    shll $16, %ecx
-; CHECK64-NEXT:    orl %edx, %ecx
-; CHECK64-NEXT:    movsbl 15(%rdi,%rax), %eax
-; CHECK64-NEXT:    shll $24, %eax
-; CHECK64-NEXT:    orl %ecx, %eax
+; CHECK64-NEXT:    movl 12(%rdi,%rax), %eax
 ; CHECK64-NEXT:    retq
   %tmp = add nuw nsw i32 %arg1, 3
   %tmp2 = add nuw nsw i32 %arg1, 2


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