[llvm] r295254 - GlobalISel: support translating va_arg

Thu Feb 16 17:23:49 PST 2017

Hi Tim,

> On Feb 15, 2017, at 3:22 PM, Tim Northover via llvm-commits <llvm-commits at lists.llvm.org> wrote:
> 
> Author: tnorthover
> Date: Wed Feb 15 17:22:33 2017
> New Revision: 295254
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=295254&view=rev
> Log:
> GlobalISel: support translating va_arg
> 
> Since (say) i128 and [16 x i8] map to the same type in generic MIR, we also
> need to attach the required alignment info.
> 
> Modified:
>    llvm/trunk/include/llvm/CodeGen/GlobalISel/IRTranslator.h
>    llvm/trunk/include/llvm/Target/GenericOpcodes.td
>    llvm/trunk/include/llvm/Target/TargetOpcodes.def
>    llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp
>    llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
> 
> Modified: llvm/trunk/include/llvm/CodeGen/GlobalISel/IRTranslator.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/GlobalISel/IRTranslator.h?rev=295254&r1=295253&r2=295254&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/CodeGen/GlobalISel/IRTranslator.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/GlobalISel/IRTranslator.h Wed Feb 15 17:22:33 2017
> @@ -300,6 +300,8 @@ private:
>     return translateBinaryOp(TargetOpcode::G_FREM, U, MIRBuilder);
>   }
> 
> +  bool translateVAArg(const User &U, MachineIRBuilder &MIRBuilder);
> +
>   // Stubs to keep the compiler happy while we implement the rest of the
>   // translation.
>   bool translateResume(const User &U, MachineIRBuilder &MIRBuilder) {
> @@ -338,9 +340,6 @@ private:
>   bool translateUserOp2(const User &U, MachineIRBuilder &MIRBuilder) {
>     return false;
>   }
> -  bool translateVAArg(const User &U, MachineIRBuilder &MIRBuilder) {
> -    return false;
> -  }
>   bool translateExtractElement(const User &U, MachineIRBuilder &MIRBuilder) {
>     return false;
>   }
> 
> Modified: llvm/trunk/include/llvm/Target/GenericOpcodes.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/GenericOpcodes.td?rev=295254&r1=295253&r2=295254&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/Target/GenericOpcodes.td (original)
> +++ llvm/trunk/include/llvm/Target/GenericOpcodes.td Wed Feb 15 17:22:33 2017
> @@ -98,6 +98,14 @@ def G_VASTART : Instruction {
>   let mayStore = 1;
> }
> 
> +def G_VAARG : Instruction {
> +  let OutOperandList = (outs type0:$val);
> +  let InOperandList = (ins type1:$list, unknown:$align);
> +  let hasSideEffects = 0;
> +  let mayLoad = 1;
> +  let mayStore = 1;
> +}
> +
> //------------------------------------------------------------------------------
> // Binary ops.
> //------------------------------------------------------------------------------
> 
> Modified: llvm/trunk/include/llvm/Target/TargetOpcodes.def
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetOpcodes.def?rev=295254&r1=295253&r2=295254&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/Target/TargetOpcodes.def (original)
> +++ llvm/trunk/include/llvm/Target/TargetOpcodes.def Wed Feb 15 17:22:33 2017
> @@ -283,6 +283,9 @@ HANDLE_TARGET_OPCODE(G_FCONSTANT)
> /// Generic va_start instruction. Stores to its one pointer operand.
> HANDLE_TARGET_OPCODE(G_VASTART)
> 
> +/// Generic va_start instruction. Stores to its one pointer operand.
> +HANDLE_TARGET_OPCODE(G_VAARG)
> +
> // Generic sign extend
> HANDLE_TARGET_OPCODE(G_SEXT)
> 
> 
> Modified: llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp?rev=295254&r1=295253&r2=295254&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp (original)
> +++ llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp Wed Feb 15 17:22:33 2017
> @@ -906,6 +906,18 @@ bool IRTranslator::translateAlloca(const
>   return true;
> }
> 
> +bool IRTranslator::translateVAArg(const User &U, MachineIRBuilder &MIRBuilder) {
> +  // FIXME: We may need more info about the type. Because of how LLT works,
> +  // we're completely discarding the i64/double distinction here (amongst
> +  // others). Fortunately the ABIs I know of where that matters don't use va_arg
> +  // anyway but that's not guaranteed.

Forward looking question: Would that mean more argument to the G_VAARG instruction, or more complex LLT?
If the latter, should we think about keeping information about structure while we are here? (In particular the padding bits that we know we can optimize.)

Cheers,
-Quentin

> +  MIRBuilder.buildInstr(TargetOpcode::G_VAARG)
> +    .addDef(getOrCreateVReg(U))
> +    .addUse(getOrCreateVReg(*U.getOperand(0)))
> +    .addImm(DL->getABITypeAlignment(U.getType()));
> +  return true;
> +}
> +
> bool IRTranslator::translatePHI(const User &U, MachineIRBuilder &MIRBuilder) {
>   const PHINode &PI = cast<PHINode>(U);
>   auto MIB = MIRBuilder.buildInstr(TargetOpcode::PHI);
> 
> Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll?rev=295254&r1=295253&r2=295254&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll (original)
> +++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll Wed Feb 15 17:22:33 2017
> @@ -1134,6 +1134,19 @@ define void @test_va_end(i8* %list) {
>   ret void
> }
> 
> +define void @test_va_arg(i8* %list) {
> +; CHECK-LABEL: test_va_arg
> +; CHECK: [[LIST:%[0-9]+]](p0) = COPY %x0
> +; CHECK: G_VAARG [[LIST]](p0), 8
> +; CHECK: G_VAARG [[LIST]](p0), 1
> +; CHECK: G_VAARG [[LIST]](p0), 16
> +
> +  %v0 = va_arg i8* %list, i64
> +  %v1 = va_arg i8* %list, i8
> +  %v2 = va_arg i8* %list, i128
> +  ret void
> +}
> +
> declare float @llvm.pow.f32(float, float)
> define float @test_pow_intrin(float %l, float %r) {
> ; CHECK-LABEL: name: test_pow_intrin
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at lists.llvm.org
> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits