[llvm] r295213 - [DAG] Don't try to create an INSERT_SUBVECTOR with an illegal source

[Justin Bogner via llvm-commits]

LGTM

Michael Kuperstein <mkuper at google.com> writes:
> +Justin
>
> On Wed, Feb 15, 2017 at 10:54 AM, Michael Kuperstein <mkuper at google.com>
> wrote:
>
>> Hans, this fixes a regression I introduced in r281402.
>>
>> Assuming this sticks, is it too late to merge into 4.0? I believe this
>> should be safe, as all it does is add a case where we bail out of a combine.
>> (The right PR number is PR31956.)
>>
>> Thanks,
>>   Michael
>>
>> On Wed, Feb 15, 2017 at 10:37 AM, Michael Kuperstein via llvm-commits <
>> llvm-commits at lists.llvm.org> wrote:
>>
>>> Author: mkuper
>>> Date: Wed Feb 15 12:37:26 2017
>>> New Revision: 295213
>>>
>>> URL: http://llvm.org/viewvc/llvm-project?rev=295213&view=rev
>>> Log:
>>> [DAG] Don't try to create an INSERT_SUBVECTOR with an illegal source
>>>
>>> We currently can't legalize those, but we should really not be creating
>>> them in the first place, since legalization would probably look similar
>>> to the
>>> way we legalize CONCAT_VECTORS - basically replace the INSERT with a
>>> BUILD.
>>>
>>> This fixes PR311956.
>>>
>>> Differential Revision: https://reviews.llvm.org/D29961
>>>
>>> Added:
>>>     llvm/trunk/test/CodeGen/X86/pr31956.ll
>>> Modified:
>>>     llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
>>>
>>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/
>>> SelectionDAG/DAGCombiner.cpp?rev=295213&r1=295212&r2=295213&view=diff
>>> ============================================================
>>> ==================
>>> --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
>>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Feb 15
>>> 12:37:26 2017
>>> @@ -13374,9 +13374,15 @@ SDValue DAGCombiner::createBuildVecShuff
>>>              !TLI.isOperationLegal(ISD::VECTOR_SHUFFLE, InVT1))
>>>            return SDValue();
>>>
>>> -        if (InVT1 != InVT2)
>>> +        // Legalizing INSERT_SUBVECTOR is tricky - you basically have to
>>> +        // lower it back into a BUILD_VECTOR. So if the inserted type is
>>> +        // illegal, don't even try.
>>> +        if (InVT1 != InVT2) {
>>> +          if (!TLI.isTypeLegal(InVT2))
>>> +            return SDValue();
>>>            VecIn2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, InVT1,
>>>                                 DAG.getUNDEF(InVT1), VecIn2, ZeroIdx);
>>> +        }
>>>          ShuffleNumElems = NumElems * 2;
>>>        } else {
>>>          // Both VecIn1 and VecIn2 are wider than the output, and VecIn2
>>> is wider
>>>
>>> Added: llvm/trunk/test/CodeGen/X86/pr31956.ll
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/
>>> X86/pr31956.ll?rev=295213&view=auto
>>> ============================================================
>>> ==================
>>> --- llvm/trunk/test/CodeGen/X86/pr31956.ll (added)
>>> +++ llvm/trunk/test/CodeGen/X86/pr31956.ll Wed Feb 15 12:37:26 2017
>>> @@ -0,0 +1,25 @@
>>> +; NOTE: Assertions have been autogenerated by
>>> utils/update_llc_test_checks.py
>>> +; RUN: llc -mattr=+avx < %s | FileCheck %s
>>> +target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
>>> +target triple = "x86_64-scei-ps4"
>>> +
>>> + at G1 = common global <2 x float> zeroinitializer, align 8
>>> + at G2 = common global <8 x float> zeroinitializer, align 32
>>> +
>>> +define <4 x float> @foo() {
>>> +; CHECK-LABEL: foo:
>>> +; CHECK:       # BB#0: # %entry
>>> +; CHECK-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
>>> +; CHECK-NEXT:    vblendpd {{.*#+}} ymm0 = ymm0[0],mem[1,2,3]
>>> +; CHECK-NEXT:    vextractf128 $1, %ymm0, %xmm1
>>> +; CHECK-NEXT:    vshufps {{.*#+}} xmm0 = xmm1[0,2],xmm0[2,0]
>>> +; CHECK-NEXT:    vpermilps {{.*#+}} xmm0 = xmm0[0,2,1,3]
>>> +; CHECK-NEXT:    vzeroupper
>>> +; CHECK-NEXT:    retq
>>> +entry:
>>> +  %V = load <2 x float>, <2 x float>* @G1, align 8
>>> +  %shuffle = shufflevector <2 x float> %V, <2 x float> undef, <8 x i32>
>>> <i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 undef, i32 undef,
>>> i32 undef>
>>> +  %L = load <8 x float>, <8 x float>* @G2, align 32
>>> +  %shuffle1 = shufflevector <8 x float> %shuffle, <8 x float> %L, <4 x
>>> i32> <i32 12, i32 10, i32 14, i32 4>
>>> +  ret <4 x float> %shuffle1
>>> +}
>>>
>>>
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>>
>>