[llvm] r295177 - [X86] Regenerate i64 ext-load on 32-bit target tests

Simon Pilgrim via llvm-commits llvm-commits at lists.llvm.org
Wed Feb 15 06:06:17 PST 2017


Author: rksimon
Date: Wed Feb 15 08:06:17 2017
New Revision: 295177

URL: http://llvm.org/viewvc/llvm-project?rev=295177&view=rev
Log:
[X86] Regenerate i64 ext-load on 32-bit target tests

Modified:
    llvm/trunk/test/CodeGen/X86/2012-07-10-extload64.ll

Modified: llvm/trunk/test/CodeGen/X86/2012-07-10-extload64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2012-07-10-extload64.ll?rev=295177&r1=295176&r2=295177&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2012-07-10-extload64.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2012-07-10-extload64.ll Wed Feb 15 08:06:17 2017
@@ -1,32 +1,42 @@
-; RUN: llc < %s -march=x86 -mcpu=corei7 -mtriple=i686-pc-win32 | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-pc-win32 -mcpu=corei7 | FileCheck %s
 
-; CHECK: load_store
 define void @load_store(<4 x i16>* %in) {
+; CHECK-LABEL: load_store:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    pmovzxwd {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
+; CHECK-NEXT:    paddw %xmm0, %xmm0
+; CHECK-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
+; CHECK-NEXT:    movq %xmm0, (%eax)
+; CHECK-NEXT:    retl
 entry:
-; CHECK: pmovzxwd
   %A27 = load <4 x i16>, <4 x i16>* %in, align 4
   %A28 = add <4 x i16> %A27, %A27
-; CHECK: movq
   store <4 x i16> %A28, <4 x i16>* %in, align 4
   ret void
-; CHECK: ret
 }
 
 ; Make sure that we store a 64bit value, even on 32bit systems.
-;CHECK-LABEL: store_64:
 define void @store_64(<2 x i32>* %ptr) {
+; CHECK-LABEL: store_64:
+; CHECK:       # BB#0: # %BB
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    xorps %xmm0, %xmm0
+; CHECK-NEXT:    movlps %xmm0, (%eax)
+; CHECK-NEXT:    retl
 BB:
   store <2 x i32> zeroinitializer, <2 x i32>* %ptr
   ret void
-;CHECK: movlps
-;CHECK: ret
 }
 
-;CHECK-LABEL: load_64:
 define <2 x i32> @load_64(<2 x i32>* %ptr) {
+; CHECK-LABEL: load_64:
+; CHECK:       # BB#0: # %BB
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    pmovzxdq {{.*#+}} xmm0 = mem[0],zero,mem[1],zero
+; CHECK-NEXT:    retl
 BB:
   %t = load <2 x i32>, <2 x i32>* %ptr
   ret <2 x i32> %t
-;CHECK: pmovzxdq
-;CHECK: ret
 }




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