[PATCH] D29938: [RISCV 16/n] Support and tests for a variety of additional LLVM IR constructs

[Alex Bradbury via Phabricator via llvm-commits]

asb created this revision.

Previous patches primarily ensured that codegen was possible for the standard RISC-V instructions. However, there are a number of IR inputs that wouldn't be appropriately lowered. This patch both adds test cases and supports lowering for a number of these cases:

- Improved sext/zext/trunc support
- Support for setcc variants that don't map directly to RISC-V instructions
- Lowering mul, and hence support for external symbols
- addc, adde, subc, sube
- mulhs, srem, mulhu, urem, udiv, sdiv
- {srl,sra,shl}_parts
- Bare select
- brind

A future patch will fix the TODOs regarding the cases where a register is wasted holding 0.


https://reviews.llvm.org/D29938

Files:
  lib/Target/RISCV/RISCVISelLowering.cpp
  lib/Target/RISCV/RISCVISelLowering.h
  lib/Target/RISCV/RISCVInstrInfo.td
  lib/Target/RISCV/RISCVMCInstLower.cpp
  test/CodeGen/RISCV/addc-adde-sube-subc.ll
  test/CodeGen/RISCV/alu.ll
  test/CodeGen/RISCV/bare-select.ll
  test/CodeGen/RISCV/div.ll
  test/CodeGen/RISCV/indirectbr.ll
  test/CodeGen/RISCV/mul.ll
  test/CodeGen/RISCV/rem.ll
  test/CodeGen/RISCV/setcc.ll
  test/CodeGen/RISCV/sext-zext-trunc.ll
  test/CodeGen/RISCV/shifts.ll

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