[PATCH] D23566: [RISCV 8/10] Add support for all RV32I instructions

[Alex Bradbury via Phabricator via llvm-commits]

asb updated this revision to Diff 88307.
asb marked 3 inline comments as done.
asb added a comment.

Refresh patch and incorporate suggestion from @jyknight regarding FENCE and FENCEI (thanks!).

I _think_ the discussion about naming immediate types was resolved with the use of `simm13_lsb0`, but let me know if there are still concerns. Using semantic names like `branchimm` or similar isn't ideal as the names may not hold for further RISC-V extensions (out-of-tree custom extensions or future standard extensions). `imm_frm_r`, `imm_frm_i` or similar could be an option, but I'm not really seeing a strong advantage. Input welcome though.


https://reviews.llvm.org/D23566

Files:
  lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
  lib/Target/RISCV/RISCVInstrInfo.td
  test/MC/RISCV/rv32i-invalid.s
  test/MC/RISCV/rv32i-valid.s

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