[PATCH] D29887: [mips] divide macro instruction cleanup.

[Sagar Thakur via Phabricator via llvm-commits]

slthakur accepted this revision.
slthakur added a comment.
This revision is now accepted and ready to land.

LGTM with minor nits.



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Comment at: lib/Target/Mips/AsmParser/MipsAsmParser.cpp:3416
+//
+// Notably we don't have emit a warning when encountering $rt is the $zero
+// register, or 0 as an immediate. processInstruction() has already done that.
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Should this be like -> "Notably we don't have **to** emit a warning when encountering $rt **as** the $zero register"?


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Comment at: lib/Target/Mips/AsmParser/MipsAsmParser.cpp:3419
+//
+// The destination register should $zero register should only be seen in
+// the immediate case.
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Could you please rephrase this statement so that it is clear to understand?


https://reviews.llvm.org/D29887