[llvm] r294753 - [Hexagon] Replace instruction definitions with auto-generated ones
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 10 07:33:15 PST 2017
Added: llvm/trunk/lib/Target/Hexagon/HexagonDepMappings.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonDepMappings.td?rev=294753&view=auto
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonDepMappings.td (added)
+++ llvm/trunk/lib/Target/Hexagon/HexagonDepMappings.td Fri Feb 10 09:33:13 2017
@@ -0,0 +1,654 @@
+//===--- HexagonDepMappings.td --------------------------------------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+def A2_negAlias : InstAlias<"$Rd32=neg($Rs32)", (A2_subri IntRegs:$Rd32, 0, IntRegs:$Rs32)>;
+def A2_notAlias : InstAlias<"$Rd32=not($Rs32)", (A2_subri IntRegs:$Rd32, -1, IntRegs:$Rs32)>;
+def A2_tfrfAlias : InstAlias<"if (!$Pu4) $Rd32=$Rs32", (A2_paddif IntRegs:$Rd32, PredRegs:$Pu4, IntRegs:$Rs32, 0)>;
+def A2_tfrfnewAlias : InstAlias<"if (!$Pu4.new) $Rd32=$Rs32", (A2_paddifnew IntRegs:$Rd32, PredRegs:$Pu4, IntRegs:$Rs32, 0)>;
+def A2_tfrtAlias : InstAlias<"if ($Pu4) $Rd32=$Rs32", (A2_paddit IntRegs:$Rd32, PredRegs:$Pu4, IntRegs:$Rs32, 0)>;
+def A2_tfrtnewAlias : InstAlias<"if ($Pu4.new) $Rd32=$Rs32", (A2_padditnew IntRegs:$Rd32, PredRegs:$Pu4, IntRegs:$Rs32, 0)>;
+def A2_vaddb_mapAlias : InstAlias<"$Rdd32=vaddb($Rss32,$Rtt32)", (A2_vaddub DoubleRegs:$Rdd32, DoubleRegs:$Rss32, DoubleRegs:$Rtt32)>;
+def A2_vsubb_mapAlias : InstAlias<"$Rdd32=vsubb($Rss32,$Rtt32)", (A2_vsubub DoubleRegs:$Rdd32, DoubleRegs:$Rss32, DoubleRegs:$Rtt32)>;
+def A2_zxtbAlias : InstAlias<"$Rd32=zxtb($Rs32)", (A2_andir IntRegs:$Rd32, IntRegs:$Rs32, 255)>;
+def C2_cmpltAlias : InstAlias<"$Pd4=cmp.lt($Rs32,$Rt32)", (C2_cmpgt PredRegs:$Pd4, IntRegs:$Rt32, IntRegs:$Rs32)>;
+def C2_cmpltuAlias : InstAlias<"$Pd4=cmp.ltu($Rs32,$Rt32)", (C2_cmpgtu PredRegs:$Pd4, IntRegs:$Rt32, IntRegs:$Rs32)>;
+def C2_pxfer_mapAlias : InstAlias<"$Pd4=$Ps4", (C2_or PredRegs:$Pd4, PredRegs:$Ps4, PredRegs:$Ps4)>;
+def J2_jumpf_nopred_mapAlias : InstAlias<"if (!$Pu4) jump $Ii", (J2_jumpf PredRegs:$Pu4, b30_2Imm:$Ii)>;
+def J2_jumprf_nopred_mapAlias : InstAlias<"if (!$Pu4) jumpr $Rs32", (J2_jumprf PredRegs:$Pu4, IntRegs:$Rs32)>;
+def J2_jumprt_nopred_mapAlias : InstAlias<"if ($Pu4) jumpr $Rs32", (J2_jumprt PredRegs:$Pu4, IntRegs:$Rs32)>;
+def J2_jumpt_nopred_mapAlias : InstAlias<"if ($Pu4) jump $Ii", (J2_jumpt PredRegs:$Pu4, b30_2Imm:$Ii)>;
+def L2_loadalignb_zomapAlias : InstAlias<"$Ryy32=memb_fifo($Rs32)", (L2_loadalignb_io DoubleRegs:$Ryy32, IntRegs:$Rs32, 0)>;
+def L2_loadalignh_zomapAlias : InstAlias<"$Ryy32=memh_fifo($Rs32)", (L2_loadalignh_io DoubleRegs:$Ryy32, IntRegs:$Rs32, 0)>;
+def L2_loadbsw2_zomapAlias : InstAlias<"$Rd32=membh($Rs32)", (L2_loadbsw2_io IntRegs:$Rd32, IntRegs:$Rs32, 0)>;
+def L2_loadbsw4_zomapAlias : InstAlias<"$Rdd32=membh($Rs32)", (L2_loadbsw4_io DoubleRegs:$Rdd32, IntRegs:$Rs32, 0)>;
+def L2_loadbzw2_zomapAlias : InstAlias<"$Rd32=memubh($Rs32)", (L2_loadbzw2_io IntRegs:$Rd32, IntRegs:$Rs32, 0)>;
+def L2_loadbzw4_zomapAlias : InstAlias<"$Rdd32=memubh($Rs32)", (L2_loadbzw4_io DoubleRegs:$Rdd32, IntRegs:$Rs32, 0)>;
+def L2_loadrb_zomapAlias : InstAlias<"$Rd32=memb($Rs32)", (L2_loadrb_io IntRegs:$Rd32, IntRegs:$Rs32, 0)>;
+def L2_loadrd_zomapAlias : InstAlias<"$Rdd32=memd($Rs32)", (L2_loadrd_io DoubleRegs:$Rdd32, IntRegs:$Rs32, 0)>;
+def L2_loadrh_zomapAlias : InstAlias<"$Rd32=memh($Rs32)", (L2_loadrh_io IntRegs:$Rd32, IntRegs:$Rs32, 0)>;
+def L2_loadri_zomapAlias : InstAlias<"$Rd32=memw($Rs32)", (L2_loadri_io IntRegs:$Rd32, IntRegs:$Rs32, 0)>;
+def L2_loadrub_zomapAlias : InstAlias<"$Rd32=memub($Rs32)", (L2_loadrub_io IntRegs:$Rd32, IntRegs:$Rs32, 0)>;
+def L2_loadruh_zomapAlias : InstAlias<"$Rd32=memuh($Rs32)", (L2_loadruh_io IntRegs:$Rd32, IntRegs:$Rs32, 0)>;
+def L2_ploadrbf_zomapAlias : InstAlias<"if (!$Pt4) $Rd32=memb($Rs32)", (L2_ploadrbf_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
+def L2_ploadrbfnew_zomapAlias : InstAlias<"if (!$Pt4.new) $Rd32=memb($Rs32)", (L2_ploadrbfnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
+def L2_ploadrbt_zomapAlias : InstAlias<"if ($Pt4) $Rd32=memb($Rs32)", (L2_ploadrbt_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
+def L2_ploadrbtnew_zomapAlias : InstAlias<"if ($Pt4.new) $Rd32=memb($Rs32)", (L2_ploadrbtnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
+def L2_ploadrdf_zomapAlias : InstAlias<"if (!$Pt4) $Rdd32=memd($Rs32)", (L2_ploadrdf_io DoubleRegs:$Rdd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
+def L2_ploadrdfnew_zomapAlias : InstAlias<"if (!$Pt4.new) $Rdd32=memd($Rs32)", (L2_ploadrdfnew_io DoubleRegs:$Rdd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
+def L2_ploadrdt_zomapAlias : InstAlias<"if ($Pt4) $Rdd32=memd($Rs32)", (L2_ploadrdt_io DoubleRegs:$Rdd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
+def L2_ploadrdtnew_zomapAlias : InstAlias<"if ($Pt4.new) $Rdd32=memd($Rs32)", (L2_ploadrdtnew_io DoubleRegs:$Rdd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
+def L2_ploadrhf_zomapAlias : InstAlias<"if (!$Pt4) $Rd32=memh($Rs32)", (L2_ploadrhf_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
+def L2_ploadrhfnew_zomapAlias : InstAlias<"if (!$Pt4.new) $Rd32=memh($Rs32)", (L2_ploadrhfnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
+def L2_ploadrht_zomapAlias : InstAlias<"if ($Pt4) $Rd32=memh($Rs32)", (L2_ploadrht_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
+def L2_ploadrhtnew_zomapAlias : InstAlias<"if ($Pt4.new) $Rd32=memh($Rs32)", (L2_ploadrhtnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
+def L2_ploadrif_zomapAlias : InstAlias<"if (!$Pt4) $Rd32=memw($Rs32)", (L2_ploadrif_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
+def L2_ploadrifnew_zomapAlias : InstAlias<"if (!$Pt4.new) $Rd32=memw($Rs32)", (L2_ploadrifnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
+def L2_ploadrit_zomapAlias : InstAlias<"if ($Pt4) $Rd32=memw($Rs32)", (L2_ploadrit_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
+def L2_ploadritnew_zomapAlias : InstAlias<"if ($Pt4.new) $Rd32=memw($Rs32)", (L2_ploadritnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
+def L2_ploadrubf_zomapAlias : InstAlias<"if (!$Pt4) $Rd32=memub($Rs32)", (L2_ploadrubf_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
+def L2_ploadrubfnew_zomapAlias : InstAlias<"if (!$Pt4.new) $Rd32=memub($Rs32)", (L2_ploadrubfnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
+def L2_ploadrubt_zomapAlias : InstAlias<"if ($Pt4) $Rd32=memub($Rs32)", (L2_ploadrubt_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
+def L2_ploadrubtnew_zomapAlias : InstAlias<"if ($Pt4.new) $Rd32=memub($Rs32)", (L2_ploadrubtnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
+def L2_ploadruhf_zomapAlias : InstAlias<"if (!$Pt4) $Rd32=memuh($Rs32)", (L2_ploadruhf_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
+def L2_ploadruhfnew_zomapAlias : InstAlias<"if (!$Pt4.new) $Rd32=memuh($Rs32)", (L2_ploadruhfnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
+def L2_ploadruht_zomapAlias : InstAlias<"if ($Pt4) $Rd32=memuh($Rs32)", (L2_ploadruht_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
+def L2_ploadruhtnew_zomapAlias : InstAlias<"if ($Pt4.new) $Rd32=memuh($Rs32)", (L2_ploadruhtnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>;
+def L4_add_memopb_zomapAlias : InstAlias<"memb($Rs32)+=$Rt32", (L4_add_memopb_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def L4_add_memoph_zomapAlias : InstAlias<"memh($Rs32)+=$Rt32", (L4_add_memoph_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def L4_add_memopw_zomapAlias : InstAlias<"memw($Rs32)+=$Rt32", (L4_add_memopw_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def L4_and_memopb_zomapAlias : InstAlias<"memb($Rs32)&=$Rt32", (L4_and_memopb_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def L4_and_memoph_zomapAlias : InstAlias<"memh($Rs32)&=$Rt32", (L4_and_memoph_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def L4_and_memopw_zomapAlias : InstAlias<"memw($Rs32)&=$Rt32", (L4_and_memopw_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def L4_iadd_memopb_zomapAlias : InstAlias<"memb($Rs32)+=#$II", (L4_iadd_memopb_io IntRegs:$Rs32, 0, u5_0Imm:$II)>;
+def L4_iadd_memoph_zomapAlias : InstAlias<"memh($Rs32)+=#$II", (L4_iadd_memoph_io IntRegs:$Rs32, 0, u5_0Imm:$II)>;
+def L4_iadd_memopw_zomapAlias : InstAlias<"memw($Rs32)+=#$II", (L4_iadd_memopw_io IntRegs:$Rs32, 0, u5_0Imm:$II)>;
+def L4_iand_memopb_zomapAlias : InstAlias<"memb($Rs32)=clrbit(#$II)", (L4_iand_memopb_io IntRegs:$Rs32, 0, u5_0Imm:$II)>;
+def L4_iand_memoph_zomapAlias : InstAlias<"memh($Rs32)=clrbit(#$II)", (L4_iand_memoph_io IntRegs:$Rs32, 0, u5_0Imm:$II)>;
+def L4_iand_memopw_zomapAlias : InstAlias<"memw($Rs32)=clrbit(#$II)", (L4_iand_memopw_io IntRegs:$Rs32, 0, u5_0Imm:$II)>;
+def L4_ior_memopb_zomapAlias : InstAlias<"memb($Rs32)=setbit(#$II)", (L4_ior_memopb_io IntRegs:$Rs32, 0, u5_0Imm:$II)>;
+def L4_ior_memoph_zomapAlias : InstAlias<"memh($Rs32)=setbit(#$II)", (L4_ior_memoph_io IntRegs:$Rs32, 0, u5_0Imm:$II)>;
+def L4_ior_memopw_zomapAlias : InstAlias<"memw($Rs32)=setbit(#$II)", (L4_ior_memopw_io IntRegs:$Rs32, 0, u5_0Imm:$II)>;
+def L4_isub_memopb_zomapAlias : InstAlias<"memb($Rs32)-=#$II", (L4_isub_memopb_io IntRegs:$Rs32, 0, u5_0Imm:$II)>;
+def L4_isub_memoph_zomapAlias : InstAlias<"memh($Rs32)-=#$II", (L4_isub_memoph_io IntRegs:$Rs32, 0, u5_0Imm:$II)>;
+def L4_isub_memopw_zomapAlias : InstAlias<"memw($Rs32)-=#$II", (L4_isub_memopw_io IntRegs:$Rs32, 0, u5_0Imm:$II)>;
+def L4_or_memopb_zomapAlias : InstAlias<"memb($Rs32)|=$Rt32", (L4_or_memopb_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def L4_or_memoph_zomapAlias : InstAlias<"memh($Rs32)|=$Rt32", (L4_or_memoph_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def L4_or_memopw_zomapAlias : InstAlias<"memw($Rs32)|=$Rt32", (L4_or_memopw_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def L4_sub_memopb_zomapAlias : InstAlias<"memb($Rs32)-=$Rt32", (L4_sub_memopb_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def L4_sub_memoph_zomapAlias : InstAlias<"memh($Rs32)-=$Rt32", (L4_sub_memoph_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def L4_sub_memopw_zomapAlias : InstAlias<"memw($Rs32)-=$Rt32", (L4_sub_memopw_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def M2_mpyuiAlias : InstAlias<"$Rd32=mpyui($Rs32,$Rt32)", (M2_mpyi IntRegs:$Rd32, IntRegs:$Rs32, IntRegs:$Rt32)>;
+def S2_pstorerbf_zomapAlias : InstAlias<"if (!$Pv4) memb($Rs32)=$Rt32", (S2_pstorerbf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def S2_pstorerbnewf_zomapAlias : InstAlias<"if (!$Pv4) memb($Rs32)=$Nt8.new", (S2_pstorerbnewf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>;
+def S2_pstorerbnewt_zomapAlias : InstAlias<"if ($Pv4) memb($Rs32)=$Nt8.new", (S2_pstorerbnewt_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>;
+def S2_pstorerbt_zomapAlias : InstAlias<"if ($Pv4) memb($Rs32)=$Rt32", (S2_pstorerbt_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def S2_pstorerdf_zomapAlias : InstAlias<"if (!$Pv4) memd($Rs32)=$Rtt32", (S2_pstorerdf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, DoubleRegs:$Rtt32)>;
+def S2_pstorerdt_zomapAlias : InstAlias<"if ($Pv4) memd($Rs32)=$Rtt32", (S2_pstorerdt_io PredRegs:$Pv4, IntRegs:$Rs32, 0, DoubleRegs:$Rtt32)>;
+def S2_pstorerff_zomapAlias : InstAlias<"if (!$Pv4) memh($Rs32)=$Rt32.h", (S2_pstorerff_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def S2_pstorerft_zomapAlias : InstAlias<"if ($Pv4) memh($Rs32)=$Rt32.h", (S2_pstorerft_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def S2_pstorerhf_zomapAlias : InstAlias<"if (!$Pv4) memh($Rs32)=$Rt32", (S2_pstorerhf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def S2_pstorerhnewf_zomapAlias : InstAlias<"if (!$Pv4) memh($Rs32)=$Nt8.new", (S2_pstorerhnewf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>;
+def S2_pstorerhnewt_zomapAlias : InstAlias<"if ($Pv4) memh($Rs32)=$Nt8.new", (S2_pstorerhnewt_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>;
+def S2_pstorerht_zomapAlias : InstAlias<"if ($Pv4) memh($Rs32)=$Rt32", (S2_pstorerht_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def S2_pstorerif_zomapAlias : InstAlias<"if (!$Pv4) memw($Rs32)=$Rt32", (S2_pstorerif_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def S2_pstorerinewf_zomapAlias : InstAlias<"if (!$Pv4) memw($Rs32)=$Nt8.new", (S2_pstorerinewf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>;
+def S2_pstorerinewt_zomapAlias : InstAlias<"if ($Pv4) memw($Rs32)=$Nt8.new", (S2_pstorerinewt_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>;
+def S2_pstorerit_zomapAlias : InstAlias<"if ($Pv4) memw($Rs32)=$Rt32", (S2_pstorerit_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def S2_storerb_zomapAlias : InstAlias<"memb($Rs32)=$Rt32", (S2_storerb_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def S2_storerbnew_zomapAlias : InstAlias<"memb($Rs32)=$Nt8.new", (S2_storerbnew_io IntRegs:$Rs32, 0, IntRegs:$Nt8)>;
+def S2_storerd_zomapAlias : InstAlias<"memd($Rs32)=$Rtt32", (S2_storerd_io IntRegs:$Rs32, 0, DoubleRegs:$Rtt32)>;
+def S2_storerf_zomapAlias : InstAlias<"memh($Rs32)=$Rt32.h", (S2_storerf_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def S2_storerh_zomapAlias : InstAlias<"memh($Rs32)=$Rt32", (S2_storerh_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def S2_storerhnew_zomapAlias : InstAlias<"memh($Rs32)=$Nt8.new", (S2_storerhnew_io IntRegs:$Rs32, 0, IntRegs:$Nt8)>;
+def S2_storeri_zomapAlias : InstAlias<"memw($Rs32)=$Rt32", (S2_storeri_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def S2_storerinew_zomapAlias : InstAlias<"memw($Rs32)=$Nt8.new", (S2_storerinew_io IntRegs:$Rs32, 0, IntRegs:$Nt8)>;
+def S2_tableidxb_goodsyntaxAlias : InstAlias<"$Rx32=tableidxb($Rs32,#$Ii,#$II)", (S2_tableidxb IntRegs:$Rx32, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II)>;
+def S4_pstorerbfnew_zomapAlias : InstAlias<"if (!$Pv4.new) memb($Rs32)=$Rt32", (S4_pstorerbfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def S4_pstorerbnewfnew_zomapAlias : InstAlias<"if (!$Pv4.new) memb($Rs32)=$Nt8.new", (S4_pstorerbnewfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>;
+def S4_pstorerbnewtnew_zomapAlias : InstAlias<"if ($Pv4.new) memb($Rs32)=$Nt8.new", (S4_pstorerbnewtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>;
+def S4_pstorerbtnew_zomapAlias : InstAlias<"if ($Pv4.new) memb($Rs32)=$Rt32", (S4_pstorerbtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def S4_pstorerdfnew_zomapAlias : InstAlias<"if (!$Pv4.new) memd($Rs32)=$Rtt32", (S4_pstorerdfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, DoubleRegs:$Rtt32)>;
+def S4_pstorerdtnew_zomapAlias : InstAlias<"if ($Pv4.new) memd($Rs32)=$Rtt32", (S4_pstorerdtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, DoubleRegs:$Rtt32)>;
+def S4_pstorerffnew_zomapAlias : InstAlias<"if (!$Pv4.new) memh($Rs32)=$Rt32.h", (S4_pstorerffnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def S4_pstorerftnew_zomapAlias : InstAlias<"if ($Pv4.new) memh($Rs32)=$Rt32.h", (S4_pstorerftnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def S4_pstorerhfnew_zomapAlias : InstAlias<"if (!$Pv4.new) memh($Rs32)=$Rt32", (S4_pstorerhfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def S4_pstorerhnewfnew_zomapAlias : InstAlias<"if (!$Pv4.new) memh($Rs32)=$Nt8.new", (S4_pstorerhnewfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>;
+def S4_pstorerhnewtnew_zomapAlias : InstAlias<"if ($Pv4.new) memh($Rs32)=$Nt8.new", (S4_pstorerhnewtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>;
+def S4_pstorerhtnew_zomapAlias : InstAlias<"if ($Pv4.new) memh($Rs32)=$Rt32", (S4_pstorerhtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def S4_pstorerifnew_zomapAlias : InstAlias<"if (!$Pv4.new) memw($Rs32)=$Rt32", (S4_pstorerifnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def S4_pstorerinewfnew_zomapAlias : InstAlias<"if (!$Pv4.new) memw($Rs32)=$Nt8.new", (S4_pstorerinewfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>;
+def S4_pstorerinewtnew_zomapAlias : InstAlias<"if ($Pv4.new) memw($Rs32)=$Nt8.new", (S4_pstorerinewtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>;
+def S4_pstoreritnew_zomapAlias : InstAlias<"if ($Pv4.new) memw($Rs32)=$Rt32", (S4_pstoreritnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>;
+def S4_storeirb_zomapAlias : InstAlias<"memb($Rs32)=#$II", (S4_storeirb_io IntRegs:$Rs32, 0, s32_0Imm:$II)>;
+def S4_storeirbf_zomapAlias : InstAlias<"if (!$Pv4) memb($Rs32)=#$II", (S4_storeirbf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>;
+def S4_storeirbfnew_zomapAlias : InstAlias<"if (!$Pv4.new) memb($Rs32)=#$II", (S4_storeirbfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>;
+def S4_storeirbt_zomapAlias : InstAlias<"if ($Pv4) memb($Rs32)=#$II", (S4_storeirbt_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>;
+def S4_storeirbtnew_zomapAlias : InstAlias<"if ($Pv4.new) memb($Rs32)=#$II", (S4_storeirbtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>;
+def S4_storeirh_zomapAlias : InstAlias<"memh($Rs32)=#$II", (S4_storeirh_io IntRegs:$Rs32, 0, s32_0Imm:$II)>;
+def S4_storeirhf_zomapAlias : InstAlias<"if (!$Pv4) memh($Rs32)=#$II", (S4_storeirhf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>;
+def S4_storeirhfnew_zomapAlias : InstAlias<"if (!$Pv4.new) memh($Rs32)=#$II", (S4_storeirhfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>;
+def S4_storeirht_zomapAlias : InstAlias<"if ($Pv4) memh($Rs32)=#$II", (S4_storeirht_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>;
+def S4_storeirhtnew_zomapAlias : InstAlias<"if ($Pv4.new) memh($Rs32)=#$II", (S4_storeirhtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>;
+def S4_storeiri_zomapAlias : InstAlias<"memw($Rs32)=#$II", (S4_storeiri_io IntRegs:$Rs32, 0, s32_0Imm:$II)>;
+def S4_storeirif_zomapAlias : InstAlias<"if (!$Pv4) memw($Rs32)=#$II", (S4_storeirif_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>;
+def S4_storeirifnew_zomapAlias : InstAlias<"if (!$Pv4.new) memw($Rs32)=#$II", (S4_storeirifnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>;
+def S4_storeirit_zomapAlias : InstAlias<"if ($Pv4) memw($Rs32)=#$II", (S4_storeirit_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>;
+def S4_storeiritnew_zomapAlias : InstAlias<"if ($Pv4.new) memw($Rs32)=#$II", (S4_storeiritnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>;
+def V6_MAP_equbAlias : InstAlias<"$Qd4=vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb VecPredRegs:$Qd4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_MAP_equb_128BAlias : InstAlias<"$Qd4=vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb VecPredRegs:$Qd4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_MAP_equb_andAlias : InstAlias<"$Qx4&=vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb_and VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_MAP_equb_and_128BAlias : InstAlias<"$Qx4&=vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb_and VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_MAP_equb_iorAlias : InstAlias<"$Qx4|=vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb_or VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_MAP_equb_ior_128BAlias : InstAlias<"$Qx4|=vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb_or VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_MAP_equb_xorAlias : InstAlias<"$Qx4^=vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb_xor VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_MAP_equb_xor_128BAlias : InstAlias<"$Qx4^=vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb_xor VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_MAP_equhAlias : InstAlias<"$Qd4=vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh VecPredRegs:$Qd4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_MAP_equh_128BAlias : InstAlias<"$Qd4=vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh VecPredRegs:$Qd4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_MAP_equh_andAlias : InstAlias<"$Qx4&=vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh_and VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_MAP_equh_and_128BAlias : InstAlias<"$Qx4&=vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh_and VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_MAP_equh_iorAlias : InstAlias<"$Qx4|=vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh_or VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_MAP_equh_ior_128BAlias : InstAlias<"$Qx4|=vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh_or VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_MAP_equh_xorAlias : InstAlias<"$Qx4^=vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh_xor VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_MAP_equh_xor_128BAlias : InstAlias<"$Qx4^=vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh_xor VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_MAP_equwAlias : InstAlias<"$Qd4=vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw VecPredRegs:$Qd4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_MAP_equw_128BAlias : InstAlias<"$Qd4=vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw VecPredRegs:$Qd4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_MAP_equw_andAlias : InstAlias<"$Qx4&=vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw_and VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_MAP_equw_and_128BAlias : InstAlias<"$Qx4&=vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw_and VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_MAP_equw_iorAlias : InstAlias<"$Qx4|=vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw_or VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_MAP_equw_ior_128BAlias : InstAlias<"$Qx4|=vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw_or VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_MAP_equw_xorAlias : InstAlias<"$Qx4^=vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw_xor VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_MAP_equw_xor_128BAlias : InstAlias<"$Qx4^=vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw_xor VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_extractw_altAlias : InstAlias<"$Rd32.w=vextract($Vu32,$Rs32)", (V6_extractw IntRegs:$Rd32, VectorRegs:$Vu32, IntRegs:$Rs32)>, Requires<[UseHVX]>;
+def V6_extractw_alt_128BAlias : InstAlias<"$Rd32.w=vextract($Vu32,$Rs32)", (V6_extractw IntRegs:$Rd32, VectorRegs:$Vu32, IntRegs:$Rs32)>, Requires<[UseHVX]>;
+def V6_ld0Alias : InstAlias<"$Vd32=vmem($Rt32)", (V6_vL32b_ai VectorRegs:$Vd32, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>;
+def V6_ld0_128BAlias : InstAlias<"$Vd32=vmem($Rt32)", (V6_vL32b_ai VectorRegs:$Vd32, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>;
+def V6_ldnt0Alias : InstAlias<"$Vd32=vmem($Rt32):nt", (V6_vL32b_nt_ai VectorRegs:$Vd32, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>;
+def V6_ldnt0_128BAlias : InstAlias<"$Vd32=vmem($Rt32):nt", (V6_vL32b_nt_ai VectorRegs:$Vd32, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>;
+def V6_ldu0Alias : InstAlias<"$Vd32=vmemu($Rt32)", (V6_vL32Ub_ai VectorRegs:$Vd32, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>;
+def V6_ldu0_128BAlias : InstAlias<"$Vd32=vmemu($Rt32)", (V6_vL32Ub_ai VectorRegs:$Vd32, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>;
+def V6_st0Alias : InstAlias<"vmem($Rt32)=$Vs32", (V6_vS32b_ai IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>;
+def V6_st0_128BAlias : InstAlias<"vmem($Rt32)=$Vs32", (V6_vS32b_ai IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>;
+def V6_stn0Alias : InstAlias<"vmem($Rt32)=$Os8.new", (V6_vS32b_new_ai IntRegs:$Rt32, 0, VectorRegs:$Os8)>, Requires<[UseHVX]>;
+def V6_stn0_128BAlias : InstAlias<"vmem($Rt32)=$Os8.new", (V6_vS32b_new_ai IntRegs:$Rt32, 0, VectorRegs:$Os8)>, Requires<[UseHVX]>;
+def V6_stnnt0Alias : InstAlias<"vmem($Rt32):nt=$Os8.new", (V6_vS32b_nt_new_ai IntRegs:$Rt32, 0, VectorRegs:$Os8)>, Requires<[UseHVX]>;
+def V6_stnnt0_128BAlias : InstAlias<"vmem($Rt32):nt=$Os8.new", (V6_vS32b_nt_new_ai IntRegs:$Rt32, 0, VectorRegs:$Os8)>, Requires<[UseHVX]>;
+def V6_stnp0Alias : InstAlias<"if (!$Pv4) vmem($Rt32)=$Vs32", (V6_vS32b_npred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>;
+def V6_stnp0_128BAlias : InstAlias<"if (!$Pv4) vmem($Rt32)=$Vs32", (V6_vS32b_npred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>;
+def V6_stnpnt0Alias : InstAlias<"if (!$Pv4) vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_npred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>;
+def V6_stnpnt0_128BAlias : InstAlias<"if (!$Pv4) vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_npred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>;
+def V6_stnq0Alias : InstAlias<"if (!$Qv4) vmem($Rt32)=$Vs32", (V6_vS32b_nqpred_ai VecPredRegs:$Qv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>;
+def V6_stnq0_128BAlias : InstAlias<"if (!$Qv4) vmem($Rt32)=$Vs32", (V6_vS32b_nqpred_ai VecPredRegs:$Qv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>;
+def V6_stnqnt0Alias : InstAlias<"if (!$Qv4) vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_nqpred_ai VecPredRegs:$Qv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>;
+def V6_stnqnt0_128BAlias : InstAlias<"if (!$Qv4) vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_nqpred_ai VecPredRegs:$Qv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>;
+def V6_stnt0Alias : InstAlias<"vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_ai IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>;
+def V6_stnt0_128BAlias : InstAlias<"vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_ai IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>;
+def V6_stp0Alias : InstAlias<"if ($Pv4) vmem($Rt32)=$Vs32", (V6_vS32b_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>;
+def V6_stp0_128BAlias : InstAlias<"if ($Pv4) vmem($Rt32)=$Vs32", (V6_vS32b_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>;
+def V6_stpnt0Alias : InstAlias<"if ($Pv4) vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>;
+def V6_stpnt0_128BAlias : InstAlias<"if ($Pv4) vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>;
+def V6_stq0Alias : InstAlias<"if ($Qv4) vmem($Rt32)=$Vs32", (V6_vS32b_qpred_ai VecPredRegs:$Qv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>;
+def V6_stq0_128BAlias : InstAlias<"if ($Qv4) vmem($Rt32)=$Vs32", (V6_vS32b_qpred_ai VecPredRegs:$Qv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>;
+def V6_stqnt0Alias : InstAlias<"if ($Qv4) vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_qpred_ai VecPredRegs:$Qv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>;
+def V6_stqnt0_128BAlias : InstAlias<"if ($Qv4) vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_qpred_ai VecPredRegs:$Qv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>;
+def V6_stu0Alias : InstAlias<"vmemu($Rt32)=$Vs32", (V6_vS32Ub_ai IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>;
+def V6_stu0_128BAlias : InstAlias<"vmemu($Rt32)=$Vs32", (V6_vS32Ub_ai IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>;
+def V6_stunp0Alias : InstAlias<"if (!$Pv4) vmemu($Rt32)=$Vs32", (V6_vS32Ub_npred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>;
+def V6_stunp0_128BAlias : InstAlias<"if (!$Pv4) vmemu($Rt32)=$Vs32", (V6_vS32Ub_npred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>;
+def V6_stup0Alias : InstAlias<"if ($Pv4) vmemu($Rt32)=$Vs32", (V6_vS32Ub_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>;
+def V6_stup0_128BAlias : InstAlias<"if ($Pv4) vmemu($Rt32)=$Vs32", (V6_vS32Ub_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>;
+def V6_vabsdiffh_altAlias : InstAlias<"$Vd32=vabsdiffh($Vu32,$Vv32)", (V6_vabsdiffh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vabsdiffh_alt_128BAlias : InstAlias<"$Vd32=vabsdiffh($Vu32,$Vv32)", (V6_vabsdiffh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vabsdiffub_altAlias : InstAlias<"$Vd32=vabsdiffub($Vu32,$Vv32)", (V6_vabsdiffub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vabsdiffub_alt_128BAlias : InstAlias<"$Vd32=vabsdiffub($Vu32,$Vv32)", (V6_vabsdiffub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vabsdiffuh_altAlias : InstAlias<"$Vd32=vabsdiffuh($Vu32,$Vv32)", (V6_vabsdiffuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vabsdiffuh_alt_128BAlias : InstAlias<"$Vd32=vabsdiffuh($Vu32,$Vv32)", (V6_vabsdiffuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vabsdiffw_altAlias : InstAlias<"$Vd32=vabsdiffw($Vu32,$Vv32)", (V6_vabsdiffw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vabsdiffw_alt_128BAlias : InstAlias<"$Vd32=vabsdiffw($Vu32,$Vv32)", (V6_vabsdiffw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vabsh_altAlias : InstAlias<"$Vd32=vabsh($Vu32)", (V6_vabsh VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vabsh_alt_128BAlias : InstAlias<"$Vd32=vabsh($Vu32)", (V6_vabsh VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vabsh_sat_altAlias : InstAlias<"$Vd32=vabsh($Vu32):sat", (V6_vabsh_sat VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vabsh_sat_alt_128BAlias : InstAlias<"$Vd32=vabsh($Vu32):sat", (V6_vabsh_sat VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vabsuh_altAlias : InstAlias<"$Vd32.uh=vabs($Vu32.h)", (V6_vabsh VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vabsuh_alt_128BAlias : InstAlias<"$Vd32.uh=vabs($Vu32.h)", (V6_vabsh VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vabsuw_altAlias : InstAlias<"$Vd32.uw=vabs($Vu32.w)", (V6_vabsw VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vabsuw_alt_128BAlias : InstAlias<"$Vd32.uw=vabs($Vu32.w)", (V6_vabsw VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vabsw_altAlias : InstAlias<"$Vd32=vabsw($Vu32)", (V6_vabsw VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vabsw_alt_128BAlias : InstAlias<"$Vd32=vabsw($Vu32)", (V6_vabsw VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vabsw_sat_altAlias : InstAlias<"$Vd32=vabsw($Vu32):sat", (V6_vabsw_sat VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vabsw_sat_alt_128BAlias : InstAlias<"$Vd32=vabsw($Vu32):sat", (V6_vabsw_sat VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vaddb_altAlias : InstAlias<"$Vd32=vaddb($Vu32,$Vv32)", (V6_vaddb VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vaddb_alt_128BAlias : InstAlias<"$Vd32=vaddb($Vu32,$Vv32)", (V6_vaddb VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vaddb_dv_altAlias : InstAlias<"$Vdd32=vaddb($Vuu32,$Vvv32)", (V6_vaddb_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
+def V6_vaddb_dv_alt_128BAlias : InstAlias<"$Vdd32=vaddb($Vuu32,$Vvv32)", (V6_vaddb_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
+def V6_vaddbnq_altAlias : InstAlias<"if (!$Qv4.b) $Vx32.b+=$Vu32.b", (V6_vaddbnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vaddbnq_alt_128BAlias : InstAlias<"if (!$Qv4.b) $Vx32.b+=$Vu32.b", (V6_vaddbnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vaddbq_altAlias : InstAlias<"if ($Qv4.b) $Vx32.b+=$Vu32.b", (V6_vaddbq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vaddbq_alt_128BAlias : InstAlias<"if ($Qv4.b) $Vx32.b+=$Vu32.b", (V6_vaddbq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vaddh_altAlias : InstAlias<"$Vd32=vaddh($Vu32,$Vv32)", (V6_vaddh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vaddh_alt_128BAlias : InstAlias<"$Vd32=vaddh($Vu32,$Vv32)", (V6_vaddh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vaddh_dv_altAlias : InstAlias<"$Vdd32=vaddh($Vuu32,$Vvv32)", (V6_vaddh_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
+def V6_vaddh_dv_alt_128BAlias : InstAlias<"$Vdd32=vaddh($Vuu32,$Vvv32)", (V6_vaddh_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
+def V6_vaddhnq_altAlias : InstAlias<"if (!$Qv4.h) $Vx32.h+=$Vu32.h", (V6_vaddhnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vaddhnq_alt_128BAlias : InstAlias<"if (!$Qv4.h) $Vx32.h+=$Vu32.h", (V6_vaddhnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vaddhq_altAlias : InstAlias<"if ($Qv4.h) $Vx32.h+=$Vu32.h", (V6_vaddhq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vaddhq_alt_128BAlias : InstAlias<"if ($Qv4.h) $Vx32.h+=$Vu32.h", (V6_vaddhq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vaddhsat_altAlias : InstAlias<"$Vd32=vaddh($Vu32,$Vv32):sat", (V6_vaddhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vaddhsat_alt_128BAlias : InstAlias<"$Vd32=vaddh($Vu32,$Vv32):sat", (V6_vaddhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vaddhsat_dv_altAlias : InstAlias<"$Vdd32=vaddh($Vuu32,$Vvv32):sat", (V6_vaddhsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
+def V6_vaddhsat_dv_alt_128BAlias : InstAlias<"$Vdd32=vaddh($Vuu32,$Vvv32):sat", (V6_vaddhsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
+def V6_vaddhw_altAlias : InstAlias<"$Vdd32=vaddh($Vu32,$Vv32)", (V6_vaddhw VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vaddhw_alt_128BAlias : InstAlias<"$Vdd32=vaddh($Vu32,$Vv32)", (V6_vaddhw VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vaddubh_altAlias : InstAlias<"$Vdd32=vaddub($Vu32,$Vv32)", (V6_vaddubh VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vaddubh_alt_128BAlias : InstAlias<"$Vdd32=vaddub($Vu32,$Vv32)", (V6_vaddubh VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vaddubsat_altAlias : InstAlias<"$Vd32=vaddub($Vu32,$Vv32):sat", (V6_vaddubsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vaddubsat_alt_128BAlias : InstAlias<"$Vd32=vaddub($Vu32,$Vv32):sat", (V6_vaddubsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vaddubsat_dv_altAlias : InstAlias<"$Vdd32=vaddub($Vuu32,$Vvv32):sat", (V6_vaddubsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
+def V6_vaddubsat_dv_alt_128BAlias : InstAlias<"$Vdd32=vaddub($Vuu32,$Vvv32):sat", (V6_vaddubsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
+def V6_vadduhsat_altAlias : InstAlias<"$Vd32=vadduh($Vu32,$Vv32):sat", (V6_vadduhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vadduhsat_alt_128BAlias : InstAlias<"$Vd32=vadduh($Vu32,$Vv32):sat", (V6_vadduhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vadduhsat_dv_altAlias : InstAlias<"$Vdd32=vadduh($Vuu32,$Vvv32):sat", (V6_vadduhsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
+def V6_vadduhsat_dv_alt_128BAlias : InstAlias<"$Vdd32=vadduh($Vuu32,$Vvv32):sat", (V6_vadduhsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
+def V6_vadduhw_altAlias : InstAlias<"$Vdd32=vadduh($Vu32,$Vv32)", (V6_vadduhw VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vadduhw_alt_128BAlias : InstAlias<"$Vdd32=vadduh($Vu32,$Vv32)", (V6_vadduhw VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vaddw_altAlias : InstAlias<"$Vd32=vaddw($Vu32,$Vv32)", (V6_vaddw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vaddw_alt_128BAlias : InstAlias<"$Vd32=vaddw($Vu32,$Vv32)", (V6_vaddw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vaddw_dv_altAlias : InstAlias<"$Vdd32=vaddw($Vuu32,$Vvv32)", (V6_vaddw_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
+def V6_vaddw_dv_alt_128BAlias : InstAlias<"$Vdd32=vaddw($Vuu32,$Vvv32)", (V6_vaddw_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
+def V6_vaddwnq_altAlias : InstAlias<"if (!$Qv4.w) $Vx32.w+=$Vu32.w", (V6_vaddwnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vaddwnq_alt_128BAlias : InstAlias<"if (!$Qv4.w) $Vx32.w+=$Vu32.w", (V6_vaddwnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vaddwq_altAlias : InstAlias<"if ($Qv4.w) $Vx32.w+=$Vu32.w", (V6_vaddwq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vaddwq_alt_128BAlias : InstAlias<"if ($Qv4.w) $Vx32.w+=$Vu32.w", (V6_vaddwq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vaddwsat_altAlias : InstAlias<"$Vd32=vaddw($Vu32,$Vv32):sat", (V6_vaddwsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vaddwsat_alt_128BAlias : InstAlias<"$Vd32=vaddw($Vu32,$Vv32):sat", (V6_vaddwsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vaddwsat_dv_altAlias : InstAlias<"$Vdd32=vaddw($Vuu32,$Vvv32):sat", (V6_vaddwsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
+def V6_vaddwsat_dv_alt_128BAlias : InstAlias<"$Vdd32=vaddw($Vuu32,$Vvv32):sat", (V6_vaddwsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
+def V6_vandqrt_acc_altAlias : InstAlias<"$Vx32.ub|=vand($Qu4.ub,$Rt32.ub)", (V6_vandqrt_acc VectorRegs:$Vx32, VecPredRegs:$Qu4, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vandqrt_acc_alt_128BAlias : InstAlias<"$Vx32.ub|=vand($Qu4.ub,$Rt32.ub)", (V6_vandqrt_acc VectorRegs:$Vx32, VecPredRegs:$Qu4, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vandqrt_altAlias : InstAlias<"$Vd32.ub=vand($Qu4.ub,$Rt32.ub)", (V6_vandqrt VectorRegs:$Vd32, VecPredRegs:$Qu4, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vandqrt_alt_128BAlias : InstAlias<"$Vd32.ub=vand($Qu4.ub,$Rt32.ub)", (V6_vandqrt VectorRegs:$Vd32, VecPredRegs:$Qu4, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vandvrt_acc_altAlias : InstAlias<"$Qx4.ub|=vand($Vu32.ub,$Rt32.ub)", (V6_vandvrt_acc VecPredRegs:$Qx4, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vandvrt_acc_alt_128BAlias : InstAlias<"$Qx4.ub|=vand($Vu32.ub,$Rt32.ub)", (V6_vandvrt_acc VecPredRegs:$Qx4, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vandvrt_altAlias : InstAlias<"$Qd4.ub=vand($Vu32.ub,$Rt32.ub)", (V6_vandvrt VecPredRegs:$Qd4, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vandvrt_alt_128BAlias : InstAlias<"$Qd4.ub=vand($Vu32.ub,$Rt32.ub)", (V6_vandvrt VecPredRegs:$Qd4, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vaslh_altAlias : InstAlias<"$Vd32=vaslh($Vu32,$Rt32)", (V6_vaslh VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vaslh_alt_128BAlias : InstAlias<"$Vd32=vaslh($Vu32,$Rt32)", (V6_vaslh VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vaslhv_altAlias : InstAlias<"$Vd32=vaslh($Vu32,$Vv32)", (V6_vaslhv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vaslhv_alt_128BAlias : InstAlias<"$Vd32=vaslh($Vu32,$Vv32)", (V6_vaslhv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vaslw_acc_altAlias : InstAlias<"$Vx32+=vaslw($Vu32,$Rt32)", (V6_vaslw_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vaslw_acc_alt_128BAlias : InstAlias<"$Vx32+=vaslw($Vu32,$Rt32)", (V6_vaslw_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vaslw_altAlias : InstAlias<"$Vd32=vaslw($Vu32,$Rt32)", (V6_vaslw VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vaslw_alt_128BAlias : InstAlias<"$Vd32=vaslw($Vu32,$Rt32)", (V6_vaslw VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vaslwv_altAlias : InstAlias<"$Vd32=vaslw($Vu32,$Vv32)", (V6_vaslwv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vaslwv_alt_128BAlias : InstAlias<"$Vd32=vaslw($Vu32,$Vv32)", (V6_vaslwv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vasrh_altAlias : InstAlias<"$Vd32=vasrh($Vu32,$Rt32)", (V6_vasrh VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vasrh_alt_128BAlias : InstAlias<"$Vd32=vasrh($Vu32,$Rt32)", (V6_vasrh VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vasrhbrndsat_altAlias : InstAlias<"$Vd32=vasrhb($Vu32,$Vv32,$Rt8):rnd:sat", (V6_vasrhbrndsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8)>;
+def V6_vasrhubrndsat_altAlias : InstAlias<"$Vd32=vasrhub($Vu32,$Vv32,$Rt8):rnd:sat", (V6_vasrhubrndsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8)>;
+def V6_vasrhubsat_altAlias : InstAlias<"$Vd32=vasrhub($Vu32,$Vv32,$Rt8):sat", (V6_vasrhubsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8)>;
+def V6_vasrhv_altAlias : InstAlias<"$Vd32=vasrh($Vu32,$Vv32)", (V6_vasrhv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vasrhv_alt_128BAlias : InstAlias<"$Vd32=vasrh($Vu32,$Vv32)", (V6_vasrhv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vasrw_acc_altAlias : InstAlias<"$Vx32+=vasrw($Vu32,$Rt32)", (V6_vasrw_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vasrw_acc_alt_128BAlias : InstAlias<"$Vx32+=vasrw($Vu32,$Rt32)", (V6_vasrw_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vasrw_altAlias : InstAlias<"$Vd32=vasrw($Vu32,$Rt32)", (V6_vasrw VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vasrw_alt_128BAlias : InstAlias<"$Vd32=vasrw($Vu32,$Rt32)", (V6_vasrw VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vasrwh_altAlias : InstAlias<"$Vd32=vasrwh($Vu32,$Vv32,$Rt8)", (V6_vasrwhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8)>;
+def V6_vasrwhrndsat_altAlias : InstAlias<"$Vd32=vasrwh($Vu32,$Vv32,$Rt8):rnd:sat", (V6_vasrwhrndsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8)>;
+def V6_vasrwhsat_altAlias : InstAlias<"$Vd32=vasrwh($Vu32,$Vv32,$Rt8):sat", (V6_vasrwhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8)>;
+def V6_vasrwuhsat_altAlias : InstAlias<"$Vd32=vasrwuh($Vu32,$Vv32,$Rt8):sat", (V6_vasrwuhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8)>;
+def V6_vasrwv_altAlias : InstAlias<"$Vd32=vasrw($Vu32,$Vv32)", (V6_vasrwv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vasrwv_alt_128BAlias : InstAlias<"$Vd32=vasrw($Vu32,$Vv32)", (V6_vasrwv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vavgh_altAlias : InstAlias<"$Vd32=vavgh($Vu32,$Vv32)", (V6_vavgh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vavgh_alt_128BAlias : InstAlias<"$Vd32=vavgh($Vu32,$Vv32)", (V6_vavgh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vavghrnd_altAlias : InstAlias<"$Vd32=vavgh($Vu32,$Vv32):rnd", (V6_vavghrnd VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vavghrnd_alt_128BAlias : InstAlias<"$Vd32=vavgh($Vu32,$Vv32):rnd", (V6_vavghrnd VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vavgub_altAlias : InstAlias<"$Vd32=vavgub($Vu32,$Vv32)", (V6_vavgub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vavgub_alt_128BAlias : InstAlias<"$Vd32=vavgub($Vu32,$Vv32)", (V6_vavgub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vavgubrnd_altAlias : InstAlias<"$Vd32=vavgub($Vu32,$Vv32):rnd", (V6_vavgubrnd VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vavgubrnd_alt_128BAlias : InstAlias<"$Vd32=vavgub($Vu32,$Vv32):rnd", (V6_vavgubrnd VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vavguh_altAlias : InstAlias<"$Vd32=vavguh($Vu32,$Vv32)", (V6_vavguh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vavguh_alt_128BAlias : InstAlias<"$Vd32=vavguh($Vu32,$Vv32)", (V6_vavguh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vavguhrnd_altAlias : InstAlias<"$Vd32=vavguh($Vu32,$Vv32):rnd", (V6_vavguhrnd VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vavguhrnd_alt_128BAlias : InstAlias<"$Vd32=vavguh($Vu32,$Vv32):rnd", (V6_vavguhrnd VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vavgw_altAlias : InstAlias<"$Vd32=vavgw($Vu32,$Vv32)", (V6_vavgw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vavgw_alt_128BAlias : InstAlias<"$Vd32=vavgw($Vu32,$Vv32)", (V6_vavgw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vavgwrnd_altAlias : InstAlias<"$Vd32=vavgw($Vu32,$Vv32):rnd", (V6_vavgwrnd VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vavgwrnd_alt_128BAlias : InstAlias<"$Vd32=vavgw($Vu32,$Vv32):rnd", (V6_vavgwrnd VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vcl0h_altAlias : InstAlias<"$Vd32=vcl0h($Vu32)", (V6_vcl0h VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vcl0h_alt_128BAlias : InstAlias<"$Vd32=vcl0h($Vu32)", (V6_vcl0h VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vcl0w_altAlias : InstAlias<"$Vd32=vcl0w($Vu32)", (V6_vcl0w VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vcl0w_alt_128BAlias : InstAlias<"$Vd32=vcl0w($Vu32)", (V6_vcl0w VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vd0Alias : InstAlias<"$Vd32=#0", (V6_vxor VectorRegs:$Vd32, VectorRegs:$Vd32, VectorRegs:$Vd32)>, Requires<[UseHVX]>;
+def V6_vd0_128BAlias : InstAlias<"$Vd32=#0", (V6_vxor VectorRegs:$Vd32, VectorRegs:$Vd32, VectorRegs:$Vd32)>, Requires<[UseHVX]>;
+def V6_vdd0Alias : InstAlias<"$Vdd32=#0", (V6_vsubw_dv VecDblRegs:$Vdd32, W15, W15)>, Requires<[UseHVX]>;
+def V6_vdd0_128BAlias : InstAlias<"$Vdd32=#0", (V6_vsubw_dv VecDblRegs:$Vdd32, W15, W15)>, Requires<[UseHVX]>;
+def V6_vdealb4w_altAlias : InstAlias<"$Vd32=vdealb4w($Vu32,$Vv32)", (V6_vdealb4w VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vdealb4w_alt_128BAlias : InstAlias<"$Vd32=vdealb4w($Vu32,$Vv32)", (V6_vdealb4w VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vdealb_altAlias : InstAlias<"$Vd32=vdealb($Vu32)", (V6_vdealb VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vdealb_alt_128BAlias : InstAlias<"$Vd32=vdealb($Vu32)", (V6_vdealb VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vdealh_altAlias : InstAlias<"$Vd32=vdealh($Vu32)", (V6_vdealh VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vdealh_alt_128BAlias : InstAlias<"$Vd32=vdealh($Vu32)", (V6_vdealh VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vdmpybus_acc_altAlias : InstAlias<"$Vx32+=vdmpybus($Vu32,$Rt32)", (V6_vdmpybus_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vdmpybus_acc_alt_128BAlias : InstAlias<"$Vx32+=vdmpybus($Vu32,$Rt32)", (V6_vdmpybus_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vdmpybus_altAlias : InstAlias<"$Vd32=vdmpybus($Vu32,$Rt32)", (V6_vdmpybus VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vdmpybus_alt_128BAlias : InstAlias<"$Vd32=vdmpybus($Vu32,$Rt32)", (V6_vdmpybus VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vdmpybus_dv_acc_altAlias : InstAlias<"$Vxx32+=vdmpybus($Vuu32,$Rt32)", (V6_vdmpybus_dv_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vdmpybus_dv_acc_alt_128BAlias : InstAlias<"$Vxx32+=vdmpybus($Vuu32,$Rt32)", (V6_vdmpybus_dv_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vdmpybus_dv_altAlias : InstAlias<"$Vdd32=vdmpybus($Vuu32,$Rt32)", (V6_vdmpybus_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vdmpybus_dv_alt_128BAlias : InstAlias<"$Vdd32=vdmpybus($Vuu32,$Rt32)", (V6_vdmpybus_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vdmpyhb_acc_altAlias : InstAlias<"$Vx32+=vdmpyhb($Vu32,$Rt32)", (V6_vdmpyhb_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vdmpyhb_acc_alt_128BAlias : InstAlias<"$Vx32+=vdmpyhb($Vu32,$Rt32)", (V6_vdmpyhb_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vdmpyhb_altAlias : InstAlias<"$Vd32=vdmpyhb($Vu32,$Rt32)", (V6_vdmpyhb VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vdmpyhb_alt_128BAlias : InstAlias<"$Vd32=vdmpyhb($Vu32,$Rt32)", (V6_vdmpyhb VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vdmpyhb_dv_acc_altAlias : InstAlias<"$Vxx32+=vdmpyhb($Vuu32,$Rt32)", (V6_vdmpyhb_dv_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vdmpyhb_dv_acc_alt_128BAlias : InstAlias<"$Vxx32+=vdmpyhb($Vuu32,$Rt32)", (V6_vdmpyhb_dv_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vdmpyhb_dv_altAlias : InstAlias<"$Vdd32=vdmpyhb($Vuu32,$Rt32)", (V6_vdmpyhb_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vdmpyhb_dv_alt_128BAlias : InstAlias<"$Vdd32=vdmpyhb($Vuu32,$Rt32)", (V6_vdmpyhb_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vdmpyhisat_acc_altAlias : InstAlias<"$Vx32+=vdmpyh($Vuu32,$Rt32):sat", (V6_vdmpyhisat_acc VectorRegs:$Vx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vdmpyhisat_acc_alt_128BAlias : InstAlias<"$Vx32+=vdmpyh($Vuu32,$Rt32):sat", (V6_vdmpyhisat_acc VectorRegs:$Vx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vdmpyhisat_altAlias : InstAlias<"$Vd32=vdmpyh($Vuu32,$Rt32):sat", (V6_vdmpyhisat VectorRegs:$Vd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vdmpyhisat_alt_128BAlias : InstAlias<"$Vd32=vdmpyh($Vuu32,$Rt32):sat", (V6_vdmpyhisat VectorRegs:$Vd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vdmpyhsat_acc_altAlias : InstAlias<"$Vx32+=vdmpyh($Vu32,$Rt32):sat", (V6_vdmpyhsat_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vdmpyhsat_acc_alt_128BAlias : InstAlias<"$Vx32+=vdmpyh($Vu32,$Rt32):sat", (V6_vdmpyhsat_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vdmpyhsat_altAlias : InstAlias<"$Vd32=vdmpyh($Vu32,$Rt32):sat", (V6_vdmpyhsat VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vdmpyhsat_alt_128BAlias : InstAlias<"$Vd32=vdmpyh($Vu32,$Rt32):sat", (V6_vdmpyhsat VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vdmpyhsuisat_acc_altAlias : InstAlias<"$Vx32+=vdmpyhsu($Vuu32,$Rt32,#1):sat", (V6_vdmpyhsuisat_acc VectorRegs:$Vx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vdmpyhsuisat_acc_alt_128BAlias : InstAlias<"$Vx32+=vdmpyhsu($Vuu32,$Rt32,#1):sat", (V6_vdmpyhsuisat_acc VectorRegs:$Vx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vdmpyhsuisat_altAlias : InstAlias<"$Vd32=vdmpyhsu($Vuu32,$Rt32,#1):sat", (V6_vdmpyhsuisat VectorRegs:$Vd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vdmpyhsuisat_alt_128BAlias : InstAlias<"$Vd32=vdmpyhsu($Vuu32,$Rt32,#1):sat", (V6_vdmpyhsuisat VectorRegs:$Vd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vdmpyhsusat_acc_altAlias : InstAlias<"$Vx32+=vdmpyhsu($Vu32,$Rt32):sat", (V6_vdmpyhsusat_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vdmpyhsusat_acc_alt_128BAlias : InstAlias<"$Vx32+=vdmpyhsu($Vu32,$Rt32):sat", (V6_vdmpyhsusat_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vdmpyhsusat_altAlias : InstAlias<"$Vd32=vdmpyhsu($Vu32,$Rt32):sat", (V6_vdmpyhsusat VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vdmpyhsusat_alt_128BAlias : InstAlias<"$Vd32=vdmpyhsu($Vu32,$Rt32):sat", (V6_vdmpyhsusat VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vdmpyhvsat_acc_altAlias : InstAlias<"$Vx32+=vdmpyh($Vu32,$Vv32):sat", (V6_vdmpyhvsat_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vdmpyhvsat_acc_alt_128BAlias : InstAlias<"$Vx32+=vdmpyh($Vu32,$Vv32):sat", (V6_vdmpyhvsat_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vdmpyhvsat_altAlias : InstAlias<"$Vd32=vdmpyh($Vu32,$Vv32):sat", (V6_vdmpyhvsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vdmpyhvsat_alt_128BAlias : InstAlias<"$Vd32=vdmpyh($Vu32,$Vv32):sat", (V6_vdmpyhvsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vdsaduh_acc_altAlias : InstAlias<"$Vxx32+=vdsaduh($Vuu32,$Rt32)", (V6_vdsaduh_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vdsaduh_acc_alt_128BAlias : InstAlias<"$Vxx32+=vdsaduh($Vuu32,$Rt32)", (V6_vdsaduh_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vdsaduh_altAlias : InstAlias<"$Vdd32=vdsaduh($Vuu32,$Rt32)", (V6_vdsaduh VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vdsaduh_alt_128BAlias : InstAlias<"$Vdd32=vdsaduh($Vuu32,$Rt32)", (V6_vdsaduh VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vlsrh_altAlias : InstAlias<"$Vd32=vlsrh($Vu32,$Rt32)", (V6_vlsrh VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vlsrh_alt_128BAlias : InstAlias<"$Vd32=vlsrh($Vu32,$Rt32)", (V6_vlsrh VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vlsrhv_altAlias : InstAlias<"$Vd32=vlsrh($Vu32,$Vv32)", (V6_vlsrhv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vlsrhv_alt_128BAlias : InstAlias<"$Vd32=vlsrh($Vu32,$Vv32)", (V6_vlsrhv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vlsrw_altAlias : InstAlias<"$Vd32=vlsrw($Vu32,$Rt32)", (V6_vlsrw VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vlsrw_alt_128BAlias : InstAlias<"$Vd32=vlsrw($Vu32,$Rt32)", (V6_vlsrw VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vlsrwv_altAlias : InstAlias<"$Vd32=vlsrw($Vu32,$Vv32)", (V6_vlsrwv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vlsrwv_alt_128BAlias : InstAlias<"$Vd32=vlsrw($Vu32,$Vv32)", (V6_vlsrwv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmaxh_altAlias : InstAlias<"$Vd32=vmaxh($Vu32,$Vv32)", (V6_vmaxh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmaxh_alt_128BAlias : InstAlias<"$Vd32=vmaxh($Vu32,$Vv32)", (V6_vmaxh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmaxub_altAlias : InstAlias<"$Vd32=vmaxub($Vu32,$Vv32)", (V6_vmaxub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmaxub_alt_128BAlias : InstAlias<"$Vd32=vmaxub($Vu32,$Vv32)", (V6_vmaxub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmaxuh_altAlias : InstAlias<"$Vd32=vmaxuh($Vu32,$Vv32)", (V6_vmaxuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmaxuh_alt_128BAlias : InstAlias<"$Vd32=vmaxuh($Vu32,$Vv32)", (V6_vmaxuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmaxw_altAlias : InstAlias<"$Vd32=vmaxw($Vu32,$Vv32)", (V6_vmaxw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmaxw_alt_128BAlias : InstAlias<"$Vd32=vmaxw($Vu32,$Vv32)", (V6_vmaxw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vminh_altAlias : InstAlias<"$Vd32=vminh($Vu32,$Vv32)", (V6_vminh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vminh_alt_128BAlias : InstAlias<"$Vd32=vminh($Vu32,$Vv32)", (V6_vminh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vminub_altAlias : InstAlias<"$Vd32=vminub($Vu32,$Vv32)", (V6_vminub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vminub_alt_128BAlias : InstAlias<"$Vd32=vminub($Vu32,$Vv32)", (V6_vminub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vminuh_altAlias : InstAlias<"$Vd32=vminuh($Vu32,$Vv32)", (V6_vminuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vminuh_alt_128BAlias : InstAlias<"$Vd32=vminuh($Vu32,$Vv32)", (V6_vminuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vminw_altAlias : InstAlias<"$Vd32=vminw($Vu32,$Vv32)", (V6_vminw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vminw_alt_128BAlias : InstAlias<"$Vd32=vminw($Vu32,$Vv32)", (V6_vminw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpabus_acc_altAlias : InstAlias<"$Vxx32+=vmpabus($Vuu32,$Rt32)", (V6_vmpabus_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpabus_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpabus($Vuu32,$Rt32)", (V6_vmpabus_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpabus_altAlias : InstAlias<"$Vdd32=vmpabus($Vuu32,$Rt32)", (V6_vmpabus VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpabus_alt_128BAlias : InstAlias<"$Vdd32=vmpabus($Vuu32,$Rt32)", (V6_vmpabus VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpabusv_altAlias : InstAlias<"$Vdd32=vmpabus($Vuu32,$Vvv32)", (V6_vmpabusv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
+def V6_vmpabusv_alt_128BAlias : InstAlias<"$Vdd32=vmpabus($Vuu32,$Vvv32)", (V6_vmpabusv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
+def V6_vmpabuuv_altAlias : InstAlias<"$Vdd32=vmpabuu($Vuu32,$Vvv32)", (V6_vmpabuuv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
+def V6_vmpabuuv_alt_128BAlias : InstAlias<"$Vdd32=vmpabuu($Vuu32,$Vvv32)", (V6_vmpabuuv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
+def V6_vmpahb_acc_altAlias : InstAlias<"$Vxx32+=vmpahb($Vuu32,$Rt32)", (V6_vmpahb_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpahb_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpahb($Vuu32,$Rt32)", (V6_vmpahb_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpahb_altAlias : InstAlias<"$Vdd32=vmpahb($Vuu32,$Rt32)", (V6_vmpahb VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpahb_alt_128BAlias : InstAlias<"$Vdd32=vmpahb($Vuu32,$Rt32)", (V6_vmpahb VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpybus_acc_altAlias : InstAlias<"$Vxx32+=vmpybus($Vu32,$Rt32)", (V6_vmpybus_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpybus_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpybus($Vu32,$Rt32)", (V6_vmpybus_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpybus_altAlias : InstAlias<"$Vdd32=vmpybus($Vu32,$Rt32)", (V6_vmpybus VecDblRegs:$Vdd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpybus_alt_128BAlias : InstAlias<"$Vdd32=vmpybus($Vu32,$Rt32)", (V6_vmpybus VecDblRegs:$Vdd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpybusv_acc_altAlias : InstAlias<"$Vxx32+=vmpybus($Vu32,$Vv32)", (V6_vmpybusv_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpybusv_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpybus($Vu32,$Vv32)", (V6_vmpybusv_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpybusv_altAlias : InstAlias<"$Vdd32=vmpybus($Vu32,$Vv32)", (V6_vmpybusv VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpybusv_alt_128BAlias : InstAlias<"$Vdd32=vmpybus($Vu32,$Vv32)", (V6_vmpybusv VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpybv_acc_altAlias : InstAlias<"$Vxx32+=vmpyb($Vu32,$Vv32)", (V6_vmpybv_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpybv_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpyb($Vu32,$Vv32)", (V6_vmpybv_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpybv_altAlias : InstAlias<"$Vdd32=vmpyb($Vu32,$Vv32)", (V6_vmpybv VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpybv_alt_128BAlias : InstAlias<"$Vdd32=vmpyb($Vu32,$Vv32)", (V6_vmpybv VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpyewuh_altAlias : InstAlias<"$Vd32=vmpyewuh($Vu32,$Vv32)", (V6_vmpyewuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpyewuh_alt_128BAlias : InstAlias<"$Vd32=vmpyewuh($Vu32,$Vv32)", (V6_vmpyewuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpyh_altAlias : InstAlias<"$Vdd32=vmpyh($Vu32,$Rt32)", (V6_vmpyh VecDblRegs:$Vdd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpyh_alt_128BAlias : InstAlias<"$Vdd32=vmpyh($Vu32,$Rt32)", (V6_vmpyh VecDblRegs:$Vdd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpyhsat_acc_altAlias : InstAlias<"$Vxx32+=vmpyh($Vu32,$Rt32):sat", (V6_vmpyhsat_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpyhsat_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpyh($Vu32,$Rt32):sat", (V6_vmpyhsat_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpyhsrs_altAlias : InstAlias<"$Vd32=vmpyh($Vu32,$Rt32):<<1:rnd:sat", (V6_vmpyhsrs VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpyhsrs_alt_128BAlias : InstAlias<"$Vd32=vmpyh($Vu32,$Rt32):<<1:rnd:sat", (V6_vmpyhsrs VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpyhss_altAlias : InstAlias<"$Vd32=vmpyh($Vu32,$Rt32):<<1:sat", (V6_vmpyhss VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpyhss_alt_128BAlias : InstAlias<"$Vd32=vmpyh($Vu32,$Rt32):<<1:sat", (V6_vmpyhss VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpyhus_acc_altAlias : InstAlias<"$Vxx32+=vmpyhus($Vu32,$Vv32)", (V6_vmpyhus_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpyhus_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpyhus($Vu32,$Vv32)", (V6_vmpyhus_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpyhus_altAlias : InstAlias<"$Vdd32=vmpyhus($Vu32,$Vv32)", (V6_vmpyhus VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpyhus_alt_128BAlias : InstAlias<"$Vdd32=vmpyhus($Vu32,$Vv32)", (V6_vmpyhus VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpyhv_acc_altAlias : InstAlias<"$Vxx32+=vmpyh($Vu32,$Vv32)", (V6_vmpyhv_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpyhv_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpyh($Vu32,$Vv32)", (V6_vmpyhv_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpyhv_altAlias : InstAlias<"$Vdd32=vmpyh($Vu32,$Vv32)", (V6_vmpyhv VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpyhv_alt_128BAlias : InstAlias<"$Vdd32=vmpyh($Vu32,$Vv32)", (V6_vmpyhv VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpyhvsrs_altAlias : InstAlias<"$Vd32=vmpyh($Vu32,$Vv32):<<1:rnd:sat", (V6_vmpyhvsrs VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpyhvsrs_alt_128BAlias : InstAlias<"$Vd32=vmpyh($Vu32,$Vv32):<<1:rnd:sat", (V6_vmpyhvsrs VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpyiewh_acc_altAlias : InstAlias<"$Vx32+=vmpyiewh($Vu32,$Vv32)", (V6_vmpyiewh_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpyiewh_acc_alt_128BAlias : InstAlias<"$Vx32+=vmpyiewh($Vu32,$Vv32)", (V6_vmpyiewh_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpyiewuh_acc_altAlias : InstAlias<"$Vx32+=vmpyiewuh($Vu32,$Vv32)", (V6_vmpyiewuh_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpyiewuh_acc_alt_128BAlias : InstAlias<"$Vx32+=vmpyiewuh($Vu32,$Vv32)", (V6_vmpyiewuh_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpyiewuh_altAlias : InstAlias<"$Vd32=vmpyiewuh($Vu32,$Vv32)", (V6_vmpyiewuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpyiewuh_alt_128BAlias : InstAlias<"$Vd32=vmpyiewuh($Vu32,$Vv32)", (V6_vmpyiewuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpyih_acc_altAlias : InstAlias<"$Vx32+=vmpyih($Vu32,$Vv32)", (V6_vmpyih_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpyih_acc_alt_128BAlias : InstAlias<"$Vx32+=vmpyih($Vu32,$Vv32)", (V6_vmpyih_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpyih_altAlias : InstAlias<"$Vd32=vmpyih($Vu32,$Vv32)", (V6_vmpyih VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpyih_alt_128BAlias : InstAlias<"$Vd32=vmpyih($Vu32,$Vv32)", (V6_vmpyih VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpyihb_acc_altAlias : InstAlias<"$Vx32+=vmpyihb($Vu32,$Rt32)", (V6_vmpyihb_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpyihb_acc_alt_128BAlias : InstAlias<"$Vx32+=vmpyihb($Vu32,$Rt32)", (V6_vmpyihb_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpyihb_altAlias : InstAlias<"$Vd32=vmpyihb($Vu32,$Rt32)", (V6_vmpyihb VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpyihb_alt_128BAlias : InstAlias<"$Vd32=vmpyihb($Vu32,$Rt32)", (V6_vmpyihb VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpyiowh_altAlias : InstAlias<"$Vd32=vmpyiowh($Vu32,$Vv32)", (V6_vmpyiowh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpyiowh_alt_128BAlias : InstAlias<"$Vd32=vmpyiowh($Vu32,$Vv32)", (V6_vmpyiowh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpyiwb_acc_altAlias : InstAlias<"$Vx32+=vmpyiwb($Vu32,$Rt32)", (V6_vmpyiwb_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpyiwb_acc_alt_128BAlias : InstAlias<"$Vx32+=vmpyiwb($Vu32,$Rt32)", (V6_vmpyiwb_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpyiwb_altAlias : InstAlias<"$Vd32=vmpyiwb($Vu32,$Rt32)", (V6_vmpyiwb VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpyiwb_alt_128BAlias : InstAlias<"$Vd32=vmpyiwb($Vu32,$Rt32)", (V6_vmpyiwb VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpyiwh_acc_altAlias : InstAlias<"$Vx32+=vmpyiwh($Vu32,$Rt32)", (V6_vmpyiwh_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpyiwh_acc_alt_128BAlias : InstAlias<"$Vx32+=vmpyiwh($Vu32,$Rt32)", (V6_vmpyiwh_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpyiwh_altAlias : InstAlias<"$Vd32=vmpyiwh($Vu32,$Rt32)", (V6_vmpyiwh VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpyiwh_alt_128BAlias : InstAlias<"$Vd32=vmpyiwh($Vu32,$Rt32)", (V6_vmpyiwh VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpyowh_altAlias : InstAlias<"$Vd32=vmpyowh($Vu32,$Vv32):<<1:sat", (V6_vmpyowh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpyowh_alt_128BAlias : InstAlias<"$Vd32=vmpyowh($Vu32,$Vv32):<<1:sat", (V6_vmpyowh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpyowh_rnd_altAlias : InstAlias<"$Vd32=vmpyowh($Vu32,$Vv32):<<1:rnd:sat", (V6_vmpyowh_rnd VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpyowh_rnd_alt_128BAlias : InstAlias<"$Vd32=vmpyowh($Vu32,$Vv32):<<1:rnd:sat", (V6_vmpyowh_rnd VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpyub_acc_altAlias : InstAlias<"$Vxx32+=vmpyub($Vu32,$Rt32)", (V6_vmpyub_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpyub_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpyub($Vu32,$Rt32)", (V6_vmpyub_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpyub_altAlias : InstAlias<"$Vdd32=vmpyub($Vu32,$Rt32)", (V6_vmpyub VecDblRegs:$Vdd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpyub_alt_128BAlias : InstAlias<"$Vdd32=vmpyub($Vu32,$Rt32)", (V6_vmpyub VecDblRegs:$Vdd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpyubv_acc_altAlias : InstAlias<"$Vxx32+=vmpyub($Vu32,$Vv32)", (V6_vmpyubv_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpyubv_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpyub($Vu32,$Vv32)", (V6_vmpyubv_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpyubv_altAlias : InstAlias<"$Vdd32=vmpyub($Vu32,$Vv32)", (V6_vmpyubv VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpyubv_alt_128BAlias : InstAlias<"$Vdd32=vmpyub($Vu32,$Vv32)", (V6_vmpyubv VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpyuh_acc_altAlias : InstAlias<"$Vxx32+=vmpyuh($Vu32,$Rt32)", (V6_vmpyuh_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpyuh_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpyuh($Vu32,$Rt32)", (V6_vmpyuh_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpyuh_altAlias : InstAlias<"$Vdd32=vmpyuh($Vu32,$Rt32)", (V6_vmpyuh VecDblRegs:$Vdd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpyuh_alt_128BAlias : InstAlias<"$Vdd32=vmpyuh($Vu32,$Rt32)", (V6_vmpyuh VecDblRegs:$Vdd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vmpyuhv_acc_altAlias : InstAlias<"$Vxx32+=vmpyuh($Vu32,$Vv32)", (V6_vmpyuhv_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpyuhv_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpyuh($Vu32,$Vv32)", (V6_vmpyuhv_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpyuhv_altAlias : InstAlias<"$Vdd32=vmpyuh($Vu32,$Vv32)", (V6_vmpyuhv VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vmpyuhv_alt_128BAlias : InstAlias<"$Vdd32=vmpyuh($Vu32,$Vv32)", (V6_vmpyuhv VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vnavgh_altAlias : InstAlias<"$Vd32=vnavgh($Vu32,$Vv32)", (V6_vnavgh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vnavgh_alt_128BAlias : InstAlias<"$Vd32=vnavgh($Vu32,$Vv32)", (V6_vnavgh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vnavgub_altAlias : InstAlias<"$Vd32=vnavgub($Vu32,$Vv32)", (V6_vnavgub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vnavgub_alt_128BAlias : InstAlias<"$Vd32=vnavgub($Vu32,$Vv32)", (V6_vnavgub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vnavgw_altAlias : InstAlias<"$Vd32=vnavgw($Vu32,$Vv32)", (V6_vnavgw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vnavgw_alt_128BAlias : InstAlias<"$Vd32=vnavgw($Vu32,$Vv32)", (V6_vnavgw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vnormamth_altAlias : InstAlias<"$Vd32=vnormamth($Vu32)", (V6_vnormamth VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vnormamth_alt_128BAlias : InstAlias<"$Vd32=vnormamth($Vu32)", (V6_vnormamth VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vnormamtw_altAlias : InstAlias<"$Vd32=vnormamtw($Vu32)", (V6_vnormamtw VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vnormamtw_alt_128BAlias : InstAlias<"$Vd32=vnormamtw($Vu32)", (V6_vnormamtw VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vpackeb_altAlias : InstAlias<"$Vd32=vpackeb($Vu32,$Vv32)", (V6_vpackeb VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vpackeb_alt_128BAlias : InstAlias<"$Vd32=vpackeb($Vu32,$Vv32)", (V6_vpackeb VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vpackeh_altAlias : InstAlias<"$Vd32=vpackeh($Vu32,$Vv32)", (V6_vpackeh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vpackeh_alt_128BAlias : InstAlias<"$Vd32=vpackeh($Vu32,$Vv32)", (V6_vpackeh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vpackhb_sat_altAlias : InstAlias<"$Vd32=vpackhb($Vu32,$Vv32):sat", (V6_vpackhb_sat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vpackhb_sat_alt_128BAlias : InstAlias<"$Vd32=vpackhb($Vu32,$Vv32):sat", (V6_vpackhb_sat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vpackhub_sat_altAlias : InstAlias<"$Vd32=vpackhub($Vu32,$Vv32):sat", (V6_vpackhub_sat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vpackhub_sat_alt_128BAlias : InstAlias<"$Vd32=vpackhub($Vu32,$Vv32):sat", (V6_vpackhub_sat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vpackob_altAlias : InstAlias<"$Vd32=vpackob($Vu32,$Vv32)", (V6_vpackob VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vpackob_alt_128BAlias : InstAlias<"$Vd32=vpackob($Vu32,$Vv32)", (V6_vpackob VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vpackoh_altAlias : InstAlias<"$Vd32=vpackoh($Vu32,$Vv32)", (V6_vpackoh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vpackoh_alt_128BAlias : InstAlias<"$Vd32=vpackoh($Vu32,$Vv32)", (V6_vpackoh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vpackwh_sat_altAlias : InstAlias<"$Vd32=vpackwh($Vu32,$Vv32):sat", (V6_vpackwh_sat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vpackwh_sat_alt_128BAlias : InstAlias<"$Vd32=vpackwh($Vu32,$Vv32):sat", (V6_vpackwh_sat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vpackwuh_sat_altAlias : InstAlias<"$Vd32=vpackwuh($Vu32,$Vv32):sat", (V6_vpackwuh_sat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vpackwuh_sat_alt_128BAlias : InstAlias<"$Vd32=vpackwuh($Vu32,$Vv32):sat", (V6_vpackwuh_sat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vpopcounth_altAlias : InstAlias<"$Vd32=vpopcounth($Vu32)", (V6_vpopcounth VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vpopcounth_alt_128BAlias : InstAlias<"$Vd32=vpopcounth($Vu32)", (V6_vpopcounth VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vrmpybus_acc_altAlias : InstAlias<"$Vx32+=vrmpybus($Vu32,$Rt32)", (V6_vrmpybus_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vrmpybus_acc_alt_128BAlias : InstAlias<"$Vx32+=vrmpybus($Vu32,$Rt32)", (V6_vrmpybus_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vrmpybus_altAlias : InstAlias<"$Vd32=vrmpybus($Vu32,$Rt32)", (V6_vrmpybus VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vrmpybus_alt_128BAlias : InstAlias<"$Vd32=vrmpybus($Vu32,$Rt32)", (V6_vrmpybus VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vrmpybusi_acc_altAlias : InstAlias<"$Vxx32+=vrmpybus($Vuu32,$Rt32,#$Ii)", (V6_vrmpybusi_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>;
+def V6_vrmpybusi_acc_alt_128BAlias : InstAlias<"$Vxx32+=vrmpybus($Vuu32,$Rt32,#$Ii)", (V6_vrmpybusi_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>;
+def V6_vrmpybusi_altAlias : InstAlias<"$Vdd32=vrmpybus($Vuu32,$Rt32,#$Ii)", (V6_vrmpybusi VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>;
+def V6_vrmpybusi_alt_128BAlias : InstAlias<"$Vdd32=vrmpybus($Vuu32,$Rt32,#$Ii)", (V6_vrmpybusi VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>;
+def V6_vrmpybusv_acc_altAlias : InstAlias<"$Vx32+=vrmpybus($Vu32,$Vv32)", (V6_vrmpybusv_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vrmpybusv_acc_alt_128BAlias : InstAlias<"$Vx32+=vrmpybus($Vu32,$Vv32)", (V6_vrmpybusv_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vrmpybusv_altAlias : InstAlias<"$Vd32=vrmpybus($Vu32,$Vv32)", (V6_vrmpybusv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vrmpybusv_alt_128BAlias : InstAlias<"$Vd32=vrmpybus($Vu32,$Vv32)", (V6_vrmpybusv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vrmpybv_acc_altAlias : InstAlias<"$Vx32+=vrmpyb($Vu32,$Vv32)", (V6_vrmpybv_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vrmpybv_acc_alt_128BAlias : InstAlias<"$Vx32+=vrmpyb($Vu32,$Vv32)", (V6_vrmpybv_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vrmpybv_altAlias : InstAlias<"$Vd32=vrmpyb($Vu32,$Vv32)", (V6_vrmpybv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vrmpybv_alt_128BAlias : InstAlias<"$Vd32=vrmpyb($Vu32,$Vv32)", (V6_vrmpybv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vrmpyub_acc_altAlias : InstAlias<"$Vx32+=vrmpyub($Vu32,$Rt32)", (V6_vrmpyub_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vrmpyub_acc_alt_128BAlias : InstAlias<"$Vx32+=vrmpyub($Vu32,$Rt32)", (V6_vrmpyub_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vrmpyub_altAlias : InstAlias<"$Vd32=vrmpyub($Vu32,$Rt32)", (V6_vrmpyub VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vrmpyub_alt_128BAlias : InstAlias<"$Vd32=vrmpyub($Vu32,$Rt32)", (V6_vrmpyub VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vrmpyubi_acc_altAlias : InstAlias<"$Vxx32+=vrmpyub($Vuu32,$Rt32,#$Ii)", (V6_vrmpyubi_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>;
+def V6_vrmpyubi_acc_alt_128BAlias : InstAlias<"$Vxx32+=vrmpyub($Vuu32,$Rt32,#$Ii)", (V6_vrmpyubi_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>;
+def V6_vrmpyubi_altAlias : InstAlias<"$Vdd32=vrmpyub($Vuu32,$Rt32,#$Ii)", (V6_vrmpyubi VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>;
+def V6_vrmpyubi_alt_128BAlias : InstAlias<"$Vdd32=vrmpyub($Vuu32,$Rt32,#$Ii)", (V6_vrmpyubi VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>;
+def V6_vrmpyubv_acc_altAlias : InstAlias<"$Vx32+=vrmpyub($Vu32,$Vv32)", (V6_vrmpyubv_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vrmpyubv_acc_alt_128BAlias : InstAlias<"$Vx32+=vrmpyub($Vu32,$Vv32)", (V6_vrmpyubv_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vrmpyubv_altAlias : InstAlias<"$Vd32=vrmpyub($Vu32,$Vv32)", (V6_vrmpyubv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vrmpyubv_alt_128BAlias : InstAlias<"$Vd32=vrmpyub($Vu32,$Vv32)", (V6_vrmpyubv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vroundhb_altAlias : InstAlias<"$Vd32=vroundhb($Vu32,$Vv32):sat", (V6_vroundhb VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vroundhb_alt_128BAlias : InstAlias<"$Vd32=vroundhb($Vu32,$Vv32):sat", (V6_vroundhb VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vroundhub_altAlias : InstAlias<"$Vd32=vroundhub($Vu32,$Vv32):sat", (V6_vroundhub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vroundhub_alt_128BAlias : InstAlias<"$Vd32=vroundhub($Vu32,$Vv32):sat", (V6_vroundhub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vroundwh_altAlias : InstAlias<"$Vd32=vroundwh($Vu32,$Vv32):sat", (V6_vroundwh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vroundwh_alt_128BAlias : InstAlias<"$Vd32=vroundwh($Vu32,$Vv32):sat", (V6_vroundwh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vroundwuh_altAlias : InstAlias<"$Vd32=vroundwuh($Vu32,$Vv32):sat", (V6_vroundwuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vroundwuh_alt_128BAlias : InstAlias<"$Vd32=vroundwuh($Vu32,$Vv32):sat", (V6_vroundwuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vrsadubi_acc_altAlias : InstAlias<"$Vxx32+=vrsadub($Vuu32,$Rt32,#$Ii)", (V6_vrsadubi_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>;
+def V6_vrsadubi_acc_alt_128BAlias : InstAlias<"$Vxx32+=vrsadub($Vuu32,$Rt32,#$Ii)", (V6_vrsadubi_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>;
+def V6_vrsadubi_altAlias : InstAlias<"$Vdd32=vrsadub($Vuu32,$Rt32,#$Ii)", (V6_vrsadubi VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>;
+def V6_vrsadubi_alt_128BAlias : InstAlias<"$Vdd32=vrsadub($Vuu32,$Rt32,#$Ii)", (V6_vrsadubi VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>;
+def V6_vsathub_altAlias : InstAlias<"$Vd32=vsathub($Vu32,$Vv32)", (V6_vsathub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vsathub_alt_128BAlias : InstAlias<"$Vd32=vsathub($Vu32,$Vv32)", (V6_vsathub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vsatwh_altAlias : InstAlias<"$Vd32=vsatwh($Vu32,$Vv32)", (V6_vsatwh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vsatwh_alt_128BAlias : InstAlias<"$Vd32=vsatwh($Vu32,$Vv32)", (V6_vsatwh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vsb_altAlias : InstAlias<"$Vdd32=vsxtb($Vu32)", (V6_vsb VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vsb_alt_128BAlias : InstAlias<"$Vdd32=vsxtb($Vu32)", (V6_vsb VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vsh_altAlias : InstAlias<"$Vdd32=vsxth($Vu32)", (V6_vsh VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vsh_alt_128BAlias : InstAlias<"$Vdd32=vsxth($Vu32)", (V6_vsh VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vshufeh_altAlias : InstAlias<"$Vd32=vshuffeh($Vu32,$Vv32)", (V6_vshufeh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vshufeh_alt_128BAlias : InstAlias<"$Vd32=vshuffeh($Vu32,$Vv32)", (V6_vshufeh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vshuffb_altAlias : InstAlias<"$Vd32=vshuffb($Vu32)", (V6_vshuffb VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vshuffb_alt_128BAlias : InstAlias<"$Vd32=vshuffb($Vu32)", (V6_vshuffb VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vshuffeb_altAlias : InstAlias<"$Vd32=vshuffeb($Vu32,$Vv32)", (V6_vshuffeb VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vshuffeb_alt_128BAlias : InstAlias<"$Vd32=vshuffeb($Vu32,$Vv32)", (V6_vshuffeb VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vshuffh_altAlias : InstAlias<"$Vd32=vshuffh($Vu32)", (V6_vshuffh VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vshuffh_alt_128BAlias : InstAlias<"$Vd32=vshuffh($Vu32)", (V6_vshuffh VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vshuffob_altAlias : InstAlias<"$Vd32=vshuffob($Vu32,$Vv32)", (V6_vshuffob VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vshuffob_alt_128BAlias : InstAlias<"$Vd32=vshuffob($Vu32,$Vv32)", (V6_vshuffob VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vshufoeb_altAlias : InstAlias<"$Vdd32=vshuffoeb($Vu32,$Vv32)", (V6_vshufoeb VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vshufoeb_alt_128BAlias : InstAlias<"$Vdd32=vshuffoeb($Vu32,$Vv32)", (V6_vshufoeb VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vshufoeh_altAlias : InstAlias<"$Vdd32=vshuffoeh($Vu32,$Vv32)", (V6_vshufoeh VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vshufoeh_alt_128BAlias : InstAlias<"$Vdd32=vshuffoeh($Vu32,$Vv32)", (V6_vshufoeh VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vshufoh_altAlias : InstAlias<"$Vd32=vshuffoh($Vu32,$Vv32)", (V6_vshufoh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vshufoh_alt_128BAlias : InstAlias<"$Vd32=vshuffoh($Vu32,$Vv32)", (V6_vshufoh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vsubb_altAlias : InstAlias<"$Vd32=vsubb($Vu32,$Vv32)", (V6_vsubb VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vsubb_alt_128BAlias : InstAlias<"$Vd32=vsubb($Vu32,$Vv32)", (V6_vsubb VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vsubb_dv_altAlias : InstAlias<"$Vdd32=vsubb($Vuu32,$Vvv32)", (V6_vsubb_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
+def V6_vsubb_dv_alt_128BAlias : InstAlias<"$Vdd32=vsubb($Vuu32,$Vvv32)", (V6_vsubb_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
+def V6_vsubbnq_altAlias : InstAlias<"if (!$Qv4.b) $Vx32.b-=$Vu32.b", (V6_vsubbnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vsubbnq_alt_128BAlias : InstAlias<"if (!$Qv4.b) $Vx32.b-=$Vu32.b", (V6_vsubbnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vsubbq_altAlias : InstAlias<"if ($Qv4.b) $Vx32.b-=$Vu32.b", (V6_vsubbq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vsubbq_alt_128BAlias : InstAlias<"if ($Qv4.b) $Vx32.b-=$Vu32.b", (V6_vsubbq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vsubh_altAlias : InstAlias<"$Vd32=vsubh($Vu32,$Vv32)", (V6_vsubh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vsubh_alt_128BAlias : InstAlias<"$Vd32=vsubh($Vu32,$Vv32)", (V6_vsubh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vsubh_dv_altAlias : InstAlias<"$Vdd32=vsubh($Vuu32,$Vvv32)", (V6_vsubh_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
+def V6_vsubh_dv_alt_128BAlias : InstAlias<"$Vdd32=vsubh($Vuu32,$Vvv32)", (V6_vsubh_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
+def V6_vsubhnq_altAlias : InstAlias<"if (!$Qv4.h) $Vx32.h-=$Vu32.h", (V6_vsubhnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vsubhnq_alt_128BAlias : InstAlias<"if (!$Qv4.h) $Vx32.h-=$Vu32.h", (V6_vsubhnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vsubhq_altAlias : InstAlias<"if ($Qv4.h) $Vx32.h-=$Vu32.h", (V6_vsubhq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vsubhq_alt_128BAlias : InstAlias<"if ($Qv4.h) $Vx32.h-=$Vu32.h", (V6_vsubhq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vsubhsat_altAlias : InstAlias<"$Vd32=vsubh($Vu32,$Vv32):sat", (V6_vsubhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vsubhsat_alt_128BAlias : InstAlias<"$Vd32=vsubh($Vu32,$Vv32):sat", (V6_vsubhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vsubhsat_dv_altAlias : InstAlias<"$Vdd32=vsubh($Vuu32,$Vvv32):sat", (V6_vsubhsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
+def V6_vsubhsat_dv_alt_128BAlias : InstAlias<"$Vdd32=vsubh($Vuu32,$Vvv32):sat", (V6_vsubhsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
+def V6_vsubhw_altAlias : InstAlias<"$Vdd32=vsubh($Vu32,$Vv32)", (V6_vsubhw VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vsubhw_alt_128BAlias : InstAlias<"$Vdd32=vsubh($Vu32,$Vv32)", (V6_vsubhw VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vsububh_altAlias : InstAlias<"$Vdd32=vsubub($Vu32,$Vv32)", (V6_vsububh VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vsububh_alt_128BAlias : InstAlias<"$Vdd32=vsubub($Vu32,$Vv32)", (V6_vsububh VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vsububsat_altAlias : InstAlias<"$Vd32=vsubub($Vu32,$Vv32):sat", (V6_vsububsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vsububsat_alt_128BAlias : InstAlias<"$Vd32=vsubub($Vu32,$Vv32):sat", (V6_vsububsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vsububsat_dv_altAlias : InstAlias<"$Vdd32=vsubub($Vuu32,$Vvv32):sat", (V6_vsububsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
+def V6_vsububsat_dv_alt_128BAlias : InstAlias<"$Vdd32=vsubub($Vuu32,$Vvv32):sat", (V6_vsububsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
+def V6_vsubuhsat_altAlias : InstAlias<"$Vd32=vsubuh($Vu32,$Vv32):sat", (V6_vsubuhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vsubuhsat_alt_128BAlias : InstAlias<"$Vd32=vsubuh($Vu32,$Vv32):sat", (V6_vsubuhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vsubuhsat_dv_altAlias : InstAlias<"$Vdd32=vsubuh($Vuu32,$Vvv32):sat", (V6_vsubuhsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
+def V6_vsubuhsat_dv_alt_128BAlias : InstAlias<"$Vdd32=vsubuh($Vuu32,$Vvv32):sat", (V6_vsubuhsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
+def V6_vsubuhw_altAlias : InstAlias<"$Vdd32=vsubuh($Vu32,$Vv32)", (V6_vsubuhw VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vsubuhw_alt_128BAlias : InstAlias<"$Vdd32=vsubuh($Vu32,$Vv32)", (V6_vsubuhw VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vsubw_altAlias : InstAlias<"$Vd32=vsubw($Vu32,$Vv32)", (V6_vsubw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vsubw_alt_128BAlias : InstAlias<"$Vd32=vsubw($Vu32,$Vv32)", (V6_vsubw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vsubw_dv_altAlias : InstAlias<"$Vdd32=vsubw($Vuu32,$Vvv32)", (V6_vsubw_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
+def V6_vsubw_dv_alt_128BAlias : InstAlias<"$Vdd32=vsubw($Vuu32,$Vvv32)", (V6_vsubw_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
+def V6_vsubwnq_altAlias : InstAlias<"if (!$Qv4.w) $Vx32.w-=$Vu32.w", (V6_vsubwnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vsubwnq_alt_128BAlias : InstAlias<"if (!$Qv4.w) $Vx32.w-=$Vu32.w", (V6_vsubwnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vsubwq_altAlias : InstAlias<"if ($Qv4.w) $Vx32.w-=$Vu32.w", (V6_vsubwq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vsubwq_alt_128BAlias : InstAlias<"if ($Qv4.w) $Vx32.w-=$Vu32.w", (V6_vsubwq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vsubwsat_altAlias : InstAlias<"$Vd32=vsubw($Vu32,$Vv32):sat", (V6_vsubwsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vsubwsat_alt_128BAlias : InstAlias<"$Vd32=vsubw($Vu32,$Vv32):sat", (V6_vsubwsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>;
+def V6_vsubwsat_dv_altAlias : InstAlias<"$Vdd32=vsubw($Vuu32,$Vvv32):sat", (V6_vsubwsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
+def V6_vsubwsat_dv_alt_128BAlias : InstAlias<"$Vdd32=vsubw($Vuu32,$Vvv32):sat", (V6_vsubwsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>;
+def V6_vtmpyb_acc_altAlias : InstAlias<"$Vxx32+=vtmpyb($Vuu32,$Rt32)", (V6_vtmpyb_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vtmpyb_acc_alt_128BAlias : InstAlias<"$Vxx32+=vtmpyb($Vuu32,$Rt32)", (V6_vtmpyb_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vtmpyb_altAlias : InstAlias<"$Vdd32=vtmpyb($Vuu32,$Rt32)", (V6_vtmpyb VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vtmpyb_alt_128BAlias : InstAlias<"$Vdd32=vtmpyb($Vuu32,$Rt32)", (V6_vtmpyb VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vtmpybus_acc_altAlias : InstAlias<"$Vxx32+=vtmpybus($Vuu32,$Rt32)", (V6_vtmpybus_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vtmpybus_acc_alt_128BAlias : InstAlias<"$Vxx32+=vtmpybus($Vuu32,$Rt32)", (V6_vtmpybus_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vtmpybus_altAlias : InstAlias<"$Vdd32=vtmpybus($Vuu32,$Rt32)", (V6_vtmpybus VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vtmpybus_alt_128BAlias : InstAlias<"$Vdd32=vtmpybus($Vuu32,$Rt32)", (V6_vtmpybus VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vtmpyhb_acc_altAlias : InstAlias<"$Vxx32+=vtmpyhb($Vuu32,$Rt32)", (V6_vtmpyhb_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vtmpyhb_acc_alt_128BAlias : InstAlias<"$Vxx32+=vtmpyhb($Vuu32,$Rt32)", (V6_vtmpyhb_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vtmpyhb_altAlias : InstAlias<"$Vdd32=vtmpyhb($Vuu32,$Rt32)", (V6_vtmpyhb VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vtmpyhb_alt_128BAlias : InstAlias<"$Vdd32=vtmpyhb($Vuu32,$Rt32)", (V6_vtmpyhb VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vtran2x2_mapAlias : InstAlias<"vtrans2x2($Vy32,$Vx32,$Rt32)", (V6_vshuff VectorRegs:$Vy32, VectorRegs:$Vx32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vtran2x2_map_128BAlias : InstAlias<"vtrans2x2($Vy32,$Vx32,$Rt32)", (V6_vshuff VectorRegs:$Vy32, VectorRegs:$Vx32, IntRegs:$Rt32)>, Requires<[UseHVX]>;
+def V6_vunpackb_altAlias : InstAlias<"$Vdd32=vunpackb($Vu32)", (V6_vunpackb VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vunpackb_alt_128BAlias : InstAlias<"$Vdd32=vunpackb($Vu32)", (V6_vunpackb VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vunpackh_altAlias : InstAlias<"$Vdd32=vunpackh($Vu32)", (V6_vunpackh VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vunpackh_alt_128BAlias : InstAlias<"$Vdd32=vunpackh($Vu32)", (V6_vunpackh VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vunpackoh_altAlias : InstAlias<"$Vxx32|=vunpackoh($Vu32)", (V6_vunpackoh VecDblRegs:$Vxx32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vunpackoh_alt_128BAlias : InstAlias<"$Vxx32|=vunpackoh($Vu32)", (V6_vunpackoh VecDblRegs:$Vxx32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vunpackub_altAlias : InstAlias<"$Vdd32=vunpackub($Vu32)", (V6_vunpackub VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vunpackub_alt_128BAlias : InstAlias<"$Vdd32=vunpackub($Vu32)", (V6_vunpackub VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vunpackuh_altAlias : InstAlias<"$Vdd32=vunpackuh($Vu32)", (V6_vunpackuh VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vunpackuh_alt_128BAlias : InstAlias<"$Vdd32=vunpackuh($Vu32)", (V6_vunpackuh VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vzb_altAlias : InstAlias<"$Vdd32=vzxtb($Vu32)", (V6_vzb VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vzb_alt_128BAlias : InstAlias<"$Vdd32=vzxtb($Vu32)", (V6_vzb VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vzh_altAlias : InstAlias<"$Vdd32=vzxth($Vu32)", (V6_vzh VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def V6_vzh_alt_128BAlias : InstAlias<"$Vdd32=vzxth($Vu32)", (V6_vzh VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>;
+def Y2_dcfetchAlias : InstAlias<"dcfetch($Rs32)", (Y2_dcfetchbo IntRegs:$Rs32, 0)>;
Added: llvm/trunk/lib/Target/Hexagon/HexagonDepOperands.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonDepOperands.td?rev=294753&view=auto
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonDepOperands.td (added)
+++ llvm/trunk/lib/Target/Hexagon/HexagonDepOperands.td Fri Feb 10 09:33:13 2017
@@ -0,0 +1,141 @@
+//===--- HexagonDepOperands.td --------------------------------------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+def s4_0ImmOperand : AsmOperandClass { let Name = "s4_0Imm"; let RenderMethod = "addSignedImmOperands"; }
+def s4_0Imm : Operand<i32> { let ParserMatchClass = s4_0ImmOperand; let DecoderMethod = "s4_0ImmDecoder"; }
+def s4_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<4, 0>(N->getSExtValue());}]>;
+def s29_3ImmOperand : AsmOperandClass { let Name = "s29_3Imm"; let RenderMethod = "addSignedImmOperands"; }
+def s29_3Imm : Operand<i32> { let ParserMatchClass = s29_3ImmOperand; let DecoderMethod = "s29_3ImmDecoder"; }
+def s29_3ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<32, 3>(N->getSExtValue());}]>;
+def s10_6ImmOperand : AsmOperandClass { let Name = "s10_6Imm"; let RenderMethod = "addSignedImmOperands"; }
+def s10_6Imm : Operand<i32> { let ParserMatchClass = s10_6ImmOperand; let DecoderMethod = "s10_6ImmDecoder"; }
+def s10_6ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<10, 6>(N->getSExtValue());}]>;
+def u6_0ImmOperand : AsmOperandClass { let Name = "u6_0Imm"; let RenderMethod = "addImmOperands"; }
+def u6_0Imm : Operand<i32> { let ParserMatchClass = u6_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
+def u6_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<6, 0>(N->getSExtValue());}]>;
+def a30_2ImmOperand : AsmOperandClass { let Name = "a30_2Imm"; let RenderMethod = "addSignedImmOperands"; }
+def a30_2Imm : Operand<i32> { let ParserMatchClass = a30_2ImmOperand; let DecoderMethod = "brtargetDecoder"; let PrintMethod = "printBrtarget"; }
+def a30_2ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<32, 2>(N->getSExtValue());}]>;
+def u29_3ImmOperand : AsmOperandClass { let Name = "u29_3Imm"; let RenderMethod = "addImmOperands"; }
+def u29_3Imm : Operand<i32> { let ParserMatchClass = u29_3ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
+def u29_3ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<32, 3>(N->getSExtValue());}]>;
+def s8_0ImmOperand : AsmOperandClass { let Name = "s8_0Imm"; let RenderMethod = "addSignedImmOperands"; }
+def s8_0Imm : Operand<i32> { let ParserMatchClass = s8_0ImmOperand; let DecoderMethod = "s8_0ImmDecoder"; }
+def s8_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<8, 0>(N->getSExtValue());}]>;
+def u32_0ImmOperand : AsmOperandClass { let Name = "u32_0Imm"; let RenderMethod = "addImmOperands"; }
+def u32_0Imm : Operand<i32> { let ParserMatchClass = u32_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
+def u32_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<32, 0>(N->getSExtValue());}]>;
+def u4_2ImmOperand : AsmOperandClass { let Name = "u4_2Imm"; let RenderMethod = "addImmOperands"; }
+def u4_2Imm : Operand<i32> { let ParserMatchClass = u4_2ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
+def u4_2ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<4, 2>(N->getSExtValue());}]>;
+def u3_0ImmOperand : AsmOperandClass { let Name = "u3_0Imm"; let RenderMethod = "addImmOperands"; }
+def u3_0Imm : Operand<i32> { let ParserMatchClass = u3_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
+def u3_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<3, 0>(N->getSExtValue());}]>;
+def b15_2ImmOperand : AsmOperandClass { let Name = "b15_2Imm"; let RenderMethod = "addSignedImmOperands"; }
+def b15_2Imm : Operand<OtherVT> { let ParserMatchClass = b15_2ImmOperand; let DecoderMethod = "brtargetDecoder"; let PrintMethod = "printBrtarget"; }
+def b15_2ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<15, 2>(N->getSExtValue());}]>;
+def u11_3ImmOperand : AsmOperandClass { let Name = "u11_3Imm"; let RenderMethod = "addImmOperands"; }
+def u11_3Imm : Operand<i32> { let ParserMatchClass = u11_3ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
+def u11_3ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<11, 3>(N->getSExtValue());}]>;
+def s4_3ImmOperand : AsmOperandClass { let Name = "s4_3Imm"; let RenderMethod = "addSignedImmOperands"; }
+def s4_3Imm : Operand<i32> { let ParserMatchClass = s4_3ImmOperand; let DecoderMethod = "s4_3ImmDecoder"; }
+def s4_3ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<4, 3>(N->getSExtValue());}]>;
+def m32_0ImmOperand : AsmOperandClass { let Name = "m32_0Imm"; let RenderMethod = "addImmOperands"; }
+def m32_0Imm : Operand<i32> { let ParserMatchClass = m32_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
+def m32_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<32, 0>(N->getSExtValue());}]>;
+def u3_1ImmOperand : AsmOperandClass { let Name = "u3_1Imm"; let RenderMethod = "addImmOperands"; }
+def u3_1Imm : Operand<i32> { let ParserMatchClass = u3_1ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
+def u3_1ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<3, 1>(N->getSExtValue());}]>;
+def u1_0ImmOperand : AsmOperandClass { let Name = "u1_0Imm"; let RenderMethod = "addImmOperands"; }
+def u1_0Imm : Operand<i32> { let ParserMatchClass = u1_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
+def u1_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<1, 0>(N->getSExtValue());}]>;
+def s31_1ImmOperand : AsmOperandClass { let Name = "s31_1Imm"; let RenderMethod = "addSignedImmOperands"; }
+def s31_1Imm : Operand<i32> { let ParserMatchClass = s31_1ImmOperand; let DecoderMethod = "s31_1ImmDecoder"; }
+def s31_1ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<32, 1>(N->getSExtValue());}]>;
+def s30_2ImmOperand : AsmOperandClass { let Name = "s30_2Imm"; let RenderMethod = "addSignedImmOperands"; }
+def s30_2Imm : Operand<i32> { let ParserMatchClass = s30_2ImmOperand; let DecoderMethod = "s30_2ImmDecoder"; }
+def s30_2ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<32, 2>(N->getSExtValue());}]>;
+def u4_0ImmOperand : AsmOperandClass { let Name = "u4_0Imm"; let RenderMethod = "addImmOperands"; }
+def u4_0Imm : Operand<i32> { let ParserMatchClass = u4_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
+def u4_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<4, 0>(N->getSExtValue());}]>;
+def s6_0ImmOperand : AsmOperandClass { let Name = "s6_0Imm"; let RenderMethod = "addSignedImmOperands"; }
+def s6_0Imm : Operand<i32> { let ParserMatchClass = s6_0ImmOperand; let DecoderMethod = "s6_0ImmDecoder"; }
+def s6_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<6, 0>(N->getSExtValue());}]>;
+def u5_3ImmOperand : AsmOperandClass { let Name = "u5_3Imm"; let RenderMethod = "addImmOperands"; }
+def u5_3Imm : Operand<i32> { let ParserMatchClass = u5_3ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
+def u5_3ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<5, 3>(N->getSExtValue());}]>;
+def s4_7ImmOperand : AsmOperandClass { let Name = "s4_7Imm"; }
+def s4_7Imm : Operand<i32> { let ParserMatchClass = s4_7ImmOperand; let DecoderMethod = "s4_7ImmDecoder"; let PrintMethod = "prints4_7ImmOperand"; }
+def s4_7ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<4, 7>(N->getSExtValue());}]>;
+def s32_0ImmOperand : AsmOperandClass { let Name = "s32_0Imm"; let RenderMethod = "addSignedImmOperands"; }
+def s32_0Imm : Operand<i32> { let ParserMatchClass = s32_0ImmOperand; let DecoderMethod = "s32_0ImmDecoder"; }
+def s32_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<32, 0>(N->getSExtValue());}]>;
+def s6_3ImmOperand : AsmOperandClass { let Name = "s6_3Imm"; let RenderMethod = "addSignedImmOperands"; }
+def s6_3Imm : Operand<i32> { let ParserMatchClass = s6_3ImmOperand; let DecoderMethod = "s6_3ImmDecoder"; }
+def s6_3ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<6, 3>(N->getSExtValue());}]>;
+def u10_0ImmOperand : AsmOperandClass { let Name = "u10_0Imm"; let RenderMethod = "addImmOperands"; }
+def u10_0Imm : Operand<i32> { let ParserMatchClass = u10_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
+def u10_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<10, 0>(N->getSExtValue());}]>;
+def s3_6ImmOperand : AsmOperandClass { let Name = "s3_6Imm"; }
+def s3_6Imm : Operand<i32> { let ParserMatchClass = s3_6ImmOperand; let DecoderMethod = "s3_6ImmDecoder"; let PrintMethod = "prints3_6ImmOperand"; }
+def s3_6ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<3, 6>(N->getSExtValue());}]>;
+def u31_1ImmOperand : AsmOperandClass { let Name = "u31_1Imm"; let RenderMethod = "addImmOperands"; }
+def u31_1Imm : Operand<i32> { let ParserMatchClass = u31_1ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
+def u31_1ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<32, 1>(N->getSExtValue());}]>;
+def s4_1ImmOperand : AsmOperandClass { let Name = "s4_1Imm"; let RenderMethod = "addSignedImmOperands"; }
+def s4_1Imm : Operand<i32> { let ParserMatchClass = s4_1ImmOperand; let DecoderMethod = "s4_1ImmDecoder"; }
+def s4_1ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<4, 1>(N->getSExtValue());}]>;
+def u16_0ImmOperand : AsmOperandClass { let Name = "u16_0Imm"; let RenderMethod = "addImmOperands"; }
+def u16_0Imm : Operand<i32> { let ParserMatchClass = u16_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
+def u16_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<16, 0>(N->getSExtValue());}]>;
+def u6_1ImmOperand : AsmOperandClass { let Name = "u6_1Imm"; let RenderMethod = "addImmOperands"; }
+def u6_1Imm : Operand<i32> { let ParserMatchClass = u6_1ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
+def u6_1ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<6, 1>(N->getSExtValue());}]>;
+def u5_2ImmOperand : AsmOperandClass { let Name = "u5_2Imm"; let RenderMethod = "addImmOperands"; }
+def u5_2Imm : Operand<i32> { let ParserMatchClass = u5_2ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
+def u5_2ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<5, 2>(N->getSExtValue());}]>;
+def u26_6ImmOperand : AsmOperandClass { let Name = "u26_6Imm"; let RenderMethod = "addImmOperands"; }
+def u26_6Imm : Operand<i32> { let ParserMatchClass = u26_6ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
+def u26_6ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<26, 6>(N->getSExtValue());}]>;
+def u6_2ImmOperand : AsmOperandClass { let Name = "u6_2Imm"; let RenderMethod = "addImmOperands"; }
+def u6_2Imm : Operand<i32> { let ParserMatchClass = u6_2ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
+def u6_2ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<6, 2>(N->getSExtValue());}]>;
+def u7_0ImmOperand : AsmOperandClass { let Name = "u7_0Imm"; let RenderMethod = "addImmOperands"; }
+def u7_0Imm : Operand<i32> { let ParserMatchClass = u7_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
+def u7_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<7, 0>(N->getSExtValue());}]>;
+def b13_2ImmOperand : AsmOperandClass { let Name = "b13_2Imm"; let RenderMethod = "addSignedImmOperands"; }
+def b13_2Imm : Operand<OtherVT> { let ParserMatchClass = b13_2ImmOperand; let DecoderMethod = "brtargetDecoder"; let PrintMethod = "printBrtarget"; }
+def b13_2ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<13, 2>(N->getSExtValue());}]>;
+def u5_0ImmOperand : AsmOperandClass { let Name = "u5_0Imm"; let RenderMethod = "addImmOperands"; }
+def u5_0Imm : Operand<i32> { let ParserMatchClass = u5_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
+def u5_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<5, 0>(N->getSExtValue());}]>;
+def u2_0ImmOperand : AsmOperandClass { let Name = "u2_0Imm"; let RenderMethod = "addImmOperands"; }
+def u2_0Imm : Operand<i32> { let ParserMatchClass = u2_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
+def u2_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<2, 0>(N->getSExtValue());}]>;
+def s4_2ImmOperand : AsmOperandClass { let Name = "s4_2Imm"; let RenderMethod = "addSignedImmOperands"; }
+def s4_2Imm : Operand<i32> { let ParserMatchClass = s4_2ImmOperand; let DecoderMethod = "s4_2ImmDecoder"; }
+def s4_2ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<4, 2>(N->getSExtValue());}]>;
+def b30_2ImmOperand : AsmOperandClass { let Name = "b30_2Imm"; let RenderMethod = "addSignedImmOperands"; }
+def b30_2Imm : Operand<OtherVT> { let ParserMatchClass = b30_2ImmOperand; let DecoderMethod = "brtargetDecoder"; let PrintMethod = "printBrtarget"; }
+def b30_2ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<32, 2>(N->getSExtValue());}]>;
+def u8_0ImmOperand : AsmOperandClass { let Name = "u8_0Imm"; let RenderMethod = "addImmOperands"; }
+def u8_0Imm : Operand<i32> { let ParserMatchClass = u8_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
+def u8_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<8, 0>(N->getSExtValue());}]>;
+def s3_7ImmOperand : AsmOperandClass { let Name = "s3_7Imm"; }
+def s3_7Imm : Operand<i32> { let ParserMatchClass = s3_7ImmOperand; let DecoderMethod = "s3_7ImmDecoder"; let PrintMethod = "prints3_7ImmOperand"; }
+def s3_7ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<3, 7>(N->getSExtValue());}]>;
+def u30_2ImmOperand : AsmOperandClass { let Name = "u30_2Imm"; let RenderMethod = "addImmOperands"; }
+def u30_2Imm : Operand<i32> { let ParserMatchClass = u30_2ImmOperand; let DecoderMethod = "unsignedImmDecoder"; }
+def u30_2ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<32, 2>(N->getSExtValue());}]>;
+def s4_6ImmOperand : AsmOperandClass { let Name = "s4_6Imm"; }
+def s4_6Imm : Operand<i32> { let ParserMatchClass = s4_6ImmOperand; let DecoderMethod = "s4_6ImmDecoder"; let PrintMethod = "prints4_6ImmOperand"; }
+def s4_6ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<4, 6>(N->getSExtValue());}]>;
+def s10_0ImmOperand : AsmOperandClass { let Name = "s10_0Imm"; let RenderMethod = "addSignedImmOperands"; }
+def s10_0Imm : Operand<i32> { let ParserMatchClass = s10_0ImmOperand; let DecoderMethod = "s10_0ImmDecoder"; }
+def s10_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<10, 0>(N->getSExtValue());}]>;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrFormats.td?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrFormats.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrFormats.td Fri Feb 10 09:33:13 2017
@@ -7,29 +7,6 @@
//
//===----------------------------------------------------------------------===//
-//===----------------------------------------------------------------------===//
-// Hexagon Instruction Flags +
-//
-// *** Must match HexagonBaseInfo.h ***
-//===----------------------------------------------------------------------===//
-
-class IType<bits<6> t> {
- bits<6> Value = t;
-}
-def TypePSEUDO : IType<0>;
-def TypeCR : IType<2>;
-def TypeJ : IType<4>;
-def TypeLD : IType<5>;
-def TypeST : IType<6>;
-def TypeENDLOOP: IType<40>;
-def TypeS_2op: IType<41>;
-def TypeS_3op: IType<42>;
-def TypeALU64: IType<43>;
-def TypeM: IType<44>;
-def TypeALU32_2op: IType<45>;
-def TypeALU32_3op: IType<46>;
-def TypeALU32_ADDI: IType<47>;
-
// Maintain list of valid subtargets for each instruction.
class SubTarget<bits<6> value> {
bits<6> Value = value;
@@ -57,6 +34,7 @@ class MemAccessSize<bits<4> value> {
bits<4> Value = value;
}
+// MemAccessSize is represented as 1+log2(N) where N is size in bits.
def NoMemAccess : MemAccessSize<0>;// Not a memory access instruction.
def ByteAccess : MemAccessSize<1>;// Byte access instruction (memb).
def HalfWordAccess : MemAccessSize<2>;// Half word access instruction (memh).
@@ -73,10 +51,9 @@ def Vector128Access : MemAccessSize<8>;
class OpcodeHexagon {
field bits<32> Inst = ?; // Default to an invalid insn.
bits<4> IClass = 0; // ICLASS
+ bits<1> zero = 0;
let Inst{31-28} = IClass;
-
- bits<1> zero = 0;
}
class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
@@ -182,6 +159,9 @@ class InstHexagon<dag outs, dag ins, str
bits<1> isAccumulator = 0;
let TSFlags{55} = isAccumulator;
+ bits<1> prefersSlot3 = 0;
+ let TSFlags{56} = prefersSlot3; // Complex XU
+
bit cofMax1 = 0;
let TSFlags{60} = cofMax1;
@@ -207,6 +187,9 @@ class InstHexagon<dag outs, dag ins, str
// *** Must match MCTargetDesc/HexagonBaseInfo.h ***
}
+class HInst<dag outs, dag ins, string asmstr, InstrItinClass itin, IType type> :
+ InstHexagon<outs, ins, asmstr, [], "", itin, type>;
+
//===----------------------------------------------------------------------===//
// Instruction Classes Definitions +
//===----------------------------------------------------------------------===//
@@ -218,14 +201,13 @@ class LDInst<dag outs, dag ins, string a
string cstr = "", InstrItinClass itin = LD_tc_ld_SLOT01>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>, OpcodeHexagon;
-let mayLoad = 1 in
-class LDInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [],
- string cstr = "">
- : LDInst<outs, ins, asmstr, pattern, cstr>;
+class PseudoLDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
+ string cstr = "", InstrItinClass itin = LD_tc_ld_SLOT01>
+ : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>, OpcodeHexagon;
class CONSTLDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
string cstr = "">
- : LDInst<outs, ins, asmstr, pattern, cstr>;
+ : PseudoLDInst<outs, ins, asmstr, pattern, cstr>;
// LD Instruction Class in V2/V3/V4.
// Definition of the instruction class NOT CHANGED.
@@ -251,6 +233,11 @@ class STInst<dag outs, dag ins, string a
string cstr = "", InstrItinClass itin = ST_tc_st_SLOT01>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeST>, OpcodeHexagon;
+let mayStore = 1 in
+class STInst_NoOpcode<dag outs, dag ins, string asmstr, list<dag> pattern = [],
+ string cstr = "", InstrItinClass itin = ST_tc_st_SLOT01>
+ : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeST>;
+
class STInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [],
string cstr = "">
: STInst<outs, ins, asmstr, pattern, cstr>;
@@ -273,25 +260,6 @@ class STInstPost<dag outs, dag ins, stri
string cstr = "", InstrItinClass itin = ST_tc_st_SLOT01>
: STInst<outs, ins, asmstr, pattern, cstr, itin>;
-// SYSTEM Instruction Class in V4 can take SLOT0 only
-// In V2/V3 we used ST for this but in v4 ST can take SLOT0 or SLOT1.
-class SYSInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
- string cstr = "", InstrItinClass itin = ST_tc_3stall_SLOT0>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeST>,
- OpcodeHexagon;
-
-// ALU32 Instruction Class in V2/V3/V4.
-// Definition of the instruction class NOT CHANGED.
-class ALU32Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
- string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeALU32_2op>, OpcodeHexagon;
-
-// ALU32 Instruction Class in V2/V3/V4.
-// Definition of the instruction class NOT CHANGED.
-class ALU32Inst_NoOpcode<dag outs, dag ins, string asmstr, list<dag> pattern = [],
- string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeALU32_2op>;
-
// ALU64 Instruction Class in V2/V3.
// XTYPE Instruction Class in V4.
// Definition of the instruction class NOT CHANGED.
@@ -374,12 +342,6 @@ class JInst_CJUMP_UCJUMP<dag outs, dag i
string cstr = "", InstrItinClass itin = J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeJ>, OpcodeHexagon;
-// JR Instruction Class in V2/V3/V4.
-// Definition of the instruction class NOT CHANGED.
-class JRInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
- string cstr = "", InstrItinClass itin = J_tc_2early_SLOT2>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeJ>, OpcodeHexagon;
-
// CR Instruction Class in V2/V3/V4.
// Definition of the instruction class NOT CHANGED.
class CRInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
@@ -408,26 +370,6 @@ class PseudoM<dag outs, dag ins, string
// Instruction Classes Definitions -
//===----------------------------------------------------------------------===//
-
-//
-// ALU32 patterns
-//.
-class ALU32_rr<dag outs, dag ins, string asmstr, list<dag> pattern = [],
- string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123>
- : ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>;
-
-class ALU32_ir<dag outs, dag ins, string asmstr, list<dag> pattern = [],
- string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123>
- : ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>;
-
-class ALU32_ri<dag outs, dag ins, string asmstr, list<dag> pattern = [],
- string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123>
- : ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>;
-
-class ALU32_ii<dag outs, dag ins, string asmstr, list<dag> pattern = [],
- string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123>
- : ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>;
-
//
// ALU64 patterns.
//
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrFormatsV4.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrFormatsV4.td?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrFormatsV4.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrFormatsV4.td Fri Feb 10 09:33:13 2017
@@ -11,18 +11,6 @@
//
//===----------------------------------------------------------------------===//
-//----------------------------------------------------------------------------//
-// Hexagon Instruction Flags
-//
-// *** Must match BaseInfo.h ***
-//----------------------------------------------------------------------------//
-
-def TypeV4LDST : IType<9>;
-def TypeNCJ : IType<10>;
-def TypeDUPLEX : IType<11>;
-def TypeCJ : IType<12>;
-def TypeEXTENDER : IType<39>;
-
// Duplex Instruction Class Declaration
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrFormatsV60.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrFormatsV60.td?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrFormatsV60.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrFormatsV60.td Fri Feb 10 09:33:13 2017
@@ -12,28 +12,6 @@
//===----------------------------------------------------------------------===//
//----------------------------------------------------------------------------//
-// Hexagon Instruction Flags +
-//
-// *** Must match BaseInfo.h ***
-//----------------------------------------------------------------------------//
-
-def TypeCVI_VA : IType<13>;
-def TypeCVI_VA_DV : IType<14>;
-def TypeCVI_VX : IType<15>;
-def TypeCVI_VX_DV : IType<16>;
-def TypeCVI_VP : IType<17>;
-def TypeCVI_VP_VS : IType<18>;
-def TypeCVI_VS : IType<19>;
-def TypeCVI_VINLANESAT : IType<20>;
-def TypeCVI_VM_LD : IType<21>;
-def TypeCVI_VM_TMP_LD : IType<22>;
-def TypeCVI_VM_CUR_LD : IType<23>;
-def TypeCVI_VM_VP_LDU : IType<24>;
-def TypeCVI_VM_ST : IType<25>;
-def TypeCVI_VM_NEW_ST : IType<26>;
-def TypeCVI_VM_STU : IType<27>;
-def TypeCVI_HIST : IType<28>;
-//----------------------------------------------------------------------------//
// Instruction Classes Definitions +
//----------------------------------------------------------------------------//
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp Fri Feb 10 09:33:13 2017
@@ -3419,7 +3419,9 @@ int HexagonInstrInfo::getDotNewOp(const
return NVOpcode;
switch (MI.getOpcode()) {
- default: llvm_unreachable("Unknown .new type");
+ default:
+ llvm::report_fatal_error(std::string("Unknown .new type: ") +
+ std::to_string(MI.getOpcode()).c_str());
case Hexagon::S4_storerb_ur:
return Hexagon::S4_storerbnew_ur;
Removed: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td?rev=294752&view=auto
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td (removed)
@@ -1,4796 +0,0 @@
-//==- HexagonInstrInfo.td - Target Description for Hexagon -*- tablegen -*-===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file describes the Hexagon instructions in TableGen format.
-//
-//===----------------------------------------------------------------------===//
-
-include "HexagonInstrFormats.td"
-include "HexagonOperands.td"
-include "HexagonInstrEnc.td"
-
-//===----------------------------------------------------------------------===//
-// Compare
-//===----------------------------------------------------------------------===//
-let hasSideEffects = 0, isCompare = 1, InputType = "imm", isExtendable = 1,
- opExtendable = 2 in
-class T_CMP <string mnemonic, bits<2> MajOp, bit isNot, Operand ImmOp>
- : ALU32Inst <(outs PredRegs:$dst),
- (ins IntRegs:$src1, ImmOp:$src2),
- "$dst = "#!if(isNot, "!","")#mnemonic#"($src1, #$src2)",
- [], "",ALU32_2op_tc_2early_SLOT0123 >, ImmRegRel {
- bits<2> dst;
- bits<5> src1;
- bits<10> src2;
- let CextOpcode = mnemonic;
- let opExtentBits = !if(!eq(mnemonic, "cmp.gtu"), 9, 10);
- let isExtentSigned = !if(!eq(mnemonic, "cmp.gtu"), 0, 1);
-
- let IClass = 0b0111;
-
- let Inst{27-24} = 0b0101;
- let Inst{23-22} = MajOp;
- let Inst{21} = !if(!eq(mnemonic, "cmp.gtu"), 0, src2{9});
- let Inst{20-16} = src1;
- let Inst{13-5} = src2{8-0};
- let Inst{4} = isNot;
- let Inst{3-2} = 0b00;
- let Inst{1-0} = dst;
- }
-
-def C2_cmpeqi : T_CMP <"cmp.eq", 0b00, 0, s10_0Ext>;
-def C2_cmpgti : T_CMP <"cmp.gt", 0b01, 0, s10_0Ext>;
-def C2_cmpgtui : T_CMP <"cmp.gtu", 0b10, 0, u9_0Ext>;
-
-//===----------------------------------------------------------------------===//
-// ALU32/ALU +
-//===----------------------------------------------------------------------===//
-// Add.
-
-let hasSideEffects = 0, hasNewValue = 1, InputType = "reg" in
-class T_ALU32_3op<string mnemonic, bits<3> MajOp, bits<3> MinOp, bit OpsRev,
- bit IsComm>
- : ALU32_rr<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
- "$Rd = "#mnemonic#"($Rs, $Rt)",
- [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel, PredRel {
- let isCommutable = IsComm;
- let BaseOpcode = mnemonic#_rr;
- let CextOpcode = mnemonic;
- let Type = TypeALU32_3op;
-
- bits<5> Rs;
- bits<5> Rt;
- bits<5> Rd;
-
- let IClass = 0b1111;
- let Inst{27} = 0b0;
- let Inst{26-24} = MajOp;
- let Inst{23-21} = MinOp;
- let Inst{20-16} = !if(OpsRev,Rt,Rs);
- let Inst{12-8} = !if(OpsRev,Rs,Rt);
- let Inst{4-0} = Rd;
-}
-
-let hasSideEffects = 0, hasNewValue = 1 in
-class T_ALU32_3op_pred<string mnemonic, bits<3> MajOp, bits<3> MinOp,
- bit OpsRev, bit PredNot, bit PredNew>
- : ALU32_rr<(outs IntRegs:$Rd), (ins PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt),
- "if ("#!if(PredNot,"!","")#"$Pu"#!if(PredNew,".new","")#") "#
- "$Rd = "#mnemonic#"($Rs, $Rt)",
- [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel, PredNewRel {
- let isPredicated = 1;
- let isPredicatedFalse = PredNot;
- let isPredicatedNew = PredNew;
- let BaseOpcode = mnemonic#_rr;
- let CextOpcode = mnemonic;
- let Type = TypeALU32_3op;
-
- bits<2> Pu;
- bits<5> Rs;
- bits<5> Rt;
- bits<5> Rd;
-
- let IClass = 0b1111;
- let Inst{27} = 0b1;
- let Inst{26-24} = MajOp;
- let Inst{23-21} = MinOp;
- let Inst{20-16} = !if(OpsRev,Rt,Rs);
- let Inst{13} = PredNew;
- let Inst{12-8} = !if(OpsRev,Rs,Rt);
- let Inst{7} = PredNot;
- let Inst{6-5} = Pu;
- let Inst{4-0} = Rd;
-}
-
-class T_ALU32_combineh<string Op1, string Op2, bits<3> MajOp, bits<3> MinOp,
- bit OpsRev>
- : T_ALU32_3op<"", MajOp, MinOp, OpsRev, 0> {
- let AsmString = "$Rd = combine($Rs"#Op1#", $Rt"#Op2#")";
-}
-
-def A2_combine_hh : T_ALU32_combineh<".h", ".h", 0b011, 0b100, 1>;
-def A2_combine_hl : T_ALU32_combineh<".h", ".l", 0b011, 0b101, 1>;
-def A2_combine_lh : T_ALU32_combineh<".l", ".h", 0b011, 0b110, 1>;
-def A2_combine_ll : T_ALU32_combineh<".l", ".l", 0b011, 0b111, 1>;
-
-class T_ALU32_3op_sfx<string mnemonic, string suffix, bits<3> MajOp,
- bits<3> MinOp, bit OpsRev, bit IsComm>
- : T_ALU32_3op<"", MajOp, MinOp, OpsRev, IsComm> {
- let AsmString = "$Rd = "#mnemonic#"($Rs, $Rt)"#suffix;
-}
-
-def A2_svaddh : T_ALU32_3op<"vaddh", 0b110, 0b000, 0, 1>;
-def A2_svsubh : T_ALU32_3op<"vsubh", 0b110, 0b100, 1, 0>;
-
-let Defs = [USR_OVF], Itinerary = ALU32_3op_tc_2_SLOT0123 in {
- def A2_svaddhs : T_ALU32_3op_sfx<"vaddh", ":sat", 0b110, 0b001, 0, 1>;
- def A2_addsat : T_ALU32_3op_sfx<"add", ":sat", 0b110, 0b010, 0, 1>;
- def A2_svadduhs : T_ALU32_3op_sfx<"vadduh", ":sat", 0b110, 0b011, 0, 1>;
- def A2_svsubhs : T_ALU32_3op_sfx<"vsubh", ":sat", 0b110, 0b101, 1, 0>;
- def A2_subsat : T_ALU32_3op_sfx<"sub", ":sat", 0b110, 0b110, 1, 0>;
- def A2_svsubuhs : T_ALU32_3op_sfx<"vsubuh", ":sat", 0b110, 0b111, 1, 0>;
-}
-
-let Itinerary = ALU32_3op_tc_2_SLOT0123 in
-def A2_svavghs : T_ALU32_3op_sfx<"vavgh", ":rnd", 0b111, 0b001, 0, 1>;
-
-def A2_svavgh : T_ALU32_3op<"vavgh", 0b111, 0b000, 0, 1>;
-def A2_svnavgh : T_ALU32_3op<"vnavgh", 0b111, 0b011, 1, 0>;
-
-multiclass T_ALU32_3op_p<string mnemonic, bits<3> MajOp, bits<3> MinOp,
- bit OpsRev> {
- def t : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 0, 0>;
- def f : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 1, 0>;
- def tnew : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 0, 1>;
- def fnew : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 1, 1>;
-}
-
-multiclass T_ALU32_3op_A2<string mnemonic, bits<3> MajOp, bits<3> MinOp,
- bit OpsRev, bit IsComm> {
- let isPredicable = 1 in
- def A2_#NAME : T_ALU32_3op <mnemonic, MajOp, MinOp, OpsRev, IsComm>;
- defm A2_p#NAME : T_ALU32_3op_p<mnemonic, MajOp, MinOp, OpsRev>;
-}
-
-defm add : T_ALU32_3op_A2<"add", 0b011, 0b000, 0, 1>;
-defm and : T_ALU32_3op_A2<"and", 0b001, 0b000, 0, 1>;
-defm or : T_ALU32_3op_A2<"or", 0b001, 0b001, 0, 1>;
-defm sub : T_ALU32_3op_A2<"sub", 0b011, 0b001, 1, 0>;
-defm xor : T_ALU32_3op_A2<"xor", 0b001, 0b011, 0, 1>;
-
-// A few special cases producing register pairs:
-let OutOperandList = (outs DoubleRegs:$Rd), hasNewValue = 0 in {
- def S2_packhl : T_ALU32_3op <"packhl", 0b101, 0b100, 0, 0>;
-
- let isPredicable = 1 in
- def A2_combinew : T_ALU32_3op <"combine", 0b101, 0b000, 0, 0>;
-
- // Conditional combinew uses "newt/f" instead of "t/fnew".
- def C2_ccombinewt : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 0, 0>;
- def C2_ccombinewf : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 1, 0>;
- def C2_ccombinewnewt : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 0, 1>;
- def C2_ccombinewnewf : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 1, 1>;
-}
-
-let hasSideEffects = 0, hasNewValue = 1, isCompare = 1, InputType = "reg" in
-class T_ALU32_3op_cmp<string mnemonic, bits<2> MinOp, bit IsNeg, bit IsComm>
- : ALU32_rr<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
- "$Pd = "#mnemonic#"($Rs, $Rt)",
- [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel {
- let CextOpcode = mnemonic;
- let isCommutable = IsComm;
- let Type = TypeALU32_3op;
- bits<5> Rs;
- bits<5> Rt;
- bits<2> Pd;
-
- let IClass = 0b1111;
- let Inst{27-24} = 0b0010;
- let Inst{22-21} = MinOp;
- let Inst{20-16} = Rs;
- let Inst{12-8} = Rt;
- let Inst{4} = IsNeg;
- let Inst{3-2} = 0b00;
- let Inst{1-0} = Pd;
-}
-
-let Itinerary = ALU32_3op_tc_2early_SLOT0123 in {
- def C2_cmpeq : T_ALU32_3op_cmp< "cmp.eq", 0b00, 0, 1>;
- def C2_cmpgt : T_ALU32_3op_cmp< "cmp.gt", 0b10, 0, 0>;
- def C2_cmpgtu : T_ALU32_3op_cmp< "cmp.gtu", 0b11, 0, 0>;
-}
-
-let CextOpcode = "MUX", InputType = "reg", hasNewValue = 1 in
-def C2_mux: ALU32_rr<(outs IntRegs:$Rd),
- (ins PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt),
- "$Rd = mux($Pu, $Rs, $Rt)", [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel {
- bits<5> Rd;
- bits<2> Pu;
- bits<5> Rs;
- bits<5> Rt;
-
- let CextOpcode = "mux";
- let InputType = "reg";
- let hasSideEffects = 0;
- let IClass = 0b1111;
- let Type = TypeALU32_3op;
-
- let Inst{27-24} = 0b0100;
- let Inst{20-16} = Rs;
- let Inst{12-8} = Rt;
- let Inst{6-5} = Pu;
- let Inst{4-0} = Rd;
-}
-
-// Combines the two immediates into a double register.
-// Increase complexity to make it greater than any complexity of a combine
-// that involves a register.
-
-let isReMaterializable = 1, isMoveImm = 1, isAsCheapAsAMove = 1,
- isExtentSigned = 1, isExtendable = 1, opExtentBits = 8, opExtendable = 1,
- AddedComplexity = 75 in
-def A2_combineii: ALU32Inst <(outs DoubleRegs:$Rdd), (ins s8_0Ext:$s8, s8_0Imm:$S8),
- "$Rdd = combine(#$s8, #$S8)",
- []> {
- bits<5> Rdd;
- bits<8> s8;
- bits<8> S8;
-
- let IClass = 0b0111;
- let Inst{27-23} = 0b11000;
- let Inst{22-16} = S8{7-1};
- let Inst{13} = S8{0};
- let Inst{12-5} = s8;
- let Inst{4-0} = Rdd;
- }
-
-//===----------------------------------------------------------------------===//
-// Template class for predicated ADD of a reg and an Immediate value.
-//===----------------------------------------------------------------------===//
-let hasNewValue = 1, hasSideEffects = 0 in
-class T_Addri_Pred <bit PredNot, bit PredNew>
- : ALU32_ri <(outs IntRegs:$Rd),
- (ins PredRegs:$Pu, IntRegs:$Rs, s8_0Ext:$s8),
- !if(PredNot, "if (!$Pu", "if ($Pu")#!if(PredNew,".new) $Rd = ",
- ") $Rd = ")#"add($Rs, #$s8)"> {
- bits<5> Rd;
- bits<2> Pu;
- bits<5> Rs;
- bits<8> s8;
-
- let isPredicatedNew = PredNew;
- let IClass = 0b0111;
-
- let Inst{27-24} = 0b0100;
- let Inst{23} = PredNot;
- let Inst{22-21} = Pu;
- let Inst{20-16} = Rs;
- let Inst{13} = PredNew;
- let Inst{12-5} = s8;
- let Inst{4-0} = Rd;
- }
-
-//===----------------------------------------------------------------------===//
-// A2_addi: Add a signed immediate to a register.
-//===----------------------------------------------------------------------===//
-let hasNewValue = 1, hasSideEffects = 0 in
-class T_Addri <Operand immOp>
- : ALU32_ri <(outs IntRegs:$Rd),
- (ins IntRegs:$Rs, immOp:$s16),
- "$Rd = add($Rs, #$s16)", [], "", ALU32_ADDI_tc_1_SLOT0123> {
- let Type = TypeALU32_ADDI;
- bits<5> Rd;
- bits<5> Rs;
- bits<16> s16;
-
- let IClass = 0b1011;
-
- let Inst{27-21} = s16{15-9};
- let Inst{20-16} = Rs;
- let Inst{13-5} = s16{8-0};
- let Inst{4-0} = Rd;
- }
-
-//===----------------------------------------------------------------------===//
-// Multiclass for ADD of a register and an immediate value.
-//===----------------------------------------------------------------------===//
-multiclass Addri_Pred<string mnemonic, bit PredNot> {
- let isPredicatedFalse = PredNot in {
- def NAME : T_Addri_Pred<PredNot, 0>;
- // Predicate new
- def NAME#new : T_Addri_Pred<PredNot, 1>;
- }
-}
-
-let isExtendable = 1, isExtentSigned = 1, InputType = "imm" in
-multiclass Addri_base<string mnemonic, SDNode OpNode> {
- let CextOpcode = mnemonic, BaseOpcode = mnemonic#_ri in {
- let opExtendable = 2, opExtentBits = 16, isPredicable = 1, isAdd = 1 in
- def A2_#NAME : T_Addri<s16_0Ext>;
-
- let opExtendable = 3, opExtentBits = 8, isPredicated = 1 in {
- defm A2_p#NAME#t : Addri_Pred<mnemonic, 0>;
- defm A2_p#NAME#f : Addri_Pred<mnemonic, 1>;
- }
- }
-}
-
-defm addi : Addri_base<"add", add>, ImmRegRel, PredNewRel;
-
-let hasNewValue = 1, hasSideEffects = 0, isPseudo = 1 in
-def A2_iconst
- : ALU32_ri <(outs IntRegs:$Rd),
- (ins s23_2Imm:$s23_2),
- "$Rd = iconst(#$s23_2)"> {}
-
-//===----------------------------------------------------------------------===//
-// Template class used for the following ALU32 instructions.
-// Rd=and(Rs,#s10)
-// Rd=or(Rs,#s10)
-//===----------------------------------------------------------------------===//
-let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 10,
-InputType = "imm", hasNewValue = 1 in
-class T_ALU32ri_logical <string mnemonic, SDNode OpNode, bits<2> MinOp>
- : ALU32_ri <(outs IntRegs:$Rd),
- (ins IntRegs:$Rs, s10_0Ext:$s10),
- "$Rd = "#mnemonic#"($Rs, #$s10)" ,
- []> {
- bits<5> Rd;
- bits<5> Rs;
- bits<10> s10;
- let CextOpcode = mnemonic;
-
- let IClass = 0b0111;
-
- let Inst{27-24} = 0b0110;
- let Inst{23-22} = MinOp;
- let Inst{21} = s10{9};
- let Inst{20-16} = Rs;
- let Inst{13-5} = s10{8-0};
- let Inst{4-0} = Rd;
- }
-
-def A2_orir : T_ALU32ri_logical<"or", or, 0b10>, ImmRegRel;
-def A2_andir : T_ALU32ri_logical<"and", and, 0b00>, ImmRegRel;
-
-// Subtract register from immediate
-// Rd32=sub(#s10,Rs32)
-let isExtendable = 1, CextOpcode = "sub", opExtendable = 1, isExtentSigned = 1,
- opExtentBits = 10, InputType = "imm", hasNewValue = 1, hasSideEffects = 0 in
-def A2_subri: ALU32_ri <(outs IntRegs:$Rd), (ins s10_0Ext:$s10, IntRegs:$Rs),
- "$Rd = sub(#$s10, $Rs)", []>, ImmRegRel {
- bits<5> Rd;
- bits<10> s10;
- bits<5> Rs;
-
- let IClass = 0b0111;
-
- let Inst{27-22} = 0b011001;
- let Inst{21} = s10{9};
- let Inst{20-16} = Rs;
- let Inst{13-5} = s10{8-0};
- let Inst{4-0} = Rd;
- }
-
-// Nop.
-let hasSideEffects = 0 in
-def A2_nop: ALU32Inst <(outs), (ins), "nop" > {
- let IClass = 0b0111;
- let Inst{27-24} = 0b1111;
-}
-
-let hasSideEffects = 0, hasNewValue = 1 in
-class T_tfr16<bit isHi>
- : ALU32Inst <(outs IntRegs:$Rx), (ins IntRegs:$src1, u16_0Imm:$u16),
- "$Rx"#!if(isHi, ".h", ".l")#" = #$u16",
- [], "$src1 = $Rx" > {
- bits<5> Rx;
- bits<16> u16;
-
- let IClass = 0b0111;
- let Inst{27-26} = 0b00;
- let Inst{25-24} = !if(isHi, 0b10, 0b01);
- let Inst{23-22} = u16{15-14};
- let Inst{21} = 0b1;
- let Inst{20-16} = Rx;
- let Inst{13-0} = u16{13-0};
- }
-
-def A2_tfril: T_tfr16<0>;
-def A2_tfrih: T_tfr16<1>;
-
-// Conditional transfer is an alias to conditional "Rd = add(Rs, #0)".
-let isPredicated = 1, hasNewValue = 1, isCodeGenOnly = 1, opNewValue = 0,
- isPseudo = 1 in
-class T_tfr_pred<bit isPredNot, bit isPredNew>
- : ALU32Inst<(outs IntRegs:$dst),
- (ins PredRegs:$src1, IntRegs:$src2),
- ""> {
- bits<5> dst;
- bits<2> src1;
- bits<5> src2;
-
- let isPredicatedFalse = isPredNot;
- let isPredicatedNew = isPredNew;
- let IClass = 0b0111;
-
- let Inst{27-24} = 0b0100;
- let Inst{23} = isPredNot;
- let Inst{13} = isPredNew;
- let Inst{12-5} = 0;
- let Inst{4-0} = dst;
- let Inst{22-21} = src1;
- let Inst{20-16} = src2;
- }
-
-let isPredicable = 1 in
-class T_tfr : ALU32Inst<(outs IntRegs:$dst), (ins IntRegs:$src),
- "$dst = $src"> {
- bits<5> dst;
- bits<5> src;
-
- let IClass = 0b0111;
-
- let Inst{27-21} = 0b0000011;
- let Inst{20-16} = src;
- let Inst{13} = 0b0;
- let Inst{4-0} = dst;
- }
-
-let InputType = "reg", hasNewValue = 1, hasSideEffects = 0 in
-multiclass tfr_base<string CextOp> {
- let CextOpcode = CextOp, BaseOpcode = CextOp in {
- def NAME : T_tfr;
-
- // Predicate
- def t : T_tfr_pred<0, 0>;
- def f : T_tfr_pred<1, 0>;
- // Predicate new
- def tnew : T_tfr_pred<0, 1>;
- def fnew : T_tfr_pred<1, 1>;
- }
-}
-
-// Assembler mapped to C2_ccombinew[t|f|newt|newf].
-// Please don't add bits to this instruction as it'll be converted into
-// 'combine' before object code emission.
-let isPredicated = 1 in
-class T_tfrp_pred<bit PredNot, bit PredNew>
- : ALU32_rr <(outs DoubleRegs:$dst),
- (ins PredRegs:$src1, DoubleRegs:$src2),
- "if ("#!if(PredNot, "!", "")#"$src1"
- #!if(PredNew, ".new", "")#") $dst = $src2" > {
- let isPredicatedFalse = PredNot;
- let isPredicatedNew = PredNew;
- }
-
-// Assembler mapped to A2_combinew.
-// Please don't add bits to this instruction as it'll be converted into
-// 'combine' before object code emission.
-class T_tfrp : ALU32Inst <(outs DoubleRegs:$dst),
- (ins DoubleRegs:$src),
- "$dst = $src">;
-
-let hasSideEffects = 0 in
-multiclass TFR64_base<string BaseName> {
- let BaseOpcode = BaseName in {
- let isPredicable = 1 in
- def NAME : T_tfrp;
- // Predicate
- def t : T_tfrp_pred <0, 0>;
- def f : T_tfrp_pred <1, 0>;
- // Predicate new
- def tnew : T_tfrp_pred <0, 1>;
- def fnew : T_tfrp_pred <1, 1>;
- }
-}
-
-def A2_tfrfAlias : InstAlias<"if (!$Pu4) $Rd32=$Rs32", (A2_paddif IntRegs:$Rd32, PredRegs:$Pu4, IntRegs:$Rs32, 0)>;
-def A2_tfrfnewAlias : InstAlias<"if (!$Pu4.new) $Rd32=$Rs32", (A2_paddifnew IntRegs:$Rd32, PredRegs:$Pu4, IntRegs:$Rs32, 0)>;
-def A2_tfrtAlias : InstAlias<"if ($Pu4) $Rd32=$Rs32", (A2_paddit IntRegs:$Rd32, PredRegs:$Pu4, IntRegs:$Rs32, 0)>;
-def A2_tfrtnewAlias : InstAlias<"if ($Pu4.new) $Rd32=$Rs32", (A2_padditnew IntRegs:$Rd32, PredRegs:$Pu4, IntRegs:$Rs32, 0)>;
-
-let InputType = "imm", isExtendable = 1, isExtentSigned = 1, opExtentBits = 12,
- isMoveImm = 1, opExtendable = 2, BaseOpcode = "TFRI", CextOpcode = "TFR",
- hasSideEffects = 0, isPredicated = 1, hasNewValue = 1 in
-class T_TFRI_Pred<bit PredNot, bit PredNew>
- : ALU32_ri<(outs IntRegs:$Rd), (ins PredRegs:$Pu, s12_0Ext:$s12),
- "if ("#!if(PredNot,"!","")#"$Pu"#!if(PredNew,".new","")#") $Rd = #$s12",
- [], "", ALU32_2op_tc_1_SLOT0123>, ImmRegRel, PredNewRel {
- let isPredicatedFalse = PredNot;
- let isPredicatedNew = PredNew;
-
- bits<5> Rd;
- bits<2> Pu;
- bits<12> s12;
-
- let IClass = 0b0111;
- let Inst{27-24} = 0b1110;
- let Inst{23} = PredNot;
- let Inst{22-21} = Pu;
- let Inst{20} = 0b0;
- let Inst{19-16,12-5} = s12;
- let Inst{13} = PredNew;
- let Inst{4-0} = Rd;
-}
-
-def C2_cmoveit : T_TFRI_Pred<0, 0>;
-def C2_cmoveif : T_TFRI_Pred<1, 0>;
-def C2_cmovenewit : T_TFRI_Pred<0, 1>;
-def C2_cmovenewif : T_TFRI_Pred<1, 1>;
-
-let InputType = "imm", isExtendable = 1, isExtentSigned = 1,
- CextOpcode = "TFR", BaseOpcode = "TFRI", hasNewValue = 1, opNewValue = 0,
- isAsCheapAsAMove = 1 , opExtendable = 1, opExtentBits = 16, isMoveImm = 1,
- isPredicated = 0, isPredicable = 1, isReMaterializable = 1 in
-def A2_tfrsi : ALU32Inst<(outs IntRegs:$Rd), (ins s16_0Ext:$s16), "$Rd = #$s16",
- [], "", ALU32_2op_tc_1_SLOT0123>,
- ImmRegRel, PredRel {
- bits<5> Rd;
- bits<16> s16;
-
- let IClass = 0b0111;
- let Inst{27-24} = 0b1000;
- let Inst{23-22,20-16,13-5} = s16;
- let Inst{4-0} = Rd;
-}
-
-defm A2_tfr : tfr_base<"TFR">, ImmRegRel, PredNewRel;
-let isAsmParserOnly = 1 in
-defm A2_tfrp : TFR64_base<"TFR64">, PredNewRel;
-
-// Assembler mapped
-let isReMaterializable = 1, isMoveImm = 1, isAsCheapAsAMove = 1,
- isAsmParserOnly = 1 in
-def A2_tfrpi : ALU64_rr<(outs DoubleRegs:$dst), (ins s8_0Imm64:$src1),
- "$dst = #$src1",
- []>;
-
-// TODO: see if this instruction can be deleted..
-let isExtendable = 1, opExtendable = 1, opExtentBits = 6,
- isAsmParserOnly = 1 in {
-def TFRI64_V4 : ALU64_rr<(outs DoubleRegs:$dst), (ins u64_0Imm:$src1),
- "$dst = #$src1">;
-def TFRI64_V2_ext : ALU64_rr<(outs DoubleRegs:$dst),
- (ins s8_0Ext:$src1, s8_0Imm:$src2),
- "$dst = combine(##$src1, #$src2)">;
-}
-
-//===----------------------------------------------------------------------===//
-// ALU32/ALU -
-//===----------------------------------------------------------------------===//
-
-
-//===----------------------------------------------------------------------===//
-// ALU32/PERM +
-//===----------------------------------------------------------------------===//
-// Scalar mux register immediate.
-let hasSideEffects = 0, isExtentSigned = 1, CextOpcode = "MUX",
- InputType = "imm", hasNewValue = 1, isExtendable = 1, opExtentBits = 8 in
-class T_MUX1 <bit MajOp, dag ins, string AsmStr>
- : ALU32Inst <(outs IntRegs:$Rd), ins, AsmStr>, ImmRegRel {
- bits<5> Rd;
- bits<2> Pu;
- bits<8> s8;
- bits<5> Rs;
-
- let IClass = 0b0111;
- let Inst{27-24} = 0b0011;
- let Inst{23} = MajOp;
- let Inst{22-21} = Pu;
- let Inst{20-16} = Rs;
- let Inst{13} = 0b0;
- let Inst{12-5} = s8;
- let Inst{4-0} = Rd;
-}
-
-let opExtendable = 2 in
-def C2_muxri : T_MUX1<0b1, (ins PredRegs:$Pu, s8_0Ext:$s8, IntRegs:$Rs),
- "$Rd = mux($Pu, #$s8, $Rs)">;
-
-let opExtendable = 3 in
-def C2_muxir : T_MUX1<0b0, (ins PredRegs:$Pu, IntRegs:$Rs, s8_0Ext:$s8),
- "$Rd = mux($Pu, $Rs, #$s8)">;
-
-// C2_muxii: Scalar mux immediates.
-let isExtentSigned = 1, hasNewValue = 1, isExtendable = 1,
- opExtentBits = 8, opExtendable = 2 in
-def C2_muxii: ALU32Inst <(outs IntRegs:$Rd),
- (ins PredRegs:$Pu, s8_0Ext:$s8, s8_0Imm:$S8),
- "$Rd = mux($Pu, #$s8, #$S8)" ,
- []> {
- bits<5> Rd;
- bits<2> Pu;
- bits<8> s8;
- bits<8> S8;
-
- let IClass = 0b0111;
-
- let Inst{27-25} = 0b101;
- let Inst{24-23} = Pu;
- let Inst{22-16} = S8{7-1};
- let Inst{13} = S8{0};
- let Inst{12-5} = s8;
- let Inst{4-0} = Rd;
- }
-
-let isCodeGenOnly = 1, isPseudo = 1 in
-def PS_pselect : ALU64_rr<(outs DoubleRegs:$Rd),
- (ins PredRegs:$Pu, DoubleRegs:$Rs, DoubleRegs:$Rt),
- ".error \"should not emit\" ", []>;
-
-
-//===----------------------------------------------------------------------===//
-// template class for non-predicated alu32_2op instructions
-// - aslh, asrh, sxtb, sxth, zxth
-//===----------------------------------------------------------------------===//
-let hasNewValue = 1, opNewValue = 0 in
-class T_ALU32_2op <string mnemonic, bits<3> minOp> :
- ALU32Inst <(outs IntRegs:$Rd), (ins IntRegs:$Rs),
- "$Rd = "#mnemonic#"($Rs)", [] > {
- bits<5> Rd;
- bits<5> Rs;
-
- let IClass = 0b0111;
-
- let Inst{27-24} = 0b0000;
- let Inst{23-21} = minOp;
- let Inst{13} = 0b0;
- let Inst{4-0} = Rd;
- let Inst{20-16} = Rs;
-}
-
-//===----------------------------------------------------------------------===//
-// template class for predicated alu32_2op instructions
-// - aslh, asrh, sxtb, sxth, zxtb, zxth
-//===----------------------------------------------------------------------===//
-let hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
-class T_ALU32_2op_Pred <string mnemonic, bits<3> minOp, bit isPredNot,
- bit isPredNew > :
- ALU32Inst <(outs IntRegs:$Rd), (ins PredRegs:$Pu, IntRegs:$Rs),
- !if(isPredNot, "if (!$Pu", "if ($Pu")
- #!if(isPredNew, ".new) ",") ")#"$Rd = "#mnemonic#"($Rs)"> {
- bits<5> Rd;
- bits<2> Pu;
- bits<5> Rs;
-
- let IClass = 0b0111;
-
- let Inst{27-24} = 0b0000;
- let Inst{23-21} = minOp;
- let Inst{13} = 0b1;
- let Inst{11} = isPredNot;
- let Inst{10} = isPredNew;
- let Inst{4-0} = Rd;
- let Inst{9-8} = Pu;
- let Inst{20-16} = Rs;
-}
-
-multiclass ALU32_2op_Pred<string mnemonic, bits<3> minOp, bit PredNot> {
- let isPredicatedFalse = PredNot in {
- def NAME : T_ALU32_2op_Pred<mnemonic, minOp, PredNot, 0>;
-
- // Predicate new
- let isPredicatedNew = 1 in
- def NAME#new : T_ALU32_2op_Pred<mnemonic, minOp, PredNot, 1>;
- }
-}
-
-multiclass ALU32_2op_base<string mnemonic, bits<3> minOp> {
- let BaseOpcode = mnemonic in {
- let isPredicable = 1, hasSideEffects = 0 in
- def A2_#NAME : T_ALU32_2op<mnemonic, minOp>;
-
- let isPredicated = 1, hasSideEffects = 0 in {
- defm A4_p#NAME#t : ALU32_2op_Pred<mnemonic, minOp, 0>;
- defm A4_p#NAME#f : ALU32_2op_Pred<mnemonic, minOp, 1>;
- }
- }
-}
-
-defm aslh : ALU32_2op_base<"aslh", 0b000>, PredNewRel;
-defm asrh : ALU32_2op_base<"asrh", 0b001>, PredNewRel;
-defm sxtb : ALU32_2op_base<"sxtb", 0b101>, PredNewRel;
-defm sxth : ALU32_2op_base<"sxth", 0b111>, PredNewRel;
-defm zxth : ALU32_2op_base<"zxth", 0b110>, PredNewRel;
-
-// Rd=zxtb(Rs): assembler mapped to Rd=and(Rs,#255).
-// Compiler would want to generate 'zxtb' instead of 'and' because 'zxtb' has
-// predicated forms while 'and' doesn't. Since integrated assembler can't
-// handle 'mapped' instructions, we need to encode 'zxtb' same as 'and' where
-// immediate operand is set to '255'.
-
-let hasNewValue = 1, opNewValue = 0, isPseudo = 1, isCodeGenOnly = 1 in
-class T_ZXTB: ALU32Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rs),
- "$Rd=zxtb($Rs)", [] >;
-
-//Rd=zxtb(Rs): assembler mapped to "Rd=and(Rs,#255)
-multiclass ZXTB_base <string mnemonic, bits<3> minOp> {
- let BaseOpcode = mnemonic in {
- let isPredicable = 1, hasSideEffects = 0 in
- def A2_#NAME : T_ZXTB;
-
- let isPredicated = 1, hasSideEffects = 0 in {
- defm A4_p#NAME#t : ALU32_2op_Pred<mnemonic, minOp, 0>;
- defm A4_p#NAME#f : ALU32_2op_Pred<mnemonic, minOp, 1>;
- }
- }
-}
-
-defm zxtb : ZXTB_base<"zxtb",0b100>, PredNewRel;
-
-//===----------------------------------------------------------------------===//
-// Template class for vector add and avg
-//===----------------------------------------------------------------------===//
-
-class T_VectALU_64 <string opc, bits<3> majOp, bits<3> minOp,
- bit isSat, bit isRnd, bit isCrnd, bit SwapOps >
- : ALU64_rr < (outs DoubleRegs:$Rdd),
- (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
- "$Rdd = "#opc#"($Rss, $Rtt)"#!if(isRnd, ":rnd", "")
- #!if(isCrnd,":crnd","")
- #!if(isSat, ":sat", ""),
- [], "", ALU64_tc_2_SLOT23 > {
- bits<5> Rdd;
- bits<5> Rss;
- bits<5> Rtt;
-
- let IClass = 0b1101;
-
- let Inst{27-24} = 0b0011;
- let Inst{23-21} = majOp;
- let Inst{20-16} = !if (SwapOps, Rtt, Rss);
- let Inst{12-8} = !if (SwapOps, Rss, Rtt);
- let Inst{7-5} = minOp;
- let Inst{4-0} = Rdd;
- }
-
-// ALU64 - Vector add
-// Rdd=vadd[u][bhw](Rss,Rtt)
-let Itinerary = ALU64_tc_1_SLOT23 in {
- def A2_vaddub : T_VectALU_64 < "vaddub", 0b000, 0b000, 0, 0, 0, 0>;
- def A2_vaddh : T_VectALU_64 < "vaddh", 0b000, 0b010, 0, 0, 0, 0>;
- def A2_vaddw : T_VectALU_64 < "vaddw", 0b000, 0b101, 0, 0, 0, 0>;
-}
-
-// Rdd=vadd[u][bhw](Rss,Rtt):sat
-let Defs = [USR_OVF] in {
- def A2_vaddubs : T_VectALU_64 < "vaddub", 0b000, 0b001, 1, 0, 0, 0>;
- def A2_vaddhs : T_VectALU_64 < "vaddh", 0b000, 0b011, 1, 0, 0, 0>;
- def A2_vadduhs : T_VectALU_64 < "vadduh", 0b000, 0b100, 1, 0, 0, 0>;
- def A2_vaddws : T_VectALU_64 < "vaddw", 0b000, 0b110, 1, 0, 0, 0>;
-}
-
-// ALU64 - Vector average
-// Rdd=vavg[u][bhw](Rss,Rtt)
-let Itinerary = ALU64_tc_1_SLOT23 in {
- def A2_vavgub : T_VectALU_64 < "vavgub", 0b010, 0b000, 0, 0, 0, 0>;
- def A2_vavgh : T_VectALU_64 < "vavgh", 0b010, 0b010, 0, 0, 0, 0>;
- def A2_vavguh : T_VectALU_64 < "vavguh", 0b010, 0b101, 0, 0, 0, 0>;
- def A2_vavgw : T_VectALU_64 < "vavgw", 0b011, 0b000, 0, 0, 0, 0>;
- def A2_vavguw : T_VectALU_64 < "vavguw", 0b011, 0b011, 0, 0, 0, 0>;
-}
-
-// Rdd=vavg[u][bhw](Rss,Rtt)[:rnd|:crnd]
-def A2_vavgubr : T_VectALU_64 < "vavgub", 0b010, 0b001, 0, 1, 0, 0>;
-def A2_vavghr : T_VectALU_64 < "vavgh", 0b010, 0b011, 0, 1, 0, 0>;
-def A2_vavghcr : T_VectALU_64 < "vavgh", 0b010, 0b100, 0, 0, 1, 0>;
-def A2_vavguhr : T_VectALU_64 < "vavguh", 0b010, 0b110, 0, 1, 0, 0>;
-
-def A2_vavgwr : T_VectALU_64 < "vavgw", 0b011, 0b001, 0, 1, 0, 0>;
-def A2_vavgwcr : T_VectALU_64 < "vavgw", 0b011, 0b010, 0, 0, 1, 0>;
-def A2_vavguwr : T_VectALU_64 < "vavguw", 0b011, 0b100, 0, 1, 0, 0>;
-
-// Rdd=vnavg[bh](Rss,Rtt)
-let Itinerary = ALU64_tc_1_SLOT23 in {
- def A2_vnavgh : T_VectALU_64 < "vnavgh", 0b100, 0b000, 0, 0, 0, 1>;
- def A2_vnavgw : T_VectALU_64 < "vnavgw", 0b100, 0b011, 0, 0, 0, 1>;
-}
-
-// Rdd=vnavg[bh](Rss,Rtt)[:rnd|:crnd]:sat
-let Defs = [USR_OVF] in {
- def A2_vnavghr : T_VectALU_64 < "vnavgh", 0b100, 0b001, 1, 1, 0, 1>;
- def A2_vnavghcr : T_VectALU_64 < "vnavgh", 0b100, 0b010, 1, 0, 1, 1>;
- def A2_vnavgwr : T_VectALU_64 < "vnavgw", 0b100, 0b100, 1, 1, 0, 1>;
- def A2_vnavgwcr : T_VectALU_64 < "vnavgw", 0b100, 0b110, 1, 0, 1, 1>;
-}
-
-// Rdd=vsub[u][bh](Rss,Rtt)
-let Itinerary = ALU64_tc_1_SLOT23 in {
- def A2_vsubub : T_VectALU_64 < "vsubub", 0b001, 0b000, 0, 0, 0, 1>;
- def A2_vsubh : T_VectALU_64 < "vsubh", 0b001, 0b010, 0, 0, 0, 1>;
- def A2_vsubw : T_VectALU_64 < "vsubw", 0b001, 0b101, 0, 0, 0, 1>;
-}
-
-// Rdd=vsub[u][bh](Rss,Rtt):sat
-let Defs = [USR_OVF] in {
- def A2_vsububs : T_VectALU_64 < "vsubub", 0b001, 0b001, 1, 0, 0, 1>;
- def A2_vsubhs : T_VectALU_64 < "vsubh", 0b001, 0b011, 1, 0, 0, 1>;
- def A2_vsubuhs : T_VectALU_64 < "vsubuh", 0b001, 0b100, 1, 0, 0, 1>;
- def A2_vsubws : T_VectALU_64 < "vsubw", 0b001, 0b110, 1, 0, 0, 1>;
-}
-
-// Rdd=vmax[u][bhw](Rss,Rtt)
-def A2_vmaxb : T_VectALU_64 < "vmaxb", 0b110, 0b110, 0, 0, 0, 1>;
-def A2_vmaxub : T_VectALU_64 < "vmaxub", 0b110, 0b000, 0, 0, 0, 1>;
-def A2_vmaxh : T_VectALU_64 < "vmaxh", 0b110, 0b001, 0, 0, 0, 1>;
-def A2_vmaxuh : T_VectALU_64 < "vmaxuh", 0b110, 0b010, 0, 0, 0, 1>;
-def A2_vmaxw : T_VectALU_64 < "vmaxw", 0b110, 0b011, 0, 0, 0, 1>;
-def A2_vmaxuw : T_VectALU_64 < "vmaxuw", 0b101, 0b101, 0, 0, 0, 1>;
-
-// Rdd=vmin[u][bhw](Rss,Rtt)
-def A2_vminb : T_VectALU_64 < "vminb", 0b110, 0b111, 0, 0, 0, 1>;
-def A2_vminub : T_VectALU_64 < "vminub", 0b101, 0b000, 0, 0, 0, 1>;
-def A2_vminh : T_VectALU_64 < "vminh", 0b101, 0b001, 0, 0, 0, 1>;
-def A2_vminuh : T_VectALU_64 < "vminuh", 0b101, 0b010, 0, 0, 0, 1>;
-def A2_vminw : T_VectALU_64 < "vminw", 0b101, 0b011, 0, 0, 0, 1>;
-def A2_vminuw : T_VectALU_64 < "vminuw", 0b101, 0b100, 0, 0, 0, 1>;
-
-//===----------------------------------------------------------------------===//
-// Template class for vector compare
-//===----------------------------------------------------------------------===//
-let hasSideEffects = 0 in
-class T_vcmp <string Str, bits<4> minOp>
- : ALU64_rr <(outs PredRegs:$Pd),
- (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
- "$Pd = "#Str#"($Rss, $Rtt)", [],
- "", ALU64_tc_2early_SLOT23> {
- bits<2> Pd;
- bits<5> Rss;
- bits<5> Rtt;
-
- let IClass = 0b1101;
-
- let Inst{27-23} = 0b00100;
- let Inst{13} = minOp{3};
- let Inst{7-5} = minOp{2-0};
- let Inst{1-0} = Pd;
- let Inst{20-16} = Rss;
- let Inst{12-8} = Rtt;
- }
-
-// Vector compare bytes
-def A2_vcmpbeq : T_vcmp <"vcmpb.eq", 0b0110>;
-def A2_vcmpbgtu : T_vcmp <"vcmpb.gtu", 0b0111>;
-
-// Vector compare halfwords
-def A2_vcmpheq : T_vcmp <"vcmph.eq", 0b0011>;
-def A2_vcmphgt : T_vcmp <"vcmph.gt", 0b0100>;
-def A2_vcmphgtu : T_vcmp <"vcmph.gtu", 0b0101>;
-
-// Vector compare words
-def A2_vcmpweq : T_vcmp <"vcmpw.eq", 0b0000>;
-def A2_vcmpwgt : T_vcmp <"vcmpw.gt", 0b0001>;
-def A2_vcmpwgtu : T_vcmp <"vcmpw.gtu", 0b0010>;
-
-//===----------------------------------------------------------------------===//
-// ALU32/PERM -
-//===----------------------------------------------------------------------===//
-
-
-//===----------------------------------------------------------------------===//
-// ALU32/PRED +
-//===----------------------------------------------------------------------===//
-// No bits needed. If cmp.ge is found the assembler parser will
-// transform it to cmp.gt subtracting 1 from the immediate.
-let isPseudo = 1 in {
-def C2_cmpgei: ALU32Inst <
- (outs PredRegs:$Pd), (ins IntRegs:$Rs, s8_0Ext:$s8),
- "$Pd = cmp.ge($Rs, #$s8)">;
-def C2_cmpgeui: ALU32Inst <
- (outs PredRegs:$Pd), (ins IntRegs:$Rs, u8_0Ext:$s8),
- "$Pd = cmp.geu($Rs, #$s8)">;
-}
-
-
-//===----------------------------------------------------------------------===//
-// ALU32/PRED -
-//===----------------------------------------------------------------------===//
-
-
-//===----------------------------------------------------------------------===//
-// ALU64/ALU +
-//===----------------------------------------------------------------------===//
-// Add.
-//===----------------------------------------------------------------------===//
-// Template Class
-// Add/Subtract halfword
-// Rd=add(Rt.L,Rs.[HL])[:sat]
-// Rd=sub(Rt.L,Rs.[HL])[:sat]
-// Rd=add(Rt.[LH],Rs.[HL])[:sat][:<16]
-// Rd=sub(Rt.[LH],Rs.[HL])[:sat][:<16]
-//===----------------------------------------------------------------------===//
-
-let hasNewValue = 1, opNewValue = 0 in
-class T_XTYPE_ADD_SUB <bits<2> LHbits, bit isSat, bit hasShift, bit isSub>
- : ALU64Inst <(outs IntRegs:$Rd), (ins IntRegs:$Rt, IntRegs:$Rs),
- "$Rd = "#!if(isSub,"sub","add")#"($Rt."
- #!if(hasShift, !if(LHbits{1},"h","l"),"l") #", $Rs."
- #!if(hasShift, !if(LHbits{0},"h)","l)"), !if(LHbits{1},"h)","l)"))
- #!if(isSat,":sat","")
- #!if(hasShift,":<<16",""), [], "", ALU64_tc_1_SLOT23> {
- bits<5> Rd;
- bits<5> Rt;
- bits<5> Rs;
- let IClass = 0b1101;
-
- let Inst{27-23} = 0b01010;
- let Inst{22} = hasShift;
- let Inst{21} = isSub;
- let Inst{7} = isSat;
- let Inst{6-5} = LHbits;
- let Inst{4-0} = Rd;
- let Inst{12-8} = Rt;
- let Inst{20-16} = Rs;
- }
-
-//Rd=sub(Rt.L,Rs.[LH])
-def A2_subh_l16_ll : T_XTYPE_ADD_SUB <0b00, 0, 0, 1>;
-def A2_subh_l16_hl : T_XTYPE_ADD_SUB <0b10, 0, 0, 1>;
-
-//Rd=add(Rt.L,Rs.[LH])
-def A2_addh_l16_ll : T_XTYPE_ADD_SUB <0b00, 0, 0, 0>;
-def A2_addh_l16_hl : T_XTYPE_ADD_SUB <0b10, 0, 0, 0>;
-
-let Itinerary = ALU64_tc_2_SLOT23, Defs = [USR_OVF] in {
- //Rd=sub(Rt.L,Rs.[LH]):sat
- def A2_subh_l16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 0, 1>;
- def A2_subh_l16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 0, 1>;
-
- //Rd=add(Rt.L,Rs.[LH]):sat
- def A2_addh_l16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 0, 0>;
- def A2_addh_l16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 0, 0>;
-}
-
-//Rd=sub(Rt.[LH],Rs.[LH]):<<16
-def A2_subh_h16_ll : T_XTYPE_ADD_SUB <0b00, 0, 1, 1>;
-def A2_subh_h16_lh : T_XTYPE_ADD_SUB <0b01, 0, 1, 1>;
-def A2_subh_h16_hl : T_XTYPE_ADD_SUB <0b10, 0, 1, 1>;
-def A2_subh_h16_hh : T_XTYPE_ADD_SUB <0b11, 0, 1, 1>;
-
-//Rd=add(Rt.[LH],Rs.[LH]):<<16
-def A2_addh_h16_ll : T_XTYPE_ADD_SUB <0b00, 0, 1, 0>;
-def A2_addh_h16_lh : T_XTYPE_ADD_SUB <0b01, 0, 1, 0>;
-def A2_addh_h16_hl : T_XTYPE_ADD_SUB <0b10, 0, 1, 0>;
-def A2_addh_h16_hh : T_XTYPE_ADD_SUB <0b11, 0, 1, 0>;
-
-let Itinerary = ALU64_tc_2_SLOT23, Defs = [USR_OVF] in {
- //Rd=sub(Rt.[LH],Rs.[LH]):sat:<<16
- def A2_subh_h16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 1, 1>;
- def A2_subh_h16_sat_lh : T_XTYPE_ADD_SUB <0b01, 1, 1, 1>;
- def A2_subh_h16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 1, 1>;
- def A2_subh_h16_sat_hh : T_XTYPE_ADD_SUB <0b11, 1, 1, 1>;
-
- //Rd=add(Rt.[LH],Rs.[LH]):sat:<<16
- def A2_addh_h16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 1, 0>;
- def A2_addh_h16_sat_lh : T_XTYPE_ADD_SUB <0b01, 1, 1, 0>;
- def A2_addh_h16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 1, 0>;
- def A2_addh_h16_sat_hh : T_XTYPE_ADD_SUB <0b11, 1, 1, 0>;
-}
-
-let hasSideEffects = 0, hasNewValue = 1 in
-def S2_parityp: ALU64Inst<(outs IntRegs:$Rd),
- (ins DoubleRegs:$Rs, DoubleRegs:$Rt),
- "$Rd = parity($Rs, $Rt)", [], "", ALU64_tc_2_SLOT23> {
- bits<5> Rd;
- bits<5> Rs;
- bits<5> Rt;
-
- let IClass = 0b1101;
- let Inst{27-24} = 0b0000;
- let Inst{20-16} = Rs;
- let Inst{12-8} = Rt;
- let Inst{4-0} = Rd;
-}
-
-let hasNewValue = 1, opNewValue = 0, hasSideEffects = 0 in
-class T_XTYPE_MIN_MAX < bit isMax, bit isUnsigned >
- : ALU64Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rt, IntRegs:$Rs),
- "$Rd = "#!if(isMax,"max","min")#!if(isUnsigned,"u","")
- #"($Rt, $Rs)", [], "", ALU64_tc_2_SLOT23> {
- bits<5> Rd;
- bits<5> Rt;
- bits<5> Rs;
-
- let IClass = 0b1101;
-
- let Inst{27-23} = 0b01011;
- let Inst{22-21} = !if(isMax, 0b10, 0b01);
- let Inst{7} = isUnsigned;
- let Inst{4-0} = Rd;
- let Inst{12-8} = !if(isMax, Rs, Rt);
- let Inst{20-16} = !if(isMax, Rt, Rs);
- }
-
-def A2_min : T_XTYPE_MIN_MAX < 0, 0 >;
-def A2_minu : T_XTYPE_MIN_MAX < 0, 1 >;
-def A2_max : T_XTYPE_MIN_MAX < 1, 0 >;
-def A2_maxu : T_XTYPE_MIN_MAX < 1, 1 >;
-
-class T_cmp64_rr<string mnemonic, bits<3> MinOp, bit IsComm>
- : ALU64_rr<(outs PredRegs:$Pd), (ins DoubleRegs:$Rs, DoubleRegs:$Rt),
- "$Pd = "#mnemonic#"($Rs, $Rt)", [], "", ALU64_tc_2early_SLOT23> {
- let isCompare = 1;
- let isCommutable = IsComm;
- let hasSideEffects = 0;
-
- bits<2> Pd;
- bits<5> Rs;
- bits<5> Rt;
-
- let IClass = 0b1101;
- let Inst{27-21} = 0b0010100;
- let Inst{20-16} = Rs;
- let Inst{12-8} = Rt;
- let Inst{7-5} = MinOp;
- let Inst{1-0} = Pd;
-}
-
-def C2_cmpeqp : T_cmp64_rr<"cmp.eq", 0b000, 1>;
-def C2_cmpgtp : T_cmp64_rr<"cmp.gt", 0b010, 0>;
-def C2_cmpgtup : T_cmp64_rr<"cmp.gtu", 0b100, 0>;
-
-def C2_vmux : ALU64_rr<(outs DoubleRegs:$Rd),
- (ins PredRegs:$Pu, DoubleRegs:$Rs, DoubleRegs:$Rt),
- "$Rd = vmux($Pu, $Rs, $Rt)", [], "", ALU64_tc_1_SLOT23> {
- let hasSideEffects = 0;
-
- bits<5> Rd;
- bits<2> Pu;
- bits<5> Rs;
- bits<5> Rt;
-
- let IClass = 0b1101;
- let Inst{27-24} = 0b0001;
- let Inst{20-16} = Rs;
- let Inst{12-8} = Rt;
- let Inst{6-5} = Pu;
- let Inst{4-0} = Rd;
-}
-
-class T_ALU64_rr<string mnemonic, string suffix, bits<4> RegType,
- bits<3> MajOp, bits<3> MinOp, bit OpsRev, bit IsComm,
- string Op2Pfx>
- : ALU64_rr<(outs DoubleRegs:$Rd), (ins DoubleRegs:$Rs, DoubleRegs:$Rt),
- "$Rd = " #mnemonic# "($Rs, " #Op2Pfx# "$Rt)" #suffix, [],
- "", ALU64_tc_1_SLOT23> {
- let hasSideEffects = 0;
- let isCommutable = IsComm;
-
- bits<5> Rs;
- bits<5> Rt;
- bits<5> Rd;
-
- let IClass = 0b1101;
- let Inst{27-24} = RegType;
- let Inst{23-21} = MajOp;
- let Inst{20-16} = !if (OpsRev,Rt,Rs);
- let Inst{12-8} = !if (OpsRev,Rs,Rt);
- let Inst{7-5} = MinOp;
- let Inst{4-0} = Rd;
-}
-
-class T_ALU64_arith<string mnemonic, bits<3> MajOp, bits<3> MinOp, bit IsSat,
- bit OpsRev, bit IsComm>
- : T_ALU64_rr<mnemonic, !if(IsSat,":sat",""), 0b0011, MajOp, MinOp, OpsRev,
- IsComm, "">;
-
-let isAdd = 1 in
-def A2_addp : T_ALU64_arith<"add", 0b000, 0b111, 0, 0, 1>;
-def A2_subp : T_ALU64_arith<"sub", 0b001, 0b111, 0, 1, 0>;
-
-class T_ALU64_logical<string mnemonic, bits<3> MinOp, bit OpsRev, bit IsComm,
- bit IsNeg>
- : T_ALU64_rr<mnemonic, "", 0b0011, 0b111, MinOp, OpsRev, IsComm,
- !if(IsNeg,"~","")>;
-
-def A2_andp : T_ALU64_logical<"and", 0b000, 0, 1, 0>;
-def A2_orp : T_ALU64_logical<"or", 0b010, 0, 1, 0>;
-def A2_xorp : T_ALU64_logical<"xor", 0b100, 0, 1, 0>;
-
-//===----------------------------------------------------------------------===//
-// ALU64/ALU -
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// ALU64/BIT +
-//===----------------------------------------------------------------------===//
-//
-//===----------------------------------------------------------------------===//
-// ALU64/BIT -
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// ALU64/PERM +
-//===----------------------------------------------------------------------===//
-//
-//===----------------------------------------------------------------------===//
-// ALU64/PERM -
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// CR +
-//===----------------------------------------------------------------------===//
-// Logical reductions on predicates.
-
-// Looping instructions.
-
-// Pipelined looping instructions.
-
-// Logical operations on predicates.
-let hasSideEffects = 0 in
-class T_LOGICAL_1OP<string MnOp, bits<2> OpBits>
- : CRInst<(outs PredRegs:$Pd), (ins PredRegs:$Ps),
- "$Pd = " # MnOp # "($Ps)", [], "", CR_tc_2early_SLOT23> {
- bits<2> Pd;
- bits<2> Ps;
-
- let IClass = 0b0110;
- let Inst{27-23} = 0b10111;
- let Inst{22-21} = OpBits;
- let Inst{20} = 0b0;
- let Inst{17-16} = Ps;
- let Inst{13} = 0b0;
- let Inst{1-0} = Pd;
-}
-
-def C2_any8 : T_LOGICAL_1OP<"any8", 0b00>;
-def C2_all8 : T_LOGICAL_1OP<"all8", 0b01>;
-def C2_not : T_LOGICAL_1OP<"not", 0b10>;
-
-let hasSideEffects = 0 in
-class T_LOGICAL_2OP<string MnOp, bits<3> OpBits, bit IsNeg, bit Rev>
- : CRInst<(outs PredRegs:$Pd), (ins PredRegs:$Ps, PredRegs:$Pt),
- "$Pd = " # MnOp # "($Ps, " # !if (IsNeg,"!","") # "$Pt)",
- [], "", CR_tc_2early_SLOT23> {
- bits<2> Pd;
- bits<2> Ps;
- bits<2> Pt;
-
- let IClass = 0b0110;
- let Inst{27-24} = 0b1011;
- let Inst{23-21} = OpBits;
- let Inst{20} = 0b0;
- let Inst{17-16} = !if(Rev,Pt,Ps); // Rs and Rt are reversed for some
- let Inst{13} = 0b0; // instructions.
- let Inst{9-8} = !if(Rev,Ps,Pt);
- let Inst{1-0} = Pd;
-}
-
-def C2_and : T_LOGICAL_2OP<"and", 0b000, 0, 1>;
-def C2_or : T_LOGICAL_2OP<"or", 0b001, 0, 1>;
-def C2_xor : T_LOGICAL_2OP<"xor", 0b010, 0, 0>;
-def C2_andn : T_LOGICAL_2OP<"and", 0b011, 1, 1>;
-def C2_orn : T_LOGICAL_2OP<"or", 0b111, 1, 1>;
-
-let hasSideEffects = 0, hasNewValue = 1 in
-def C2_vitpack : SInst<(outs IntRegs:$Rd), (ins PredRegs:$Ps, PredRegs:$Pt),
- "$Rd = vitpack($Ps, $Pt)", [], "", S_2op_tc_1_SLOT23> {
- bits<5> Rd;
- bits<2> Ps;
- bits<2> Pt;
-
- let IClass = 0b1000;
- let Inst{27-24} = 0b1001;
- let Inst{22-21} = 0b00;
- let Inst{17-16} = Ps;
- let Inst{9-8} = Pt;
- let Inst{4-0} = Rd;
-}
-
-let hasSideEffects = 0 in
-def C2_mask : SInst<(outs DoubleRegs:$Rd), (ins PredRegs:$Pt),
- "$Rd = mask($Pt)", [], "", S_2op_tc_1_SLOT23> {
- bits<5> Rd;
- bits<2> Pt;
-
- let IClass = 0b1000;
- let Inst{27-24} = 0b0110;
- let Inst{9-8} = Pt;
- let Inst{4-0} = Rd;
-}
-
-// User control register transfer.
-//===----------------------------------------------------------------------===//
-// CR -
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// JR +
-//===----------------------------------------------------------------------===//
-
-class CondStr<string CReg, bit True, bit New> {
- string S = "if (" # !if(True,"","!") # CReg # !if(New,".new","") # ") ";
-}
-class JumpOpcStr<string Mnemonic, bit New, bit Taken> {
- string S = Mnemonic # !if(Taken, ":t", ":nt");
-}
-
-let isBranch = 1, isBarrier = 1, Defs = [PC], hasSideEffects = 0,
- isPredicable = 1,
- isExtendable = 1, opExtendable = 0, isExtentSigned = 1,
- opExtentBits = 24, opExtentAlign = 2, InputType = "imm" in
-class T_JMP<string ExtStr>
- : JInst_CJUMP_UCJUMP<(outs), (ins brtarget:$dst),
- "jump " # ExtStr # "$dst",
- [], "", J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT> {
- bits<24> dst;
- let IClass = 0b0101;
-
- let Inst{27-25} = 0b100;
- let Inst{24-16} = dst{23-15};
- let Inst{13-1} = dst{14-2};
-}
-
-let isBranch = 1, Defs = [PC], hasSideEffects = 0, isPredicated = 1,
- isExtendable = 1, opExtendable = 1, isExtentSigned = 1,
- opExtentBits = 17, opExtentAlign = 2, InputType = "imm" in
-class T_JMP_c<bit PredNot, bit isPredNew, bit isTak, string ExtStr>
- : JInst_CJUMP_UCJUMP<(outs), (ins PredRegs:$src, brtarget:$dst),
- CondStr<"$src", !if(PredNot,0,1), isPredNew>.S #
- JumpOpcStr<"jump", isPredNew, isTak>.S # " " #
- ExtStr # "$dst",
- [], "", J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT>, ImmRegRel {
- let isTaken = isTak;
- let isPredicatedFalse = PredNot;
- let isPredicatedNew = isPredNew;
- bits<2> src;
- bits<17> dst;
-
- let IClass = 0b0101;
-
- let Inst{27-24} = 0b1100;
- let Inst{21} = PredNot;
- let Inst{12} = isTak;
- let Inst{11} = isPredNew;
- let Inst{9-8} = src;
- let Inst{23-22} = dst{16-15};
- let Inst{20-16} = dst{14-10};
- let Inst{13} = dst{9};
- let Inst{7-1} = dst{8-2};
- }
-
-multiclass JMP_Pred<bit PredNot, string ExtStr> {
- def NAME : T_JMP_c<PredNot, 0, 0, ExtStr>; // not taken
- // Predicate new
- def NAME#newpt : T_JMP_c<PredNot, 1, 1, ExtStr>; // taken
- def NAME#new : T_JMP_c<PredNot, 1, 0, ExtStr>; // not taken
-}
-
-multiclass JMP_base<string BaseOp, string ExtStr> {
- let BaseOpcode = BaseOp in {
- def NAME : T_JMP<ExtStr>;
- defm t : JMP_Pred<0, ExtStr>;
- defm f : JMP_Pred<1, ExtStr>;
- }
-}
-
-// Jumps to address stored in a register, JUMPR_MISC
-// if ([[!]P[.new]]) jumpr[:t/nt] Rs
-let isBranch = 1, isIndirectBranch = 1, isBarrier = 1, Defs = [PC],
- isPredicable = 1, hasSideEffects = 0, InputType = "reg" in
-class T_JMPr
- : JRInst<(outs), (ins IntRegs:$dst),
- "jumpr $dst", [], "", J_tc_2early_SLOT2> {
- bits<5> dst;
-
- let IClass = 0b0101;
- let Inst{27-21} = 0b0010100;
- let Inst{20-16} = dst;
-}
-
-let isBranch = 1, isIndirectBranch = 1, Defs = [PC], isPredicated = 1,
- hasSideEffects = 0, InputType = "reg" in
-class T_JMPr_c <bit PredNot, bit isPredNew, bit isTak>
- : JRInst <(outs), (ins PredRegs:$src, IntRegs:$dst),
- CondStr<"$src", !if(PredNot,0,1), isPredNew>.S #
- JumpOpcStr<"jumpr", isPredNew, isTak>.S # " $dst", [],
- "", J_tc_2early_SLOT2> {
-
- let isTaken = isTak;
- let isPredicatedFalse = PredNot;
- let isPredicatedNew = isPredNew;
- bits<2> src;
- bits<5> dst;
-
- let IClass = 0b0101;
-
- let Inst{27-22} = 0b001101;
- let Inst{21} = PredNot;
- let Inst{20-16} = dst;
- let Inst{12} = isTak;
- let Inst{11} = isPredNew;
- let Inst{9-8} = src;
-}
-
-multiclass JMPR_Pred<bit PredNot> {
- def NAME : T_JMPr_c<PredNot, 0, 0>; // not taken
- // Predicate new
- def NAME#newpt : T_JMPr_c<PredNot, 1, 1>; // taken
- def NAME#new : T_JMPr_c<PredNot, 1, 0>; // not taken
-}
-
-multiclass JMPR_base<string BaseOp> {
- let BaseOpcode = BaseOp in {
- def NAME : T_JMPr;
- defm t : JMPR_Pred<0>;
- defm f : JMPR_Pred<1>;
- }
-}
-
-let isCall = 1, hasSideEffects = 1 in
-class JUMPR_MISC_CALLR<bit isPred, bit isPredNot,
- dag InputDag = (ins IntRegs:$Rs)>
- : JRInst<(outs), InputDag,
- !if(isPred, !if(isPredNot, "if (!$Pu) callr $Rs",
- "if ($Pu) callr $Rs"),
- "callr $Rs"),
- [], "", J_tc_2early_SLOT2> {
- bits<5> Rs;
- bits<2> Pu;
- let isPredicated = isPred;
- let isPredicatedFalse = isPredNot;
-
- let IClass = 0b0101;
- let Inst{27-25} = 0b000;
- let Inst{24-23} = !if (isPred, 0b10, 0b01);
- let Inst{22} = 0;
- let Inst{21} = isPredNot;
- let Inst{9-8} = !if (isPred, Pu, 0b00);
- let Inst{20-16} = Rs;
-
- }
-
-let Defs = VolatileV3.Regs in {
- def J2_callrt : JUMPR_MISC_CALLR<1, 0, (ins PredRegs:$Pu, IntRegs:$Rs)>;
- def J2_callrf : JUMPR_MISC_CALLR<1, 1, (ins PredRegs:$Pu, IntRegs:$Rs)>;
-}
-
-let isTerminator = 1, hasSideEffects = 0 in {
- defm J2_jump : JMP_base<"JMP", "">, PredNewRel;
-
- defm J2_jumpr : JMPR_base<"JMPr">, PredNewRel;
-
- let isReturn = 1, isPseudo = 1, isCodeGenOnly = 1 in
- defm PS_jmpret : JMPR_base<"JMPret">, PredNewRel;
-}
-
-let validSubTargets = HasV60SubT in
-multiclass JMPpt_base<string BaseOp> {
- let BaseOpcode = BaseOp in {
- def tpt : T_JMP_c <0, 0, 1, "">; // Predicate true - taken
- def fpt : T_JMP_c <1, 0, 1, "">; // Predicate false - taken
- }
-}
-
-let validSubTargets = HasV60SubT in
-multiclass JMPRpt_base<string BaseOp> {
- let BaseOpcode = BaseOp in {
- def tpt : T_JMPr_c<0, 0, 1>; // predicate true - taken
- def fpt : T_JMPr_c<1, 0, 1>; // predicate false - taken
- }
-}
-
-defm J2_jumpr : JMPRpt_base<"JMPr">;
-defm J2_jump : JMPpt_base<"JMP">;
-
-// A return through builtin_eh_return.
-let isReturn = 1, isTerminator = 1, isBarrier = 1, hasSideEffects = 0,
- isCodeGenOnly = 1, Defs = [PC], Uses = [R28], isPredicable = 0 in
-def EH_RETURN_JMPR : T_JMPr;
-
-//===----------------------------------------------------------------------===//
-// JR -
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// LD +
-//===----------------------------------------------------------------------===//
-
-// Load - Base with Immediate offset addressing mode
-let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, AddedComplexity = 20 in
-class T_load_io <string mnemonic, RegisterClass RC, bits<4> MajOp,
- Operand ImmOp>
- : LDInst<(outs RC:$dst), (ins IntRegs:$src1, ImmOp:$offset),
- "$dst = "#mnemonic#"($src1 + #$offset)", []>, AddrModeRel {
- bits<4> name;
- bits<5> dst;
- bits<5> src1;
- bits<14> offset;
- bits<11> offsetBits;
-
- string ImmOpStr = !cast<string>(ImmOp);
- let offsetBits = !if (!eq(ImmOpStr, "s11_3Ext"), offset{13-3},
- !if (!eq(ImmOpStr, "s11_2Ext"), offset{12-2},
- !if (!eq(ImmOpStr, "s11_1Ext"), offset{11-1},
- /* s11_0Ext */ offset{10-0})));
- let opExtentBits = !if (!eq(ImmOpStr, "s11_3Ext"), 14,
- !if (!eq(ImmOpStr, "s11_2Ext"), 13,
- !if (!eq(ImmOpStr, "s11_1Ext"), 12,
- /* s11_0Ext */ 11)));
- let hasNewValue = !if (!eq(!cast<string>(RC), "DoubleRegs"), 0, 1);
-
- let IClass = 0b1001;
-
- let Inst{27} = 0b0;
- let Inst{26-25} = offsetBits{10-9};
- let Inst{24-21} = MajOp;
- let Inst{20-16} = src1;
- let Inst{13-5} = offsetBits{8-0};
- let Inst{4-0} = dst;
- }
-
-let opExtendable = 3, isExtentSigned = 0, isPredicated = 1 in
-class T_pload_io <string mnemonic, RegisterClass RC, bits<4>MajOp,
- Operand ImmOp, bit isNot, bit isPredNew>
- : LDInst<(outs RC:$dst),
- (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset),
- "if ("#!if(isNot, "!$src1", "$src1")
- #!if(isPredNew, ".new", "")
- #") $dst = "#mnemonic#"($src2 + #$offset)",
- [],"", V2LDST_tc_ld_SLOT01> , AddrModeRel {
- bits<5> dst;
- bits<2> src1;
- bits<5> src2;
- bits<9> offset;
- bits<6> offsetBits;
- string ImmOpStr = !cast<string>(ImmOp);
-
- let offsetBits = !if (!eq(ImmOpStr, "u6_3Ext"), offset{8-3},
- !if (!eq(ImmOpStr, "u6_2Ext"), offset{7-2},
- !if (!eq(ImmOpStr, "u6_1Ext"), offset{6-1},
- /* u6_0Ext */ offset{5-0})));
- let opExtentBits = !if (!eq(ImmOpStr, "u6_3Ext"), 9,
- !if (!eq(ImmOpStr, "u6_2Ext"), 8,
- !if (!eq(ImmOpStr, "u6_1Ext"), 7,
- /* u6_0Ext */ 6)));
- let hasNewValue = !if (!eq(ImmOpStr, "u6_3Ext"), 0, 1);
- let isPredicatedNew = isPredNew;
- let isPredicatedFalse = isNot;
-
- let IClass = 0b0100;
-
- let Inst{27} = 0b0;
- let Inst{27} = 0b0;
- let Inst{26} = isNot;
- let Inst{25} = isPredNew;
- let Inst{24-21} = MajOp;
- let Inst{20-16} = src2;
- let Inst{13} = 0b0;
- let Inst{12-11} = src1;
- let Inst{10-5} = offsetBits;
- let Inst{4-0} = dst;
- }
-
-let isExtendable = 1, hasSideEffects = 0, addrMode = BaseImmOffset in
-multiclass LD_Idxd<string mnemonic, string CextOp, RegisterClass RC,
- Operand ImmOp, Operand predImmOp, bits<4>MajOp> {
- let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
- let isPredicable = 1 in
- def L2_#NAME#_io : T_load_io <mnemonic, RC, MajOp, ImmOp>;
-
- // Predicated
- def L2_p#NAME#t_io : T_pload_io <mnemonic, RC, MajOp, predImmOp, 0, 0>;
- def L2_p#NAME#f_io : T_pload_io <mnemonic, RC, MajOp, predImmOp, 1, 0>;
-
- // Predicated new
- def L2_p#NAME#tnew_io : T_pload_io <mnemonic, RC, MajOp, predImmOp, 0, 1>;
- def L2_p#NAME#fnew_io : T_pload_io <mnemonic, RC, MajOp, predImmOp, 1, 1>;
- }
-}
-
-let accessSize = ByteAccess in {
- defm loadrb: LD_Idxd <"memb", "LDrib", IntRegs, s11_0Ext, u6_0Ext, 0b1000>;
- defm loadrub: LD_Idxd <"memub", "LDriub", IntRegs, s11_0Ext, u6_0Ext, 0b1001>;
-}
-
-let accessSize = HalfWordAccess, opExtentAlign = 1 in {
- defm loadrh: LD_Idxd <"memh", "LDrih", IntRegs, s11_1Ext, u6_1Ext, 0b1010>;
- defm loadruh: LD_Idxd <"memuh", "LDriuh", IntRegs, s11_1Ext, u6_1Ext, 0b1011>;
-}
-
-let accessSize = WordAccess, opExtentAlign = 2 in
-defm loadri: LD_Idxd <"memw", "LDriw", IntRegs, s11_2Ext, u6_2Ext, 0b1100>;
-
-let accessSize = DoubleWordAccess, opExtentAlign = 3 in
-defm loadrd: LD_Idxd <"memd", "LDrid", DoubleRegs, s11_3Ext, u6_3Ext, 0b1110>;
-
-let accessSize = HalfWordAccess, opExtentAlign = 1 in {
- def L2_loadbsw2_io: T_load_io<"membh", IntRegs, 0b0001, s11_1Ext>;
- def L2_loadbzw2_io: T_load_io<"memubh", IntRegs, 0b0011, s11_1Ext>;
-}
-
-let accessSize = WordAccess, opExtentAlign = 2 in {
- def L2_loadbzw4_io: T_load_io<"memubh", DoubleRegs, 0b0101, s11_2Ext>;
- def L2_loadbsw4_io: T_load_io<"membh", DoubleRegs, 0b0111, s11_2Ext>;
-}
-
-let addrMode = BaseImmOffset, isExtendable = 1, hasSideEffects = 0,
- opExtendable = 3, isExtentSigned = 1 in
-class T_loadalign_io <string str, bits<4> MajOp, Operand ImmOp>
- : LDInst<(outs DoubleRegs:$dst),
- (ins DoubleRegs:$src1, IntRegs:$src2, ImmOp:$offset),
- "$dst = "#str#"($src2 + #$offset)", [],
- "$src1 = $dst">, AddrModeRel {
- bits<4> name;
- bits<5> dst;
- bits<5> src2;
- bits<12> offset;
- bits<11> offsetBits;
-
- let offsetBits = !if (!eq(!cast<string>(ImmOp), "s11_1Ext"), offset{11-1},
- /* s11_0Ext */ offset{10-0});
- let IClass = 0b1001;
-
- let Inst{27} = 0b0;
- let Inst{26-25} = offsetBits{10-9};
- let Inst{24-21} = MajOp;
- let Inst{20-16} = src2;
- let Inst{13-5} = offsetBits{8-0};
- let Inst{4-0} = dst;
- }
-
-let accessSize = HalfWordAccess, opExtentBits = 12, opExtentAlign = 1 in
-def L2_loadalignh_io: T_loadalign_io <"memh_fifo", 0b0010, s11_1Ext>;
-
-let accessSize = ByteAccess, opExtentBits = 11 in
-def L2_loadalignb_io: T_loadalign_io <"memb_fifo", 0b0100, s11_0Ext>;
-
-//===----------------------------------------------------------------------===//
-// Post increment load
-//===----------------------------------------------------------------------===//
-//===----------------------------------------------------------------------===//
-// Template class for non-predicated post increment loads with immediate offset.
-//===----------------------------------------------------------------------===//
-let hasSideEffects = 0, addrMode = PostInc in
-class T_load_pi <string mnemonic, RegisterClass RC, Operand ImmOp,
- bits<4> MajOp >
- : LDInstPI <(outs RC:$dst, IntRegs:$dst2),
- (ins IntRegs:$src1, ImmOp:$offset),
- "$dst = "#mnemonic#"($src1++#$offset)" ,
- [],
- "$src1 = $dst2" > ,
- PredNewRel {
- bits<5> dst;
- bits<5> src1;
- bits<7> offset;
- bits<4> offsetBits;
-
- string ImmOpStr = !cast<string>(ImmOp);
- let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3},
- !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
- !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
- /* s4_0Imm */ offset{3-0})));
- let hasNewValue = !if (!eq(ImmOpStr, "s4_3Imm"), 0, 1);
-
- let IClass = 0b1001;
-
- let Inst{27-25} = 0b101;
- let Inst{24-21} = MajOp;
- let Inst{20-16} = src1;
- let Inst{13-12} = 0b00;
- let Inst{8-5} = offsetBits;
- let Inst{4-0} = dst;
- }
-
-//===----------------------------------------------------------------------===//
-// Template class for predicated post increment loads with immediate offset.
-//===----------------------------------------------------------------------===//
-let isPredicated = 1, hasSideEffects = 0, addrMode = PostInc in
-class T_pload_pi <string mnemonic, RegisterClass RC, Operand ImmOp,
- bits<4> MajOp, bit isPredNot, bit isPredNew >
- : LDInst <(outs RC:$dst, IntRegs:$dst2),
- (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset),
- !if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
- ") ")#"$dst = "#mnemonic#"($src2++#$offset)",
- [] ,
- "$src2 = $dst2" > ,
- PredNewRel {
- bits<5> dst;
- bits<2> src1;
- bits<5> src2;
- bits<7> offset;
- bits<4> offsetBits;
-
- let isPredicatedNew = isPredNew;
- let isPredicatedFalse = isPredNot;
-
- string ImmOpStr = !cast<string>(ImmOp);
- let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3},
- !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
- !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
- /* s4_0Imm */ offset{3-0})));
- let hasNewValue = !if (!eq(ImmOpStr, "s4_3Imm"), 0, 1);
-
- let IClass = 0b1001;
-
- let Inst{27-25} = 0b101;
- let Inst{24-21} = MajOp;
- let Inst{20-16} = src2;
- let Inst{13} = 0b1;
- let Inst{12} = isPredNew;
- let Inst{11} = isPredNot;
- let Inst{10-9} = src1;
- let Inst{8-5} = offsetBits;
- let Inst{4-0} = dst;
- }
-
-//===----------------------------------------------------------------------===//
-// Multiclass for post increment loads with immediate offset.
-//===----------------------------------------------------------------------===//
-
-multiclass LD_PostInc <string mnemonic, string BaseOp, RegisterClass RC,
- Operand ImmOp, bits<4> MajOp> {
- let BaseOpcode = "POST_"#BaseOp in {
- let isPredicable = 1 in
- def L2_#NAME#_pi : T_load_pi < mnemonic, RC, ImmOp, MajOp>;
-
- // Predicated
- def L2_p#NAME#t_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 0, 0>;
- def L2_p#NAME#f_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 1, 0>;
-
- // Predicated new
- def L2_p#NAME#tnew_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 0, 1>;
- def L2_p#NAME#fnew_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 1, 1>;
- }
-}
-
-// post increment byte loads with immediate offset
-let accessSize = ByteAccess in {
- defm loadrb : LD_PostInc <"memb", "LDrib", IntRegs, s4_0Imm, 0b1000>;
- defm loadrub : LD_PostInc <"memub", "LDriub", IntRegs, s4_0Imm, 0b1001>;
-}
-
-// post increment halfword loads with immediate offset
-let accessSize = HalfWordAccess, opExtentAlign = 1 in {
- defm loadrh : LD_PostInc <"memh", "LDrih", IntRegs, s4_1Imm, 0b1010>;
- defm loadruh : LD_PostInc <"memuh", "LDriuh", IntRegs, s4_1Imm, 0b1011>;
-}
-
-// post increment word loads with immediate offset
-let accessSize = WordAccess, opExtentAlign = 2 in
-defm loadri : LD_PostInc <"memw", "LDriw", IntRegs, s4_2Imm, 0b1100>;
-
-// post increment doubleword loads with immediate offset
-let accessSize = DoubleWordAccess, opExtentAlign = 3 in
-defm loadrd : LD_PostInc <"memd", "LDrid", DoubleRegs, s4_3Imm, 0b1110>;
-
-// Rd=memb[u]h(Rx++#s4:1)
-// Rdd=memb[u]h(Rx++#s4:2)
-let accessSize = HalfWordAccess, opExtentAlign = 1 in {
- def L2_loadbsw2_pi : T_load_pi <"membh", IntRegs, s4_1Imm, 0b0001>;
- def L2_loadbzw2_pi : T_load_pi <"memubh", IntRegs, s4_1Imm, 0b0011>;
-}
-let accessSize = WordAccess, opExtentAlign = 2, hasNewValue = 0 in {
- def L2_loadbsw4_pi : T_load_pi <"membh", DoubleRegs, s4_2Imm, 0b0111>;
- def L2_loadbzw4_pi : T_load_pi <"memubh", DoubleRegs, s4_2Imm, 0b0101>;
-}
-
-//===----------------------------------------------------------------------===//
-// Template class for post increment fifo loads with immediate offset.
-//===----------------------------------------------------------------------===//
-let hasSideEffects = 0, addrMode = PostInc in
-class T_loadalign_pi <string mnemonic, Operand ImmOp, bits<4> MajOp >
- : LDInstPI <(outs DoubleRegs:$dst, IntRegs:$dst2),
- (ins DoubleRegs:$src1, IntRegs:$src2, ImmOp:$offset),
- "$dst = "#mnemonic#"($src2++#$offset)" ,
- [], "$src2 = $dst2, $src1 = $dst" > ,
- PredNewRel {
- bits<5> dst;
- bits<5> src2;
- bits<5> offset;
- bits<4> offsetBits;
-
- let offsetBits = !if (!eq(!cast<string>(ImmOp), "s4_1Imm"), offset{4-1},
- /* s4_0Imm */ offset{3-0});
- let IClass = 0b1001;
-
- let Inst{27-25} = 0b101;
- let Inst{24-21} = MajOp;
- let Inst{20-16} = src2;
- let Inst{13-12} = 0b00;
- let Inst{8-5} = offsetBits;
- let Inst{4-0} = dst;
- }
-
-// Ryy=memh_fifo(Rx++#s4:1)
-// Ryy=memb_fifo(Rx++#s4:0)
-let accessSize = ByteAccess in
-def L2_loadalignb_pi : T_loadalign_pi <"memb_fifo", s4_0Imm, 0b0100>;
-
-let accessSize = HalfWordAccess, opExtentAlign = 1 in
-def L2_loadalignh_pi : T_loadalign_pi <"memh_fifo", s4_1Imm, 0b0010>;
-
-//===----------------------------------------------------------------------===//
-// Template class for post increment loads with register offset.
-//===----------------------------------------------------------------------===//
-let hasSideEffects = 0, addrMode = PostInc in
-class T_load_pr <string mnemonic, RegisterClass RC, bits<4> MajOp,
- MemAccessSize AccessSz>
- : LDInstPI <(outs RC:$dst, IntRegs:$_dst_),
- (ins IntRegs:$src1, ModRegs:$src2),
- "$dst = "#mnemonic#"($src1++$src2)" ,
- [], "$src1 = $_dst_" > {
- bits<5> dst;
- bits<5> src1;
- bits<1> src2;
-
- let accessSize = AccessSz;
- let IClass = 0b1001;
-
- let Inst{27-25} = 0b110;
- let Inst{24-21} = MajOp;
- let Inst{20-16} = src1;
- let Inst{13} = src2;
- let Inst{12} = 0b0;
- let Inst{7} = 0b0;
- let Inst{4-0} = dst;
- }
-
-let hasNewValue = 1 in {
- def L2_loadrb_pr : T_load_pr <"memb", IntRegs, 0b1000, ByteAccess>;
- def L2_loadrub_pr : T_load_pr <"memub", IntRegs, 0b1001, ByteAccess>;
- def L2_loadrh_pr : T_load_pr <"memh", IntRegs, 0b1010, HalfWordAccess>;
- def L2_loadruh_pr : T_load_pr <"memuh", IntRegs, 0b1011, HalfWordAccess>;
- def L2_loadri_pr : T_load_pr <"memw", IntRegs, 0b1100, WordAccess>;
-
- def L2_loadbzw2_pr : T_load_pr <"memubh", IntRegs, 0b0011, HalfWordAccess>;
-}
-
-def L2_loadrd_pr : T_load_pr <"memd", DoubleRegs, 0b1110, DoubleWordAccess>;
-def L2_loadbzw4_pr : T_load_pr <"memubh", DoubleRegs, 0b0101, WordAccess>;
-
-// Load predicate.
-let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 13,
- isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in
-def LDriw_pred : LDInst<(outs PredRegs:$dst),
- (ins IntRegs:$addr, s11_2Ext:$off),
- ".error \"should not emit\"", []>;
-// Load modifier.
-let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 13,
- isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in
-def LDriw_mod : LDInst<(outs ModRegs:$dst),
- (ins IntRegs:$addr, s11_2Ext:$off),
- ".error \"should not emit\"", []>;
-
-let Defs = [R29, R30, R31], Uses = [R30], hasSideEffects = 0 in
- def L2_deallocframe : LDInst<(outs), (ins),
- "deallocframe",
- []> {
- let IClass = 0b1001;
-
- let Inst{27-16} = 0b000000011110;
- let Inst{13} = 0b0;
- let Inst{4-0} = 0b11110;
-}
-
-// Load / Post increment circular addressing mode.
-let Uses = [CS], hasSideEffects = 0, addrMode = PostInc in
-class T_load_pcr<string mnemonic, RegisterClass RC, bits<4> MajOp>
- : LDInst <(outs RC:$dst, IntRegs:$_dst_),
- (ins IntRegs:$Rz, ModRegs:$Mu),
- "$dst = "#mnemonic#"($Rz ++ I:circ($Mu))", [],
- "$Rz = $_dst_" > {
- bits<5> dst;
- bits<5> Rz;
- bit Mu;
-
- let hasNewValue = !if (!eq(!cast<string>(RC), "DoubleRegs"), 0, 1);
- let IClass = 0b1001;
-
- let Inst{27-25} = 0b100;
- let Inst{24-21} = MajOp;
- let Inst{20-16} = Rz;
- let Inst{13} = Mu;
- let Inst{12} = 0b0;
- let Inst{9} = 0b1;
- let Inst{7} = 0b0;
- let Inst{4-0} = dst;
- }
-
-let accessSize = ByteAccess in {
- def L2_loadrb_pcr : T_load_pcr <"memb", IntRegs, 0b1000>;
- def L2_loadrub_pcr : T_load_pcr <"memub", IntRegs, 0b1001>;
-}
-
-let accessSize = HalfWordAccess in {
- def L2_loadrh_pcr : T_load_pcr <"memh", IntRegs, 0b1010>;
- def L2_loadruh_pcr : T_load_pcr <"memuh", IntRegs, 0b1011>;
- def L2_loadbsw2_pcr : T_load_pcr <"membh", IntRegs, 0b0001>;
- def L2_loadbzw2_pcr : T_load_pcr <"memubh", IntRegs, 0b0011>;
-}
-
-let accessSize = WordAccess in {
- def L2_loadri_pcr : T_load_pcr <"memw", IntRegs, 0b1100>;
- let hasNewValue = 0 in {
- def L2_loadbzw4_pcr : T_load_pcr <"memubh", DoubleRegs, 0b0101>;
- def L2_loadbsw4_pcr : T_load_pcr <"membh", DoubleRegs, 0b0111>;
- }
-}
-
-let accessSize = DoubleWordAccess in
-def L2_loadrd_pcr : T_load_pcr <"memd", DoubleRegs, 0b1110>;
-
-// Load / Post increment circular addressing mode.
-let Uses = [CS], hasSideEffects = 0, addrMode = PostInc in
-class T_loadalign_pcr<string mnemonic, bits<4> MajOp, MemAccessSize AccessSz >
- : LDInst <(outs DoubleRegs:$dst, IntRegs:$_dst_),
- (ins DoubleRegs:$_src_, IntRegs:$Rz, ModRegs:$Mu),
- "$dst = "#mnemonic#"($Rz ++ I:circ($Mu))", [],
- "$Rz = $_dst_, $dst = $_src_" > {
- bits<5> dst;
- bits<5> Rz;
- bit Mu;
-
- let accessSize = AccessSz;
- let IClass = 0b1001;
-
- let Inst{27-25} = 0b100;
- let Inst{24-21} = MajOp;
- let Inst{20-16} = Rz;
- let Inst{13} = Mu;
- let Inst{12} = 0b0;
- let Inst{9} = 0b1;
- let Inst{7} = 0b0;
- let Inst{4-0} = dst;
- }
-
-def L2_loadalignb_pcr : T_loadalign_pcr <"memb_fifo", 0b0100, ByteAccess>;
-def L2_loadalignh_pcr : T_loadalign_pcr <"memh_fifo", 0b0010, HalfWordAccess>;
-
-//===----------------------------------------------------------------------===//
-// Circular loads with immediate offset.
-//===----------------------------------------------------------------------===//
-let Uses = [CS], mayLoad = 1, hasSideEffects = 0, addrMode = PostInc in
-class T_load_pci <string mnemonic, RegisterClass RC,
- Operand ImmOp, bits<4> MajOp>
- : LDInstPI<(outs RC:$dst, IntRegs:$_dst_),
- (ins IntRegs:$Rz, ImmOp:$offset, ModRegs:$Mu),
- "$dst = "#mnemonic#"($Rz ++ #$offset:circ($Mu))", [],
- "$Rz = $_dst_"> {
- bits<5> dst;
- bits<5> Rz;
- bits<1> Mu;
- bits<7> offset;
- bits<4> offsetBits;
-
- string ImmOpStr = !cast<string>(ImmOp);
- let hasNewValue = !if (!eq(!cast<string>(RC), "DoubleRegs"), 0, 1);
- let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3},
- !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
- !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
- /* s4_0Imm */ offset{3-0})));
- let IClass = 0b1001;
- let Inst{27-25} = 0b100;
- let Inst{24-21} = MajOp;
- let Inst{20-16} = Rz;
- let Inst{13} = Mu;
- let Inst{12} = 0b0;
- let Inst{9} = 0b0;
- let Inst{8-5} = offsetBits;
- let Inst{4-0} = dst;
- }
-
-// Byte variants of circ load
-let accessSize = ByteAccess in {
- def L2_loadrb_pci : T_load_pci <"memb", IntRegs, s4_0Imm, 0b1000>;
- def L2_loadrub_pci : T_load_pci <"memub", IntRegs, s4_0Imm, 0b1001>;
-}
-
-// Half word variants of circ load
-let accessSize = HalfWordAccess in {
- def L2_loadrh_pci : T_load_pci <"memh", IntRegs, s4_1Imm, 0b1010>;
- def L2_loadruh_pci : T_load_pci <"memuh", IntRegs, s4_1Imm, 0b1011>;
- def L2_loadbzw2_pci : T_load_pci <"memubh", IntRegs, s4_1Imm, 0b0011>;
- def L2_loadbsw2_pci : T_load_pci <"membh", IntRegs, s4_1Imm, 0b0001>;
-}
-
-// Word variants of circ load
-let accessSize = WordAccess in
-def L2_loadri_pci : T_load_pci <"memw", IntRegs, s4_2Imm, 0b1100>;
-
-let accessSize = WordAccess, hasNewValue = 0 in {
- def L2_loadbzw4_pci : T_load_pci <"memubh", DoubleRegs, s4_2Imm, 0b0101>;
- def L2_loadbsw4_pci : T_load_pci <"membh", DoubleRegs, s4_2Imm, 0b0111>;
-}
-
-let accessSize = DoubleWordAccess, hasNewValue = 0 in
-def L2_loadrd_pci : T_load_pci <"memd", DoubleRegs, s4_3Imm, 0b1110>;
-
-
-// TODO: memb_fifo and memh_fifo must take destination register as input.
-// One-off circ loads - not enough in common to break into a class.
-let accessSize = ByteAccess in
-def L2_loadalignb_pci : T_load_pci <"memb_fifo", DoubleRegs, s4_0Imm, 0b0100>;
-
-let accessSize = HalfWordAccess, opExtentAlign = 1 in
-def L2_loadalignh_pci : T_load_pci <"memh_fifo", DoubleRegs, s4_1Imm, 0b0010>;
-
-// L[24]_load[wd]_locked: Load word/double with lock.
-let isSoloAX = 1 in
-class T_load_locked <string mnemonic, RegisterClass RC>
- : LD0Inst <(outs RC:$dst),
- (ins IntRegs:$src),
- "$dst = "#mnemonic#"($src)"> {
- bits<5> dst;
- bits<5> src;
- let IClass = 0b1001;
- let Inst{27-21} = 0b0010000;
- let Inst{20-16} = src;
- let Inst{13-12} = !if (!eq(mnemonic, "memd_locked"), 0b01, 0b00);
- let Inst{5} = 0;
- let Inst{4-0} = dst;
-}
-let hasNewValue = 1, accessSize = WordAccess, opNewValue = 0 in
- def L2_loadw_locked : T_load_locked <"memw_locked", IntRegs>;
-let accessSize = DoubleWordAccess in
- def L4_loadd_locked : T_load_locked <"memd_locked", DoubleRegs>;
-
-// S[24]_store[wd]_locked: Store word/double conditionally.
-let isSoloAX = 1, isPredicateLate = 1 in
-class T_store_locked <string mnemonic, RegisterClass RC>
- : ST0Inst <(outs PredRegs:$Pd), (ins IntRegs:$Rs, RC:$Rt),
- mnemonic#"($Rs, $Pd) = $Rt"> {
- bits<2> Pd;
- bits<5> Rs;
- bits<5> Rt;
-
- let IClass = 0b1010;
- let Inst{27-23} = 0b00001;
- let Inst{22} = !if (!eq(mnemonic, "memw_locked"), 0b0, 0b1);
- let Inst{21} = 0b1;
- let Inst{20-16} = Rs;
- let Inst{12-8} = Rt;
- let Inst{1-0} = Pd;
-}
-
-let accessSize = WordAccess in
-def S2_storew_locked : T_store_locked <"memw_locked", IntRegs>;
-
-let accessSize = DoubleWordAccess in
-def S4_stored_locked : T_store_locked <"memd_locked", DoubleRegs>;
-
-//===----------------------------------------------------------------------===//
-// Bit-reversed loads with auto-increment register
-//===----------------------------------------------------------------------===//
-let hasSideEffects = 0, addrMode = PostInc in
-class T_load_pbr<string mnemonic, RegisterClass RC,
- MemAccessSize addrSize, bits<4> majOp>
- : LDInst
- <(outs RC:$dst, IntRegs:$_dst_),
- (ins IntRegs:$Rz, ModRegs:$Mu),
- "$dst = "#mnemonic#"($Rz ++ $Mu:brev)" ,
- [] , "$Rz = $_dst_" > {
-
- let accessSize = addrSize;
-
- bits<5> dst;
- bits<5> Rz;
- bits<1> Mu;
-
- let IClass = 0b1001;
-
- let Inst{27-25} = 0b111;
- let Inst{24-21} = majOp;
- let Inst{20-16} = Rz;
- let Inst{13} = Mu;
- let Inst{12} = 0b0;
- let Inst{7} = 0b0;
- let Inst{4-0} = dst;
- }
-
-let hasNewValue =1, opNewValue = 0 in {
- def L2_loadrb_pbr : T_load_pbr <"memb", IntRegs, ByteAccess, 0b1000>;
- def L2_loadrub_pbr : T_load_pbr <"memub", IntRegs, ByteAccess, 0b1001>;
- def L2_loadrh_pbr : T_load_pbr <"memh", IntRegs, HalfWordAccess, 0b1010>;
- def L2_loadruh_pbr : T_load_pbr <"memuh", IntRegs, HalfWordAccess, 0b1011>;
- def L2_loadbsw2_pbr : T_load_pbr <"membh", IntRegs, HalfWordAccess, 0b0001>;
- def L2_loadbzw2_pbr : T_load_pbr <"memubh", IntRegs, HalfWordAccess, 0b0011>;
- def L2_loadri_pbr : T_load_pbr <"memw", IntRegs, WordAccess, 0b1100>;
-}
-
-def L2_loadbzw4_pbr : T_load_pbr <"memubh", DoubleRegs, WordAccess, 0b0101>;
-def L2_loadbsw4_pbr : T_load_pbr <"membh", DoubleRegs, WordAccess, 0b0111>;
-def L2_loadrd_pbr : T_load_pbr <"memd", DoubleRegs, DoubleWordAccess, 0b1110>;
-
-def L2_loadalignb_pbr :T_load_pbr <"memb_fifo", DoubleRegs, ByteAccess, 0b0100>;
-def L2_loadalignh_pbr :T_load_pbr <"memh_fifo", DoubleRegs,
- HalfWordAccess, 0b0010>;
-
-//===----------------------------------------------------------------------===//
-// LD -
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// MTYPE/ALU +
-//===----------------------------------------------------------------------===//
-//===----------------------------------------------------------------------===//
-// MTYPE/ALU -
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// MTYPE/COMPLEX +
-//===----------------------------------------------------------------------===//
-//===----------------------------------------------------------------------===//
-// MTYPE/COMPLEX -
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// MTYPE/MPYH +
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// Template Class
-// MPYS / Multipy signed/unsigned halfwords
-//Rd=mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:rnd][:sat]
-//===----------------------------------------------------------------------===//
-
-let hasNewValue = 1, opNewValue = 0 in
-class T_M2_mpy < bits<2> LHbits, bit isSat, bit isRnd,
- bit hasShift, bit isUnsigned>
- : MInst < (outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
- "$Rd = "#!if(isUnsigned,"mpyu","mpy")#"($Rs."#!if(LHbits{1},"h","l")
- #", $Rt."#!if(LHbits{0},"h)","l)")
- #!if(hasShift,":<<1","")
- #!if(isRnd,":rnd","")
- #!if(isSat,":sat",""),
- [], "", M_tc_3x_SLOT23 > {
- bits<5> Rd;
- bits<5> Rs;
- bits<5> Rt;
-
- let IClass = 0b1110;
-
- let Inst{27-24} = 0b1100;
- let Inst{23} = hasShift;
- let Inst{22} = isUnsigned;
- let Inst{21} = isRnd;
- let Inst{7} = isSat;
- let Inst{6-5} = LHbits;
- let Inst{4-0} = Rd;
- let Inst{20-16} = Rs;
- let Inst{12-8} = Rt;
- }
-
-//Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1]
-def M2_mpy_ll_s1: T_M2_mpy<0b00, 0, 0, 1, 0>;
-def M2_mpy_ll_s0: T_M2_mpy<0b00, 0, 0, 0, 0>;
-def M2_mpy_lh_s1: T_M2_mpy<0b01, 0, 0, 1, 0>;
-def M2_mpy_lh_s0: T_M2_mpy<0b01, 0, 0, 0, 0>;
-def M2_mpy_hl_s1: T_M2_mpy<0b10, 0, 0, 1, 0>;
-def M2_mpy_hl_s0: T_M2_mpy<0b10, 0, 0, 0, 0>;
-def M2_mpy_hh_s1: T_M2_mpy<0b11, 0, 0, 1, 0>;
-def M2_mpy_hh_s0: T_M2_mpy<0b11, 0, 0, 0, 0>;
-
-//Rd=mpyu(Rs.[H|L],Rt.[H|L])[:<<1]
-def M2_mpyu_ll_s1: T_M2_mpy<0b00, 0, 0, 1, 1>;
-def M2_mpyu_ll_s0: T_M2_mpy<0b00, 0, 0, 0, 1>;
-def M2_mpyu_lh_s1: T_M2_mpy<0b01, 0, 0, 1, 1>;
-def M2_mpyu_lh_s0: T_M2_mpy<0b01, 0, 0, 0, 1>;
-def M2_mpyu_hl_s1: T_M2_mpy<0b10, 0, 0, 1, 1>;
-def M2_mpyu_hl_s0: T_M2_mpy<0b10, 0, 0, 0, 1>;
-def M2_mpyu_hh_s1: T_M2_mpy<0b11, 0, 0, 1, 1>;
-def M2_mpyu_hh_s0: T_M2_mpy<0b11, 0, 0, 0, 1>;
-
-//Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1]:rnd
-def M2_mpy_rnd_ll_s1: T_M2_mpy <0b00, 0, 1, 1, 0>;
-def M2_mpy_rnd_ll_s0: T_M2_mpy <0b00, 0, 1, 0, 0>;
-def M2_mpy_rnd_lh_s1: T_M2_mpy <0b01, 0, 1, 1, 0>;
-def M2_mpy_rnd_lh_s0: T_M2_mpy <0b01, 0, 1, 0, 0>;
-def M2_mpy_rnd_hl_s1: T_M2_mpy <0b10, 0, 1, 1, 0>;
-def M2_mpy_rnd_hl_s0: T_M2_mpy <0b10, 0, 1, 0, 0>;
-def M2_mpy_rnd_hh_s1: T_M2_mpy <0b11, 0, 1, 1, 0>;
-def M2_mpy_rnd_hh_s0: T_M2_mpy <0b11, 0, 1, 0, 0>;
-
-//Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1][:sat]
-//Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1][:rnd][:sat]
-let Defs = [USR_OVF] in {
- def M2_mpy_sat_ll_s1: T_M2_mpy <0b00, 1, 0, 1, 0>;
- def M2_mpy_sat_ll_s0: T_M2_mpy <0b00, 1, 0, 0, 0>;
- def M2_mpy_sat_lh_s1: T_M2_mpy <0b01, 1, 0, 1, 0>;
- def M2_mpy_sat_lh_s0: T_M2_mpy <0b01, 1, 0, 0, 0>;
- def M2_mpy_sat_hl_s1: T_M2_mpy <0b10, 1, 0, 1, 0>;
- def M2_mpy_sat_hl_s0: T_M2_mpy <0b10, 1, 0, 0, 0>;
- def M2_mpy_sat_hh_s1: T_M2_mpy <0b11, 1, 0, 1, 0>;
- def M2_mpy_sat_hh_s0: T_M2_mpy <0b11, 1, 0, 0, 0>;
-
- def M2_mpy_sat_rnd_ll_s1: T_M2_mpy <0b00, 1, 1, 1, 0>;
- def M2_mpy_sat_rnd_ll_s0: T_M2_mpy <0b00, 1, 1, 0, 0>;
- def M2_mpy_sat_rnd_lh_s1: T_M2_mpy <0b01, 1, 1, 1, 0>;
- def M2_mpy_sat_rnd_lh_s0: T_M2_mpy <0b01, 1, 1, 0, 0>;
- def M2_mpy_sat_rnd_hl_s1: T_M2_mpy <0b10, 1, 1, 1, 0>;
- def M2_mpy_sat_rnd_hl_s0: T_M2_mpy <0b10, 1, 1, 0, 0>;
- def M2_mpy_sat_rnd_hh_s1: T_M2_mpy <0b11, 1, 1, 1, 0>;
- def M2_mpy_sat_rnd_hh_s0: T_M2_mpy <0b11, 1, 1, 0, 0>;
-}
-
-//===----------------------------------------------------------------------===//
-// Template Class
-// MPYS / Multipy signed/unsigned halfwords and add/subtract the
-// result from the accumulator.
-//Rx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat]
-//===----------------------------------------------------------------------===//
-
-let hasNewValue = 1, opNewValue = 0 in
-class T_M2_mpy_acc < bits<2> LHbits, bit isSat, bit isNac,
- bit hasShift, bit isUnsigned >
- : MInst_acc<(outs IntRegs:$Rx), (ins IntRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt),
- "$Rx "#!if(isNac,"-= ","+= ")#!if(isUnsigned,"mpyu","mpy")
- #"($Rs."#!if(LHbits{1},"h","l")
- #", $Rt."#!if(LHbits{0},"h)","l)")
- #!if(hasShift,":<<1","")
- #!if(isSat,":sat",""),
- [], "$dst2 = $Rx", M_tc_3x_SLOT23 > {
- bits<5> Rx;
- bits<5> Rs;
- bits<5> Rt;
-
- let IClass = 0b1110;
- let Inst{27-24} = 0b1110;
- let Inst{23} = hasShift;
- let Inst{22} = isUnsigned;
- let Inst{21} = isNac;
- let Inst{7} = isSat;
- let Inst{6-5} = LHbits;
- let Inst{4-0} = Rx;
- let Inst{20-16} = Rs;
- let Inst{12-8} = Rt;
- }
-
-//Rx += mpy(Rs.[H|L],Rt.[H|L])[:<<1]
-def M2_mpy_acc_ll_s1: T_M2_mpy_acc <0b00, 0, 0, 1, 0>;
-def M2_mpy_acc_ll_s0: T_M2_mpy_acc <0b00, 0, 0, 0, 0>;
-def M2_mpy_acc_lh_s1: T_M2_mpy_acc <0b01, 0, 0, 1, 0>;
-def M2_mpy_acc_lh_s0: T_M2_mpy_acc <0b01, 0, 0, 0, 0>;
-def M2_mpy_acc_hl_s1: T_M2_mpy_acc <0b10, 0, 0, 1, 0>;
-def M2_mpy_acc_hl_s0: T_M2_mpy_acc <0b10, 0, 0, 0, 0>;
-def M2_mpy_acc_hh_s1: T_M2_mpy_acc <0b11, 0, 0, 1, 0>;
-def M2_mpy_acc_hh_s0: T_M2_mpy_acc <0b11, 0, 0, 0, 0>;
-
-//Rx += mpyu(Rs.[H|L],Rt.[H|L])[:<<1]
-def M2_mpyu_acc_ll_s1: T_M2_mpy_acc <0b00, 0, 0, 1, 1>;
-def M2_mpyu_acc_ll_s0: T_M2_mpy_acc <0b00, 0, 0, 0, 1>;
-def M2_mpyu_acc_lh_s1: T_M2_mpy_acc <0b01, 0, 0, 1, 1>;
-def M2_mpyu_acc_lh_s0: T_M2_mpy_acc <0b01, 0, 0, 0, 1>;
-def M2_mpyu_acc_hl_s1: T_M2_mpy_acc <0b10, 0, 0, 1, 1>;
-def M2_mpyu_acc_hl_s0: T_M2_mpy_acc <0b10, 0, 0, 0, 1>;
-def M2_mpyu_acc_hh_s1: T_M2_mpy_acc <0b11, 0, 0, 1, 1>;
-def M2_mpyu_acc_hh_s0: T_M2_mpy_acc <0b11, 0, 0, 0, 1>;
-
-//Rx -= mpy(Rs.[H|L],Rt.[H|L])[:<<1]
-def M2_mpy_nac_ll_s1: T_M2_mpy_acc <0b00, 0, 1, 1, 0>;
-def M2_mpy_nac_ll_s0: T_M2_mpy_acc <0b00, 0, 1, 0, 0>;
-def M2_mpy_nac_lh_s1: T_M2_mpy_acc <0b01, 0, 1, 1, 0>;
-def M2_mpy_nac_lh_s0: T_M2_mpy_acc <0b01, 0, 1, 0, 0>;
-def M2_mpy_nac_hl_s1: T_M2_mpy_acc <0b10, 0, 1, 1, 0>;
-def M2_mpy_nac_hl_s0: T_M2_mpy_acc <0b10, 0, 1, 0, 0>;
-def M2_mpy_nac_hh_s1: T_M2_mpy_acc <0b11, 0, 1, 1, 0>;
-def M2_mpy_nac_hh_s0: T_M2_mpy_acc <0b11, 0, 1, 0, 0>;
-
-//Rx -= mpyu(Rs.[H|L],Rt.[H|L])[:<<1]
-def M2_mpyu_nac_ll_s1: T_M2_mpy_acc <0b00, 0, 1, 1, 1>;
-def M2_mpyu_nac_ll_s0: T_M2_mpy_acc <0b00, 0, 1, 0, 1>;
-def M2_mpyu_nac_lh_s1: T_M2_mpy_acc <0b01, 0, 1, 1, 1>;
-def M2_mpyu_nac_lh_s0: T_M2_mpy_acc <0b01, 0, 1, 0, 1>;
-def M2_mpyu_nac_hl_s1: T_M2_mpy_acc <0b10, 0, 1, 1, 1>;
-def M2_mpyu_nac_hl_s0: T_M2_mpy_acc <0b10, 0, 1, 0, 1>;
-def M2_mpyu_nac_hh_s1: T_M2_mpy_acc <0b11, 0, 1, 1, 1>;
-def M2_mpyu_nac_hh_s0: T_M2_mpy_acc <0b11, 0, 1, 0, 1>;
-
-//Rx += mpy(Rs.[H|L],Rt.[H|L])[:<<1]:sat
-def M2_mpy_acc_sat_ll_s1: T_M2_mpy_acc <0b00, 1, 0, 1, 0>;
-def M2_mpy_acc_sat_ll_s0: T_M2_mpy_acc <0b00, 1, 0, 0, 0>;
-def M2_mpy_acc_sat_lh_s1: T_M2_mpy_acc <0b01, 1, 0, 1, 0>;
-def M2_mpy_acc_sat_lh_s0: T_M2_mpy_acc <0b01, 1, 0, 0, 0>;
-def M2_mpy_acc_sat_hl_s1: T_M2_mpy_acc <0b10, 1, 0, 1, 0>;
-def M2_mpy_acc_sat_hl_s0: T_M2_mpy_acc <0b10, 1, 0, 0, 0>;
-def M2_mpy_acc_sat_hh_s1: T_M2_mpy_acc <0b11, 1, 0, 1, 0>;
-def M2_mpy_acc_sat_hh_s0: T_M2_mpy_acc <0b11, 1, 0, 0, 0>;
-
-//Rx -= mpy(Rs.[H|L],Rt.[H|L])[:<<1]:sat
-def M2_mpy_nac_sat_ll_s1: T_M2_mpy_acc <0b00, 1, 1, 1, 0>;
-def M2_mpy_nac_sat_ll_s0: T_M2_mpy_acc <0b00, 1, 1, 0, 0>;
-def M2_mpy_nac_sat_lh_s1: T_M2_mpy_acc <0b01, 1, 1, 1, 0>;
-def M2_mpy_nac_sat_lh_s0: T_M2_mpy_acc <0b01, 1, 1, 0, 0>;
-def M2_mpy_nac_sat_hl_s1: T_M2_mpy_acc <0b10, 1, 1, 1, 0>;
-def M2_mpy_nac_sat_hl_s0: T_M2_mpy_acc <0b10, 1, 1, 0, 0>;
-def M2_mpy_nac_sat_hh_s1: T_M2_mpy_acc <0b11, 1, 1, 1, 0>;
-def M2_mpy_nac_sat_hh_s0: T_M2_mpy_acc <0b11, 1, 1, 0, 0>;
-
-//===----------------------------------------------------------------------===//
-// Template Class
-// MPYS / Multipy signed/unsigned halfwords and add/subtract the
-// result from the 64-bit destination register.
-//Rxx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat]
-//===----------------------------------------------------------------------===//
-
-class T_M2_mpyd_acc < bits<2> LHbits, bit isNac, bit hasShift, bit isUnsigned>
- : MInst_acc<(outs DoubleRegs:$Rxx),
- (ins DoubleRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt),
- "$Rxx "#!if(isNac,"-= ","+= ")#!if(isUnsigned,"mpyu","mpy")
- #"($Rs."#!if(LHbits{1},"h","l")
- #", $Rt."#!if(LHbits{0},"h)","l)")
- #!if(hasShift,":<<1",""),
- [], "$dst2 = $Rxx", M_tc_3x_SLOT23 > {
- bits<5> Rxx;
- bits<5> Rs;
- bits<5> Rt;
-
- let IClass = 0b1110;
-
- let Inst{27-24} = 0b0110;
- let Inst{23} = hasShift;
- let Inst{22} = isUnsigned;
- let Inst{21} = isNac;
- let Inst{7} = 0;
- let Inst{6-5} = LHbits;
- let Inst{4-0} = Rxx;
- let Inst{20-16} = Rs;
- let Inst{12-8} = Rt;
- }
-
-def M2_mpyd_acc_hh_s0: T_M2_mpyd_acc <0b11, 0, 0, 0>;
-def M2_mpyd_acc_hl_s0: T_M2_mpyd_acc <0b10, 0, 0, 0>;
-def M2_mpyd_acc_lh_s0: T_M2_mpyd_acc <0b01, 0, 0, 0>;
-def M2_mpyd_acc_ll_s0: T_M2_mpyd_acc <0b00, 0, 0, 0>;
-
-def M2_mpyd_acc_hh_s1: T_M2_mpyd_acc <0b11, 0, 1, 0>;
-def M2_mpyd_acc_hl_s1: T_M2_mpyd_acc <0b10, 0, 1, 0>;
-def M2_mpyd_acc_lh_s1: T_M2_mpyd_acc <0b01, 0, 1, 0>;
-def M2_mpyd_acc_ll_s1: T_M2_mpyd_acc <0b00, 0, 1, 0>;
-
-def M2_mpyd_nac_hh_s0: T_M2_mpyd_acc <0b11, 1, 0, 0>;
-def M2_mpyd_nac_hl_s0: T_M2_mpyd_acc <0b10, 1, 0, 0>;
-def M2_mpyd_nac_lh_s0: T_M2_mpyd_acc <0b01, 1, 0, 0>;
-def M2_mpyd_nac_ll_s0: T_M2_mpyd_acc <0b00, 1, 0, 0>;
-
-def M2_mpyd_nac_hh_s1: T_M2_mpyd_acc <0b11, 1, 1, 0>;
-def M2_mpyd_nac_hl_s1: T_M2_mpyd_acc <0b10, 1, 1, 0>;
-def M2_mpyd_nac_lh_s1: T_M2_mpyd_acc <0b01, 1, 1, 0>;
-def M2_mpyd_nac_ll_s1: T_M2_mpyd_acc <0b00, 1, 1, 0>;
-
-def M2_mpyud_acc_hh_s0: T_M2_mpyd_acc <0b11, 0, 0, 1>;
-def M2_mpyud_acc_hl_s0: T_M2_mpyd_acc <0b10, 0, 0, 1>;
-def M2_mpyud_acc_lh_s0: T_M2_mpyd_acc <0b01, 0, 0, 1>;
-def M2_mpyud_acc_ll_s0: T_M2_mpyd_acc <0b00, 0, 0, 1>;
-
-def M2_mpyud_acc_hh_s1: T_M2_mpyd_acc <0b11, 0, 1, 1>;
-def M2_mpyud_acc_hl_s1: T_M2_mpyd_acc <0b10, 0, 1, 1>;
-def M2_mpyud_acc_lh_s1: T_M2_mpyd_acc <0b01, 0, 1, 1>;
-def M2_mpyud_acc_ll_s1: T_M2_mpyd_acc <0b00, 0, 1, 1>;
-
-def M2_mpyud_nac_hh_s0: T_M2_mpyd_acc <0b11, 1, 0, 1>;
-def M2_mpyud_nac_hl_s0: T_M2_mpyd_acc <0b10, 1, 0, 1>;
-def M2_mpyud_nac_lh_s0: T_M2_mpyd_acc <0b01, 1, 0, 1>;
-def M2_mpyud_nac_ll_s0: T_M2_mpyd_acc <0b00, 1, 0, 1>;
-
-def M2_mpyud_nac_hh_s1: T_M2_mpyd_acc <0b11, 1, 1, 1>;
-def M2_mpyud_nac_hl_s1: T_M2_mpyd_acc <0b10, 1, 1, 1>;
-def M2_mpyud_nac_lh_s1: T_M2_mpyd_acc <0b01, 1, 1, 1>;
-def M2_mpyud_nac_ll_s1: T_M2_mpyd_acc <0b00, 1, 1, 1>;
-
-//===----------------------------------------------------------------------===//
-// Template Class -- Vector Multipy
-// Used for complex multiply real or imaginary, dual multiply and even halfwords
-//===----------------------------------------------------------------------===//
-class T_M2_vmpy < string opc, bits<3> MajOp, bits<3> MinOp, bit hasShift,
- bit isRnd, bit isSat >
- : MInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
- "$Rdd = "#opc#"($Rss, $Rtt)"#!if(hasShift,":<<1","")
- #!if(isRnd,":rnd","")
- #!if(isSat,":sat",""),
- [] > {
- bits<5> Rdd;
- bits<5> Rss;
- bits<5> Rtt;
-
- let IClass = 0b1110;
-
- let Inst{27-24} = 0b1000;
- let Inst{23-21} = MajOp;
- let Inst{7-5} = MinOp;
- let Inst{4-0} = Rdd;
- let Inst{20-16} = Rss;
- let Inst{12-8} = Rtt;
- }
-
-// Vector complex multiply imaginary: Rdd=vcmpyi(Rss,Rtt)[:<<1]:sat
-let Defs = [USR_OVF] in {
-def M2_vcmpy_s1_sat_i: T_M2_vmpy <"vcmpyi", 0b110, 0b110, 1, 0, 1>;
-def M2_vcmpy_s0_sat_i: T_M2_vmpy <"vcmpyi", 0b010, 0b110, 0, 0, 1>;
-
-// Vector complex multiply real: Rdd=vcmpyr(Rss,Rtt)[:<<1]:sat
-def M2_vcmpy_s1_sat_r: T_M2_vmpy <"vcmpyr", 0b101, 0b110, 1, 0, 1>;
-def M2_vcmpy_s0_sat_r: T_M2_vmpy <"vcmpyr", 0b001, 0b110, 0, 0, 1>;
-
-// Vector dual multiply: Rdd=vdmpy(Rss,Rtt)[:<<1]:sat
-def M2_vdmpys_s1: T_M2_vmpy <"vdmpy", 0b100, 0b100, 1, 0, 1>;
-def M2_vdmpys_s0: T_M2_vmpy <"vdmpy", 0b000, 0b100, 0, 0, 1>;
-
-// Vector multiply even halfwords: Rdd=vmpyeh(Rss,Rtt)[:<<1]:sat
-def M2_vmpy2es_s1: T_M2_vmpy <"vmpyeh", 0b100, 0b110, 1, 0, 1>;
-def M2_vmpy2es_s0: T_M2_vmpy <"vmpyeh", 0b000, 0b110, 0, 0, 1>;
-
-//Rdd=vmpywoh(Rss,Rtt)[:<<1][:rnd]:sat
-def M2_mmpyh_s0: T_M2_vmpy <"vmpywoh", 0b000, 0b111, 0, 0, 1>;
-def M2_mmpyh_s1: T_M2_vmpy <"vmpywoh", 0b100, 0b111, 1, 0, 1>;
-def M2_mmpyh_rs0: T_M2_vmpy <"vmpywoh", 0b001, 0b111, 0, 1, 1>;
-def M2_mmpyh_rs1: T_M2_vmpy <"vmpywoh", 0b101, 0b111, 1, 1, 1>;
-
-//Rdd=vmpyweh(Rss,Rtt)[:<<1][:rnd]:sat
-def M2_mmpyl_s0: T_M2_vmpy <"vmpyweh", 0b000, 0b101, 0, 0, 1>;
-def M2_mmpyl_s1: T_M2_vmpy <"vmpyweh", 0b100, 0b101, 1, 0, 1>;
-def M2_mmpyl_rs0: T_M2_vmpy <"vmpyweh", 0b001, 0b101, 0, 1, 1>;
-def M2_mmpyl_rs1: T_M2_vmpy <"vmpyweh", 0b101, 0b101, 1, 1, 1>;
-
-//Rdd=vmpywouh(Rss,Rtt)[:<<1][:rnd]:sat
-def M2_mmpyuh_s0: T_M2_vmpy <"vmpywouh", 0b010, 0b111, 0, 0, 1>;
-def M2_mmpyuh_s1: T_M2_vmpy <"vmpywouh", 0b110, 0b111, 1, 0, 1>;
-def M2_mmpyuh_rs0: T_M2_vmpy <"vmpywouh", 0b011, 0b111, 0, 1, 1>;
-def M2_mmpyuh_rs1: T_M2_vmpy <"vmpywouh", 0b111, 0b111, 1, 1, 1>;
-
-//Rdd=vmpyweuh(Rss,Rtt)[:<<1][:rnd]:sat
-def M2_mmpyul_s0: T_M2_vmpy <"vmpyweuh", 0b010, 0b101, 0, 0, 1>;
-def M2_mmpyul_s1: T_M2_vmpy <"vmpyweuh", 0b110, 0b101, 1, 0, 1>;
-def M2_mmpyul_rs0: T_M2_vmpy <"vmpyweuh", 0b011, 0b101, 0, 1, 1>;
-def M2_mmpyul_rs1: T_M2_vmpy <"vmpyweuh", 0b111, 0b101, 1, 1, 1>;
-}
-
-let hasNewValue = 1, opNewValue = 0 in
-class T_MType_mpy <string mnemonic, bits<4> RegTyBits, RegisterClass RC,
- bits<3> MajOp, bits<3> MinOp, bit isSat = 0, bit isRnd = 0,
- string op2Suffix = "", bit isRaw = 0, bit isHi = 0 >
- : MInst <(outs IntRegs:$dst), (ins RC:$src1, RC:$src2),
- "$dst = "#mnemonic
- #"($src1, $src2"#op2Suffix#")"
- #!if(MajOp{2}, ":<<1", "")
- #!if(isRnd, ":rnd", "")
- #!if(isSat, ":sat", "")
- #!if(isRaw, !if(isHi, ":raw:hi", ":raw:lo"), ""), [] > {
- bits<5> dst;
- bits<5> src1;
- bits<5> src2;
-
- let IClass = 0b1110;
-
- let Inst{27-24} = RegTyBits;
- let Inst{23-21} = MajOp;
- let Inst{20-16} = src1;
- let Inst{13} = 0b0;
- let Inst{12-8} = src2;
- let Inst{7-5} = MinOp;
- let Inst{4-0} = dst;
- }
-
-class T_MType_vrcmpy <string mnemonic, bits<3> MajOp, bits<3> MinOp, bit isHi>
- : T_MType_mpy <mnemonic, 0b1001, DoubleRegs, MajOp, MinOp, 1, 1, "", 1, isHi>;
-
-class T_MType_dd <string mnemonic, bits<3> MajOp, bits<3> MinOp,
- bit isSat = 0, bit isRnd = 0 >
- : T_MType_mpy <mnemonic, 0b1001, DoubleRegs, MajOp, MinOp, isSat, isRnd>;
-
-class T_MType_rr1 <string mnemonic, bits<3> MajOp, bits<3> MinOp,
- bit isSat = 0, bit isRnd = 0 >
- : T_MType_mpy<mnemonic, 0b1101, IntRegs, MajOp, MinOp, isSat, isRnd>;
-
-class T_MType_rr2 <string mnemonic, bits<3> MajOp, bits<3> MinOp,
- bit isSat = 0, bit isRnd = 0, string op2str = "" >
- : T_MType_mpy<mnemonic, 0b1101, IntRegs, MajOp, MinOp, isSat, isRnd, op2str>;
-
-def M2_vradduh : T_MType_dd <"vradduh", 0b000, 0b001, 0, 0>;
-def M2_vdmpyrs_s0 : T_MType_dd <"vdmpy", 0b000, 0b000, 1, 1>;
-def M2_vdmpyrs_s1 : T_MType_dd <"vdmpy", 0b100, 0b000, 1, 1>;
-
-let CextOpcode = "mpyi", InputType = "reg" in
-def M2_mpyi : T_MType_rr1 <"mpyi", 0b000, 0b000>, ImmRegRel;
-
-def M2_mpy_up : T_MType_rr1 <"mpy", 0b000, 0b001>;
-def M2_mpyu_up : T_MType_rr1 <"mpyu", 0b010, 0b001>;
-
-def M2_dpmpyss_rnd_s0 : T_MType_rr1 <"mpy", 0b001, 0b001, 0, 1>;
-
-def M2_vmpy2s_s0pack : T_MType_rr1 <"vmpyh", 0b001, 0b111, 1, 1>;
-def M2_vmpy2s_s1pack : T_MType_rr1 <"vmpyh", 0b101, 0b111, 1, 1>;
-
-def M2_hmmpyh_rs1 : T_MType_rr2 <"mpy", 0b101, 0b100, 1, 1, ".h">;
-def M2_hmmpyl_rs1 : T_MType_rr2 <"mpy", 0b111, 0b100, 1, 1, ".l">;
-
-def M2_cmpyrs_s0 : T_MType_rr2 <"cmpy", 0b001, 0b110, 1, 1>;
-def M2_cmpyrs_s1 : T_MType_rr2 <"cmpy", 0b101, 0b110, 1, 1>;
-def M2_cmpyrsc_s0 : T_MType_rr2 <"cmpy", 0b011, 0b110, 1, 1, "*">;
-def M2_cmpyrsc_s1 : T_MType_rr2 <"cmpy", 0b111, 0b110, 1, 1, "*">;
-
-// V4 Instructions
-def M2_vraddh : T_MType_dd <"vraddh", 0b001, 0b111, 0>;
-def M2_mpysu_up : T_MType_rr1 <"mpysu", 0b011, 0b001, 0>;
-def M2_mpy_up_s1 : T_MType_rr1 <"mpy", 0b101, 0b010, 0>;
-def M2_mpy_up_s1_sat : T_MType_rr1 <"mpy", 0b111, 0b000, 1>;
-
-def M2_hmmpyh_s1 : T_MType_rr2 <"mpy", 0b101, 0b000, 1, 0, ".h">;
-def M2_hmmpyl_s1 : T_MType_rr2 <"mpy", 0b101, 0b001, 1, 0, ".l">;
-
-let hasNewValue = 1, opNewValue = 0 in
-class T_MType_mpy_ri <bit isNeg, Operand ImmOp, list<dag> pattern>
- : MInst < (outs IntRegs:$Rd), (ins IntRegs:$Rs, ImmOp:$u8),
- "$Rd ="#!if(isNeg, "- ", "+ ")#"mpyi($Rs, #$u8)" ,
- pattern, "", M_tc_3x_SLOT23> {
- bits<5> Rd;
- bits<5> Rs;
- bits<8> u8;
-
- let IClass = 0b1110;
-
- let Inst{27-24} = 0b0000;
- let Inst{23} = isNeg;
- let Inst{13} = 0b0;
- let Inst{4-0} = Rd;
- let Inst{20-16} = Rs;
- let Inst{12-5} = u8;
- }
-
-let isExtendable = 1, opExtentBits = 8, opExtendable = 2 in
-def M2_mpysip : T_MType_mpy_ri <0, u8_0Ext, []>;
-
-def M2_mpysin : T_MType_mpy_ri <1, u8_0Imm, []>;
-
-// Assember mapped to M2_mpyi
-let isAsmParserOnly = 1 in
-def M2_mpyui : MInst<(outs IntRegs:$dst),
- (ins IntRegs:$src1, IntRegs:$src2),
- "$dst = mpyui($src1, $src2)">;
-
-// Rd=mpyi(Rs,#m9)
-// s9 is NOT the same as m9 - but it works.. so far.
-// Assembler maps to either Rd=+mpyi(Rs,#u8) or Rd=-mpyi(Rs,#u8)
-// depending on the value of m9. See Arch Spec.
-let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 9,
- CextOpcode = "mpyi", InputType = "imm", hasNewValue = 1,
- isAsmParserOnly = 1 in
-def M2_mpysmi : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s9_0Ext:$src2),
- "$dst = mpyi($src1, #$src2)", []>, ImmRegRel;
-
-let hasNewValue = 1, isExtendable = 1, opExtentBits = 8, opExtendable = 3,
- InputType = "imm" in
-class T_MType_acc_ri <string mnemonic, bits<3> MajOp, Operand ImmOp,
- list<dag> pattern = []>
- : MInst < (outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2, ImmOp:$src3),
- "$dst "#mnemonic#"($src2, #$src3)",
- pattern, "$src1 = $dst", M_tc_2_SLOT23> {
- bits<5> dst;
- bits<5> src2;
- bits<8> src3;
-
- let IClass = 0b1110;
-
- let Inst{27-26} = 0b00;
- let Inst{25-23} = MajOp;
- let Inst{20-16} = src2;
- let Inst{13} = 0b0;
- let Inst{12-5} = src3;
- let Inst{4-0} = dst;
- }
-
-let InputType = "reg", hasNewValue = 1 in
-class T_MType_acc_rr <string mnemonic, bits<3> MajOp, bits<3> MinOp,
- bit isSwap = 0, list<dag> pattern = [], bit hasNot = 0,
- bit isSat = 0, bit isShift = 0>
- : MInst < (outs IntRegs:$dst),
- (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
- "$dst "#mnemonic#"($src2, "#!if(hasNot, "~$src3)","$src3)")
- #!if(isShift, ":<<1", "")
- #!if(isSat, ":sat", ""),
- pattern, "$src1 = $dst", M_tc_2_SLOT23 > {
- bits<5> dst;
- bits<5> src2;
- bits<5> src3;
-
- let IClass = 0b1110;
-
- let Inst{27-24} = 0b1111;
- let Inst{23-21} = MajOp;
- let Inst{20-16} = !if(isSwap, src3, src2);
- let Inst{13} = 0b0;
- let Inst{12-8} = !if(isSwap, src2, src3);
- let Inst{7-5} = MinOp;
- let Inst{4-0} = dst;
- }
-
-let CextOpcode = "MPYI_acc", Itinerary = M_tc_3x_SLOT23 in {
- def M2_macsip : T_MType_acc_ri <"+= mpyi", 0b010, u8_0Ext, []>, ImmRegRel;
-
- def M2_maci : T_MType_acc_rr <"+= mpyi", 0b000, 0b000, 0, []>, ImmRegRel;
-}
-
-let CextOpcode = "ADD_acc" in {
- let isExtentSigned = 1 in
- def M2_accii : T_MType_acc_ri <"+= add", 0b100, s8_0Ext, []>, ImmRegRel;
-
- def M2_acci : T_MType_acc_rr <"+= add", 0b000, 0b001, 0, []>, ImmRegRel;
-}
-
-let CextOpcode = "SUB_acc" in {
- let isExtentSigned = 1 in
- def M2_naccii : T_MType_acc_ri <"-= add", 0b101, s8_0Ext>, ImmRegRel;
-
- def M2_nacci : T_MType_acc_rr <"-= add", 0b100, 0b001, 0>, ImmRegRel;
-}
-
-let Itinerary = M_tc_3x_SLOT23 in
-def M2_macsin : T_MType_acc_ri <"-= mpyi", 0b011, u8_0Ext>;
-
-def M2_xor_xacc : T_MType_acc_rr < "^= xor", 0b100, 0b011, 0>;
-def M2_subacc : T_MType_acc_rr <"+= sub", 0b000, 0b011, 1>;
-
-//===----------------------------------------------------------------------===//
-// Template Class -- XType Vector Instructions
-//===----------------------------------------------------------------------===//
-class T_XTYPE_Vect < string opc, bits<3> MajOp, bits<3> MinOp, bit isConj >
- : MInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
- "$Rdd = "#opc#"($Rss, $Rtt"#!if(isConj,"*)",")"),
- [] > {
- bits<5> Rdd;
- bits<5> Rss;
- bits<5> Rtt;
-
- let IClass = 0b1110;
-
- let Inst{27-24} = 0b1000;
- let Inst{23-21} = MajOp;
- let Inst{7-5} = MinOp;
- let Inst{4-0} = Rdd;
- let Inst{20-16} = Rss;
- let Inst{12-8} = Rtt;
- }
-
-class T_XTYPE_Vect_acc < string opc, bits<3> MajOp, bits<3> MinOp, bit isConj >
- : MInst <(outs DoubleRegs:$Rdd),
- (ins DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt),
- "$Rdd += "#opc#"($Rss, $Rtt"#!if(isConj,"*)",")"),
- [], "$dst2 = $Rdd",M_tc_3x_SLOT23 > {
- bits<5> Rdd;
- bits<5> Rss;
- bits<5> Rtt;
-
- let IClass = 0b1110;
-
- let Inst{27-24} = 0b1010;
- let Inst{23-21} = MajOp;
- let Inst{7-5} = MinOp;
- let Inst{4-0} = Rdd;
- let Inst{20-16} = Rss;
- let Inst{12-8} = Rtt;
- }
-
-class T_XTYPE_Vect_diff < bits<3> MajOp, string opc >
- : MInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rtt, DoubleRegs:$Rss),
- "$Rdd = "#opc#"($Rtt, $Rss)",
- [], "",M_tc_2_SLOT23 > {
- bits<5> Rdd;
- bits<5> Rss;
- bits<5> Rtt;
-
- let IClass = 0b1110;
-
- let Inst{27-24} = 0b1000;
- let Inst{23-21} = MajOp;
- let Inst{7-5} = 0b000;
- let Inst{4-0} = Rdd;
- let Inst{20-16} = Rss;
- let Inst{12-8} = Rtt;
- }
-
-// Vector reduce add unsigned bytes: Rdd32=vrmpybu(Rss32,Rtt32)
-def A2_vraddub: T_XTYPE_Vect <"vraddub", 0b010, 0b001, 0>;
-def A2_vraddub_acc: T_XTYPE_Vect_acc <"vraddub", 0b010, 0b001, 0>;
-
-// Vector sum of absolute differences unsigned bytes: Rdd=vrsadub(Rss,Rtt)
-def A2_vrsadub: T_XTYPE_Vect <"vrsadub", 0b010, 0b010, 0>;
-def A2_vrsadub_acc: T_XTYPE_Vect_acc <"vrsadub", 0b010, 0b010, 0>;
-
-// Vector absolute difference: Rdd=vabsdiffh(Rtt,Rss)
-def M2_vabsdiffh: T_XTYPE_Vect_diff<0b011, "vabsdiffh">;
-
-// Vector absolute difference words: Rdd=vabsdiffw(Rtt,Rss)
-def M2_vabsdiffw: T_XTYPE_Vect_diff<0b001, "vabsdiffw">;
-
-// Vector reduce complex multiply real or imaginary:
-// Rdd[+]=vrcmpy[ir](Rss,Rtt[*])
-def M2_vrcmpyi_s0: T_XTYPE_Vect <"vrcmpyi", 0b000, 0b000, 0>;
-def M2_vrcmpyi_s0c: T_XTYPE_Vect <"vrcmpyi", 0b010, 0b000, 1>;
-def M2_vrcmaci_s0: T_XTYPE_Vect_acc <"vrcmpyi", 0b000, 0b000, 0>;
-def M2_vrcmaci_s0c: T_XTYPE_Vect_acc <"vrcmpyi", 0b010, 0b000, 1>;
-
-def M2_vrcmpyr_s0: T_XTYPE_Vect <"vrcmpyr", 0b000, 0b001, 0>;
-def M2_vrcmpyr_s0c: T_XTYPE_Vect <"vrcmpyr", 0b011, 0b001, 1>;
-def M2_vrcmacr_s0: T_XTYPE_Vect_acc <"vrcmpyr", 0b000, 0b001, 0>;
-def M2_vrcmacr_s0c: T_XTYPE_Vect_acc <"vrcmpyr", 0b011, 0b001, 1>;
-
-// Vector reduce halfwords:
-// Rdd[+]=vrmpyh(Rss,Rtt)
-def M2_vrmpy_s0: T_XTYPE_Vect <"vrmpyh", 0b000, 0b010, 0>;
-def M2_vrmac_s0: T_XTYPE_Vect_acc <"vrmpyh", 0b000, 0b010, 0>;
-
-//===----------------------------------------------------------------------===//
-// Template Class -- Vector Multipy with accumulation.
-// Used for complex multiply real or imaginary, dual multiply and even halfwords
-//===----------------------------------------------------------------------===//
-let Defs = [USR_OVF] in
-class T_M2_vmpy_acc_sat < string opc, bits<3> MajOp, bits<3> MinOp,
- bit hasShift, bit isRnd >
- : MInst <(outs DoubleRegs:$Rxx),
- (ins DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt),
- "$Rxx += "#opc#"($Rss, $Rtt)"#!if(hasShift,":<<1","")
- #!if(isRnd,":rnd","")#":sat",
- [], "$dst2 = $Rxx",M_tc_3x_SLOT23 > {
- bits<5> Rxx;
- bits<5> Rss;
- bits<5> Rtt;
-
- let IClass = 0b1110;
-
- let Inst{27-24} = 0b1010;
- let Inst{23-21} = MajOp;
- let Inst{7-5} = MinOp;
- let Inst{4-0} = Rxx;
- let Inst{20-16} = Rss;
- let Inst{12-8} = Rtt;
- }
-
-class T_M2_vmpy_acc < string opc, bits<3> MajOp, bits<3> MinOp,
- bit hasShift, bit isRnd >
- : MInst <(outs DoubleRegs:$Rxx),
- (ins DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt),
- "$Rxx += "#opc#"($Rss, $Rtt)"#!if(hasShift,":<<1","")
- #!if(isRnd,":rnd",""),
- [], "$dst2 = $Rxx",M_tc_3x_SLOT23 > {
- bits<5> Rxx;
- bits<5> Rss;
- bits<5> Rtt;
-
- let IClass = 0b1110;
-
- let Inst{27-24} = 0b1010;
- let Inst{23-21} = MajOp;
- let Inst{7-5} = MinOp;
- let Inst{4-0} = Rxx;
- let Inst{20-16} = Rss;
- let Inst{12-8} = Rtt;
- }
-
-// Vector multiply word by signed half with accumulation
-// Rxx+=vmpyw[eo]h(Rss,Rtt)[:<<1][:rnd]:sat
-def M2_mmacls_s1: T_M2_vmpy_acc_sat <"vmpyweh", 0b100, 0b101, 1, 0>;
-def M2_mmacls_s0: T_M2_vmpy_acc_sat <"vmpyweh", 0b000, 0b101, 0, 0>;
-def M2_mmacls_rs1: T_M2_vmpy_acc_sat <"vmpyweh", 0b101, 0b101, 1, 1>;
-def M2_mmacls_rs0: T_M2_vmpy_acc_sat <"vmpyweh", 0b001, 0b101, 0, 1>;
-
-def M2_mmachs_s1: T_M2_vmpy_acc_sat <"vmpywoh", 0b100, 0b111, 1, 0>;
-def M2_mmachs_s0: T_M2_vmpy_acc_sat <"vmpywoh", 0b000, 0b111, 0, 0>;
-def M2_mmachs_rs1: T_M2_vmpy_acc_sat <"vmpywoh", 0b101, 0b111, 1, 1>;
-def M2_mmachs_rs0: T_M2_vmpy_acc_sat <"vmpywoh", 0b001, 0b111, 0, 1>;
-
-// Vector multiply word by unsigned half with accumulation
-// Rxx+=vmpyw[eo]uh(Rss,Rtt)[:<<1][:rnd]:sat
-def M2_mmaculs_s1: T_M2_vmpy_acc_sat <"vmpyweuh", 0b110, 0b101, 1, 0>;
-def M2_mmaculs_s0: T_M2_vmpy_acc_sat <"vmpyweuh", 0b010, 0b101, 0, 0>;
-def M2_mmaculs_rs1: T_M2_vmpy_acc_sat <"vmpyweuh", 0b111, 0b101, 1, 1>;
-def M2_mmaculs_rs0: T_M2_vmpy_acc_sat <"vmpyweuh", 0b011, 0b101, 0, 1>;
-
-def M2_mmacuhs_s1: T_M2_vmpy_acc_sat <"vmpywouh", 0b110, 0b111, 1, 0>;
-def M2_mmacuhs_s0: T_M2_vmpy_acc_sat <"vmpywouh", 0b010, 0b111, 0, 0>;
-def M2_mmacuhs_rs1: T_M2_vmpy_acc_sat <"vmpywouh", 0b111, 0b111, 1, 1>;
-def M2_mmacuhs_rs0: T_M2_vmpy_acc_sat <"vmpywouh", 0b011, 0b111, 0, 1>;
-
-// Vector multiply even halfwords with accumulation
-// Rxx+=vmpyeh(Rss,Rtt)[:<<1][:sat]
-def M2_vmac2es: T_M2_vmpy_acc <"vmpyeh", 0b001, 0b010, 0, 0>;
-def M2_vmac2es_s1: T_M2_vmpy_acc_sat <"vmpyeh", 0b100, 0b110, 1, 0>;
-def M2_vmac2es_s0: T_M2_vmpy_acc_sat <"vmpyeh", 0b000, 0b110, 0, 0>;
-
-// Vector dual multiply with accumulation
-// Rxx+=vdmpy(Rss,Rtt)[:sat]
-def M2_vdmacs_s1: T_M2_vmpy_acc_sat <"vdmpy", 0b100, 0b100, 1, 0>;
-def M2_vdmacs_s0: T_M2_vmpy_acc_sat <"vdmpy", 0b000, 0b100, 0, 0>;
-
-// Vector complex multiply real or imaginary with accumulation
-// Rxx+=vcmpy[ir](Rss,Rtt):sat
-def M2_vcmac_s0_sat_r: T_M2_vmpy_acc_sat <"vcmpyr", 0b001, 0b100, 0, 0>;
-def M2_vcmac_s0_sat_i: T_M2_vmpy_acc_sat <"vcmpyi", 0b010, 0b100, 0, 0>;
-
-//===----------------------------------------------------------------------===//
-// Template Class -- Multiply signed/unsigned halfwords with and without
-// saturation and rounding
-//===----------------------------------------------------------------------===//
-class T_M2_mpyd < bits<2> LHbits, bit isRnd, bit hasShift, bit isUnsigned >
- : MInst < (outs DoubleRegs:$Rdd), (ins IntRegs:$Rs, IntRegs:$Rt),
- "$Rdd = "#!if(isUnsigned,"mpyu","mpy")#"($Rs."#!if(LHbits{1},"h","l")
- #", $Rt."#!if(LHbits{0},"h)","l)")
- #!if(hasShift,":<<1","")
- #!if(isRnd,":rnd",""),
- [] > {
- bits<5> Rdd;
- bits<5> Rs;
- bits<5> Rt;
-
- let IClass = 0b1110;
-
- let Inst{27-24} = 0b0100;
- let Inst{23} = hasShift;
- let Inst{22} = isUnsigned;
- let Inst{21} = isRnd;
- let Inst{6-5} = LHbits;
- let Inst{4-0} = Rdd;
- let Inst{20-16} = Rs;
- let Inst{12-8} = Rt;
-}
-
-def M2_mpyd_hh_s0: T_M2_mpyd<0b11, 0, 0, 0>;
-def M2_mpyd_hl_s0: T_M2_mpyd<0b10, 0, 0, 0>;
-def M2_mpyd_lh_s0: T_M2_mpyd<0b01, 0, 0, 0>;
-def M2_mpyd_ll_s0: T_M2_mpyd<0b00, 0, 0, 0>;
-
-def M2_mpyd_hh_s1: T_M2_mpyd<0b11, 0, 1, 0>;
-def M2_mpyd_hl_s1: T_M2_mpyd<0b10, 0, 1, 0>;
-def M2_mpyd_lh_s1: T_M2_mpyd<0b01, 0, 1, 0>;
-def M2_mpyd_ll_s1: T_M2_mpyd<0b00, 0, 1, 0>;
-
-def M2_mpyd_rnd_hh_s0: T_M2_mpyd<0b11, 1, 0, 0>;
-def M2_mpyd_rnd_hl_s0: T_M2_mpyd<0b10, 1, 0, 0>;
-def M2_mpyd_rnd_lh_s0: T_M2_mpyd<0b01, 1, 0, 0>;
-def M2_mpyd_rnd_ll_s0: T_M2_mpyd<0b00, 1, 0, 0>;
-
-def M2_mpyd_rnd_hh_s1: T_M2_mpyd<0b11, 1, 1, 0>;
-def M2_mpyd_rnd_hl_s1: T_M2_mpyd<0b10, 1, 1, 0>;
-def M2_mpyd_rnd_lh_s1: T_M2_mpyd<0b01, 1, 1, 0>;
-def M2_mpyd_rnd_ll_s1: T_M2_mpyd<0b00, 1, 1, 0>;
-
-//Rdd=mpyu(Rs.[HL],Rt.[HL])[:<<1]
-def M2_mpyud_hh_s0: T_M2_mpyd<0b11, 0, 0, 1>;
-def M2_mpyud_hl_s0: T_M2_mpyd<0b10, 0, 0, 1>;
-def M2_mpyud_lh_s0: T_M2_mpyd<0b01, 0, 0, 1>;
-def M2_mpyud_ll_s0: T_M2_mpyd<0b00, 0, 0, 1>;
-
-def M2_mpyud_hh_s1: T_M2_mpyd<0b11, 0, 1, 1>;
-def M2_mpyud_hl_s1: T_M2_mpyd<0b10, 0, 1, 1>;
-def M2_mpyud_lh_s1: T_M2_mpyd<0b01, 0, 1, 1>;
-def M2_mpyud_ll_s1: T_M2_mpyd<0b00, 0, 1, 1>;
-
-//===----------------------------------------------------------------------===//
-// Template Class for xtype mpy:
-// Vector multiply
-// Complex multiply
-// multiply 32X32 and use full result
-//===----------------------------------------------------------------------===//
-let hasSideEffects = 0 in
-class T_XTYPE_mpy64 <string mnemonic, bits<3> MajOp, bits<3> MinOp,
- bit isSat, bit hasShift, bit isConj>
- : MInst <(outs DoubleRegs:$Rdd),
- (ins IntRegs:$Rs, IntRegs:$Rt),
- "$Rdd = "#mnemonic#"($Rs, $Rt"#!if(isConj,"*)",")")
- #!if(hasShift,":<<1","")
- #!if(isSat,":sat",""),
- [] > {
- bits<5> Rdd;
- bits<5> Rs;
- bits<5> Rt;
-
- let IClass = 0b1110;
-
- let Inst{27-24} = 0b0101;
- let Inst{23-21} = MajOp;
- let Inst{20-16} = Rs;
- let Inst{12-8} = Rt;
- let Inst{7-5} = MinOp;
- let Inst{4-0} = Rdd;
- }
-
-//===----------------------------------------------------------------------===//
-// Template Class for xtype mpy with accumulation into 64-bit:
-// Vector multiply
-// Complex multiply
-// multiply 32X32 and use full result
-//===----------------------------------------------------------------------===//
-class T_XTYPE_mpy64_acc <string op1, string op2, bits<3> MajOp, bits<3> MinOp,
- bit isSat, bit hasShift, bit isConj>
- : MInst <(outs DoubleRegs:$Rxx),
- (ins DoubleRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt),
- "$Rxx "#op2#"= "#op1#"($Rs, $Rt"#!if(isConj,"*)",")")
- #!if(hasShift,":<<1","")
- #!if(isSat,":sat",""),
-
- [] , "$dst2 = $Rxx" > {
- bits<5> Rxx;
- bits<5> Rs;
- bits<5> Rt;
-
- let IClass = 0b1110;
-
- let Inst{27-24} = 0b0111;
- let Inst{23-21} = MajOp;
- let Inst{20-16} = Rs;
- let Inst{12-8} = Rt;
- let Inst{7-5} = MinOp;
- let Inst{4-0} = Rxx;
- }
-
-// MPY - Multiply and use full result
-// Rdd = mpy[u](Rs,Rt)
-def M2_dpmpyss_s0 : T_XTYPE_mpy64 < "mpy", 0b000, 0b000, 0, 0, 0>;
-def M2_dpmpyuu_s0 : T_XTYPE_mpy64 < "mpyu", 0b010, 0b000, 0, 0, 0>;
-
-// Rxx[+-]= mpy[u](Rs,Rt)
-def M2_dpmpyss_acc_s0 : T_XTYPE_mpy64_acc < "mpy", "+", 0b000, 0b000, 0, 0, 0>;
-def M2_dpmpyss_nac_s0 : T_XTYPE_mpy64_acc < "mpy", "-", 0b001, 0b000, 0, 0, 0>;
-def M2_dpmpyuu_acc_s0 : T_XTYPE_mpy64_acc < "mpyu", "+", 0b010, 0b000, 0, 0, 0>;
-def M2_dpmpyuu_nac_s0 : T_XTYPE_mpy64_acc < "mpyu", "-", 0b011, 0b000, 0, 0, 0>;
-
-// Complex multiply real or imaginary
-// Rxx=cmpy[ir](Rs,Rt)
-def M2_cmpyi_s0 : T_XTYPE_mpy64 < "cmpyi", 0b000, 0b001, 0, 0, 0>;
-def M2_cmpyr_s0 : T_XTYPE_mpy64 < "cmpyr", 0b000, 0b010, 0, 0, 0>;
-
-// Rxx+=cmpy[ir](Rs,Rt)
-def M2_cmaci_s0 : T_XTYPE_mpy64_acc < "cmpyi", "+", 0b000, 0b001, 0, 0, 0>;
-def M2_cmacr_s0 : T_XTYPE_mpy64_acc < "cmpyr", "+", 0b000, 0b010, 0, 0, 0>;
-
-// Complex multiply
-// Rdd=cmpy(Rs,Rt)[:<<]:sat
-def M2_cmpys_s0 : T_XTYPE_mpy64 < "cmpy", 0b000, 0b110, 1, 0, 0>;
-def M2_cmpys_s1 : T_XTYPE_mpy64 < "cmpy", 0b100, 0b110, 1, 1, 0>;
-
-// Rdd=cmpy(Rs,Rt*)[:<<]:sat
-def M2_cmpysc_s0 : T_XTYPE_mpy64 < "cmpy", 0b010, 0b110, 1, 0, 1>;
-def M2_cmpysc_s1 : T_XTYPE_mpy64 < "cmpy", 0b110, 0b110, 1, 1, 1>;
-
-// Rxx[-+]=cmpy(Rs,Rt)[:<<1]:sat
-def M2_cmacs_s0 : T_XTYPE_mpy64_acc < "cmpy", "+", 0b000, 0b110, 1, 0, 0>;
-def M2_cnacs_s0 : T_XTYPE_mpy64_acc < "cmpy", "-", 0b000, 0b111, 1, 0, 0>;
-def M2_cmacs_s1 : T_XTYPE_mpy64_acc < "cmpy", "+", 0b100, 0b110, 1, 1, 0>;
-def M2_cnacs_s1 : T_XTYPE_mpy64_acc < "cmpy", "-", 0b100, 0b111, 1, 1, 0>;
-
-// Rxx[-+]=cmpy(Rs,Rt*)[:<<1]:sat
-def M2_cmacsc_s0 : T_XTYPE_mpy64_acc < "cmpy", "+", 0b010, 0b110, 1, 0, 1>;
-def M2_cnacsc_s0 : T_XTYPE_mpy64_acc < "cmpy", "-", 0b010, 0b111, 1, 0, 1>;
-def M2_cmacsc_s1 : T_XTYPE_mpy64_acc < "cmpy", "+", 0b110, 0b110, 1, 1, 1>;
-def M2_cnacsc_s1 : T_XTYPE_mpy64_acc < "cmpy", "-", 0b110, 0b111, 1, 1, 1>;
-
-// Vector multiply halfwords
-// Rdd=vmpyh(Rs,Rt)[:<<]:sat
-//let Defs = [USR_OVF] in {
- def M2_vmpy2s_s1 : T_XTYPE_mpy64 < "vmpyh", 0b100, 0b101, 1, 1, 0>;
- def M2_vmpy2s_s0 : T_XTYPE_mpy64 < "vmpyh", 0b000, 0b101, 1, 0, 0>;
-//}
-
-// Rxx+=vmpyh(Rs,Rt)[:<<1][:sat]
-def M2_vmac2 : T_XTYPE_mpy64_acc < "vmpyh", "+", 0b001, 0b001, 0, 0, 0>;
-def M2_vmac2s_s1 : T_XTYPE_mpy64_acc < "vmpyh", "+", 0b100, 0b101, 1, 1, 0>;
-def M2_vmac2s_s0 : T_XTYPE_mpy64_acc < "vmpyh", "+", 0b000, 0b101, 1, 0, 0>;
-
-//===----------------------------------------------------------------------===//
-// MTYPE/MPYH -
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// MTYPE/MPYS +
-//===----------------------------------------------------------------------===//
-//===----------------------------------------------------------------------===//
-// MTYPE/MPYS -
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// MTYPE/VB +
-//===----------------------------------------------------------------------===//
-//===----------------------------------------------------------------------===//
-// MTYPE/VB -
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// MTYPE/VH +
-//===----------------------------------------------------------------------===//
-//===----------------------------------------------------------------------===//
-// MTYPE/VH -
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// ST +
-//===----------------------------------------------------------------------===//
-///
-// Store doubleword.
-//===----------------------------------------------------------------------===//
-// Template class for non-predicated post increment stores with immediate offset
-//===----------------------------------------------------------------------===//
-let isPredicable = 1, hasSideEffects = 0, addrMode = PostInc in
-class T_store_pi <string mnemonic, RegisterClass RC, Operand ImmOp,
- bits<4> MajOp, bit isHalf >
- : STInst <(outs IntRegs:$_dst_),
- (ins IntRegs:$src1, ImmOp:$offset, RC:$src2),
- mnemonic#"($src1++#$offset) = $src2"#!if(isHalf, ".h", ""),
- [], "$src1 = $_dst_" >,
- AddrModeRel {
- bits<5> src1;
- bits<5> src2;
- bits<7> offset;
- bits<4> offsetBits;
-
- string ImmOpStr = !cast<string>(ImmOp);
- let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3},
- !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
- !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
- /* s4_0Imm */ offset{3-0})));
- // Store upper-half and store doubleword cannot be NV.
- let isNVStorable = !if (!eq(ImmOpStr, "s4_3Imm"), 0, !if(isHalf,0,1));
-
- let IClass = 0b1010;
-
- let Inst{27-25} = 0b101;
- let Inst{24-21} = MajOp;
- let Inst{20-16} = src1;
- let Inst{13} = 0b0;
- let Inst{12-8} = src2;
- let Inst{7} = 0b0;
- let Inst{6-3} = offsetBits;
- let Inst{1} = 0b0;
- }
-
-//===----------------------------------------------------------------------===//
-// Template class for predicated post increment stores with immediate offset
-//===----------------------------------------------------------------------===//
-let isPredicated = 1, hasSideEffects = 0, addrMode = PostInc in
-class T_pstore_pi <string mnemonic, RegisterClass RC, Operand ImmOp,
- bits<4> MajOp, bit isHalf, bit isPredNot, bit isPredNew>
- : STInst <(outs IntRegs:$_dst_),
- (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset, RC:$src3),
- !if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
- ") ")#mnemonic#"($src2++#$offset) = $src3"#!if(isHalf, ".h", ""),
- [], "$src2 = $_dst_" >,
- AddrModeRel {
- bits<2> src1;
- bits<5> src2;
- bits<7> offset;
- bits<5> src3;
- bits<4> offsetBits;
-
- string ImmOpStr = !cast<string>(ImmOp);
- let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3},
- !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
- !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
- /* s4_0Imm */ offset{3-0})));
-
- // Store upper-half and store doubleword cannot be NV.
- let isNVStorable = !if (!eq(ImmOpStr, "s4_3Imm"), 0, !if(isHalf,0,1));
- let isPredicatedNew = isPredNew;
- let isPredicatedFalse = isPredNot;
-
- let IClass = 0b1010;
-
- let Inst{27-25} = 0b101;
- let Inst{24-21} = MajOp;
- let Inst{20-16} = src2;
- let Inst{13} = 0b1;
- let Inst{12-8} = src3;
- let Inst{7} = isPredNew;
- let Inst{6-3} = offsetBits;
- let Inst{2} = isPredNot;
- let Inst{1-0} = src1;
- }
-
-multiclass ST_PostInc<string mnemonic, string BaseOp, RegisterClass RC,
- Operand ImmOp, bits<4> MajOp, bit isHalf = 0 > {
-
- let BaseOpcode = "POST_"#BaseOp in {
- def S2_#NAME#_pi : T_store_pi <mnemonic, RC, ImmOp, MajOp, isHalf>;
-
- // Predicated
- def S2_p#NAME#t_pi : T_pstore_pi <mnemonic, RC, ImmOp, MajOp, isHalf, 0, 0>;
- def S2_p#NAME#f_pi : T_pstore_pi <mnemonic, RC, ImmOp, MajOp, isHalf, 1, 0>;
-
- // Predicated new
- def S2_p#NAME#tnew_pi : T_pstore_pi <mnemonic, RC, ImmOp, MajOp,
- isHalf, 0, 1>;
- def S2_p#NAME#fnew_pi : T_pstore_pi <mnemonic, RC, ImmOp, MajOp,
- isHalf, 1, 1>;
- }
-}
-
-let accessSize = ByteAccess in
-defm storerb: ST_PostInc <"memb", "STrib", IntRegs, s4_0Imm, 0b1000>;
-
-let accessSize = HalfWordAccess in
-defm storerh: ST_PostInc <"memh", "STrih", IntRegs, s4_1Imm, 0b1010>;
-
-let accessSize = WordAccess in
-defm storeri: ST_PostInc <"memw", "STriw", IntRegs, s4_2Imm, 0b1100>;
-
-let accessSize = DoubleWordAccess in
-defm storerd: ST_PostInc <"memd", "STrid", DoubleRegs, s4_3Imm, 0b1110>;
-
-let accessSize = HalfWordAccess, isNVStorable = 0 in
-defm storerf: ST_PostInc <"memh", "STrih_H", IntRegs, s4_1Imm, 0b1011, 1>;
-
-//===----------------------------------------------------------------------===//
-// Template class for post increment stores with register offset.
-//===----------------------------------------------------------------------===//
-class T_store_pr <string mnemonic, RegisterClass RC, bits<3> MajOp,
- MemAccessSize AccessSz, bit isHalf = 0>
- : STInst <(outs IntRegs:$_dst_),
- (ins IntRegs:$src1, ModRegs:$src2, RC:$src3),
- mnemonic#"($src1++$src2) = $src3"#!if(isHalf, ".h", ""),
- [], "$src1 = $_dst_" > {
- bits<5> src1;
- bits<1> src2;
- bits<5> src3;
- let accessSize = AccessSz;
-
- // Store upper-half and store doubleword cannot be NV.
- let isNVStorable = !if(!eq(mnemonic,"memd"), 0, !if(isHalf,0,1));
-
- let IClass = 0b1010;
-
- let Inst{27-24} = 0b1101;
- let Inst{23-21} = MajOp;
- let Inst{20-16} = src1;
- let Inst{13} = src2;
- let Inst{12-8} = src3;
- let Inst{7} = 0b0;
- }
-
-def S2_storerb_pr : T_store_pr<"memb", IntRegs, 0b000, ByteAccess>;
-def S2_storerh_pr : T_store_pr<"memh", IntRegs, 0b010, HalfWordAccess>;
-def S2_storeri_pr : T_store_pr<"memw", IntRegs, 0b100, WordAccess>;
-def S2_storerd_pr : T_store_pr<"memd", DoubleRegs, 0b110, DoubleWordAccess>;
-def S2_storerf_pr : T_store_pr<"memh", IntRegs, 0b011, HalfWordAccess, 1>;
-
-let opExtendable = 1, isExtentSigned = 1, isPredicable = 1 in
-class T_store_io <string mnemonic, RegisterClass RC, Operand ImmOp,
- bits<3> MajOp, bit isH = 0>
- : STInst <(outs),
- (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
- mnemonic#"($src1+#$src2) = $src3"#!if(isH,".h","")>,
- AddrModeRel, ImmRegRel {
- bits<5> src1;
- bits<14> src2; // Actual address offset
- bits<5> src3;
- bits<11> offsetBits; // Represents offset encoding
-
- string ImmOpStr = !cast<string>(ImmOp);
-
- let opExtentBits = !if (!eq(ImmOpStr, "s11_3Ext"), 14,
- !if (!eq(ImmOpStr, "s11_2Ext"), 13,
- !if (!eq(ImmOpStr, "s11_1Ext"), 12,
- /* s11_0Ext */ 11)));
- let offsetBits = !if (!eq(ImmOpStr, "s11_3Ext"), src2{13-3},
- !if (!eq(ImmOpStr, "s11_2Ext"), src2{12-2},
- !if (!eq(ImmOpStr, "s11_1Ext"), src2{11-1},
- /* s11_0Ext */ src2{10-0})));
- // Store upper-half and store doubleword cannot be NV.
- let isNVStorable = !if (!eq(mnemonic, "memd"), 0, !if(isH,0,1));
- let IClass = 0b1010;
-
- let Inst{27} = 0b0;
- let Inst{26-25} = offsetBits{10-9};
- let Inst{24} = 0b1;
- let Inst{23-21} = MajOp;
- let Inst{20-16} = src1;
- let Inst{13} = offsetBits{8};
- let Inst{12-8} = src3;
- let Inst{7-0} = offsetBits{7-0};
- }
-
-let opExtendable = 2, isPredicated = 1 in
-class T_pstore_io <string mnemonic, RegisterClass RC, Operand ImmOp,
- bits<3>MajOp, bit PredNot, bit isPredNew, bit isH = 0>
- : STInst <(outs),
- (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4),
- !if(PredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
- ") ")#mnemonic#"($src2+#$src3) = $src4"#!if(isH,".h",""),
- [],"",V2LDST_tc_st_SLOT01 >,
- AddrModeRel, ImmRegRel {
- bits<2> src1;
- bits<5> src2;
- bits<9> src3; // Actual address offset
- bits<5> src4;
- bits<6> offsetBits; // Represents offset encoding
-
- let isPredicatedNew = isPredNew;
- let isPredicatedFalse = PredNot;
-
- string ImmOpStr = !cast<string>(ImmOp);
- let opExtentBits = !if (!eq(ImmOpStr, "u6_3Ext"), 9,
- !if (!eq(ImmOpStr, "u6_2Ext"), 8,
- !if (!eq(ImmOpStr, "u6_1Ext"), 7,
- /* u6_0Ext */ 6)));
- let offsetBits = !if (!eq(ImmOpStr, "u6_3Ext"), src3{8-3},
- !if (!eq(ImmOpStr, "u6_2Ext"), src3{7-2},
- !if (!eq(ImmOpStr, "u6_1Ext"), src3{6-1},
- /* u6_0Ext */ src3{5-0})));
- // Store upper-half and store doubleword cannot be NV.
- let isNVStorable = !if (!eq(mnemonic, "memd"), 0, !if(isH,0,1));
-
- let IClass = 0b0100;
-
- let Inst{27} = 0b0;
- let Inst{26} = PredNot;
- let Inst{25} = isPredNew;
- let Inst{24} = 0b0;
- let Inst{23-21} = MajOp;
- let Inst{20-16} = src2;
- let Inst{13} = offsetBits{5};
- let Inst{12-8} = src4;
- let Inst{7-3} = offsetBits{4-0};
- let Inst{1-0} = src1;
- }
-
-let isExtendable = 1, hasSideEffects = 0 in
-multiclass ST_Idxd<string mnemonic, string CextOp, RegisterClass RC,
- Operand ImmOp, Operand predImmOp, bits<3> MajOp, bit isH = 0> {
- let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
- def S2_#NAME#_io : T_store_io <mnemonic, RC, ImmOp, MajOp, isH>;
-
- // Predicated
- def S2_p#NAME#t_io : T_pstore_io<mnemonic, RC, predImmOp, MajOp, 0, 0, isH>;
- def S2_p#NAME#f_io : T_pstore_io<mnemonic, RC, predImmOp, MajOp, 1, 0, isH>;
-
- // Predicated new
- def S4_p#NAME#tnew_io : T_pstore_io <mnemonic, RC, predImmOp,
- MajOp, 0, 1, isH>;
- def S4_p#NAME#fnew_io : T_pstore_io <mnemonic, RC, predImmOp,
- MajOp, 1, 1, isH>;
- }
-}
-
-let addrMode = BaseImmOffset, InputType = "imm" in {
- let accessSize = ByteAccess in
- defm storerb: ST_Idxd < "memb", "STrib", IntRegs, s11_0Ext, u6_0Ext, 0b000>;
-
- let accessSize = HalfWordAccess, opExtentAlign = 1 in
- defm storerh: ST_Idxd < "memh", "STrih", IntRegs, s11_1Ext, u6_1Ext, 0b010>;
-
- let accessSize = WordAccess, opExtentAlign = 2 in
- defm storeri: ST_Idxd < "memw", "STriw", IntRegs, s11_2Ext, u6_2Ext, 0b100>;
-
- let accessSize = DoubleWordAccess, isNVStorable = 0, opExtentAlign = 3 in
- defm storerd: ST_Idxd < "memd", "STrid", DoubleRegs, s11_3Ext,
- u6_3Ext, 0b110>;
-
- let accessSize = HalfWordAccess, opExtentAlign = 1 in
- defm storerf: ST_Idxd < "memh", "STrif", IntRegs, s11_1Ext,
- u6_1Ext, 0b011, 1>;
-}
-
-// Store predicate.
-let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 13,
- isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in
-def STriw_pred : STInst<(outs),
- (ins IntRegs:$addr, s11_2Ext:$off, PredRegs:$src1),
- ".error \"should not emit\"", []>;
-// Store modifier.
-let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 13,
- isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in
-def STriw_mod : STInst<(outs),
- (ins IntRegs:$addr, s11_2Ext:$off, ModRegs:$src1),
- ".error \"should not emit\"", []>;
-
-// S2_allocframe: Allocate stack frame.
-let Defs = [R29, R30], Uses = [R29, R31, R30],
- hasSideEffects = 0, accessSize = DoubleWordAccess in
-def S2_allocframe: ST0Inst <
- (outs), (ins u11_3Imm:$u11_3),
- "allocframe(#$u11_3)" > {
- bits<14> u11_3;
-
- let IClass = 0b1010;
- let Inst{27-16} = 0b000010011101;
- let Inst{13-11} = 0b000;
- let Inst{10-0} = u11_3{13-3};
- }
-
-// S2_storer[bhwdf]_pci: Store byte/half/word/double.
-// S2_storer[bhwdf]_pci -> S2_storerbnew_pci
-let Uses = [CS], addrMode = PostInc in
-class T_store_pci <string mnemonic, RegisterClass RC,
- Operand Imm, bits<4>MajOp,
- MemAccessSize AlignSize, string RegSrc = "Rt">
- : STInst <(outs IntRegs:$_dst_),
- (ins IntRegs:$Rz, Imm:$offset, ModRegs:$Mu, RC:$Rt),
- #mnemonic#"($Rz ++ #$offset:circ($Mu)) = $"#RegSrc#"",
- [] ,
- "$Rz = $_dst_" > {
- bits<5> Rz;
- bits<7> offset;
- bits<1> Mu;
- bits<5> Rt;
- let accessSize = AlignSize;
- let isNVStorable = !if(!eq(mnemonic,"memd"), 0,
- !if(!eq(RegSrc,"Rt.h"), 0, 1));
-
- let IClass = 0b1010;
- let Inst{27-25} = 0b100;
- let Inst{24-21} = MajOp;
- let Inst{20-16} = Rz;
- let Inst{13} = Mu;
- let Inst{12-8} = Rt;
- let Inst{7} = 0b0;
- let Inst{6-3} =
- !if (!eq(!cast<string>(AlignSize), "DoubleWordAccess"), offset{6-3},
- !if (!eq(!cast<string>(AlignSize), "WordAccess"), offset{5-2},
- !if (!eq(!cast<string>(AlignSize), "HalfWordAccess"), offset{4-1},
- /* ByteAccess */ offset{3-0})));
- let Inst{1} = 0b0;
- }
-
-def S2_storerb_pci : T_store_pci<"memb", IntRegs, s4_0Imm, 0b1000,
- ByteAccess>;
-def S2_storerh_pci : T_store_pci<"memh", IntRegs, s4_1Imm, 0b1010,
- HalfWordAccess>;
-def S2_storerf_pci : T_store_pci<"memh", IntRegs, s4_1Imm, 0b1011,
- HalfWordAccess, "Rt.h">;
-def S2_storeri_pci : T_store_pci<"memw", IntRegs, s4_2Imm, 0b1100,
- WordAccess>;
-def S2_storerd_pci : T_store_pci<"memd", DoubleRegs, s4_3Imm, 0b1110,
- DoubleWordAccess>;
-
-let Uses = [CS], isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 4,
- addrMode = PostInc in
-class T_storenew_pci <string mnemonic, Operand Imm,
- bits<2>MajOp, MemAccessSize AlignSize>
- : NVInst < (outs IntRegs:$_dst_),
- (ins IntRegs:$Rz, Imm:$offset, ModRegs:$Mu, IntRegs:$Nt),
- #mnemonic#"($Rz ++ #$offset:circ($Mu)) = $Nt.new",
- [],
- "$Rz = $_dst_"> {
- bits<5> Rz;
- bits<6> offset;
- bits<1> Mu;
- bits<3> Nt;
-
- let accessSize = AlignSize;
-
- let IClass = 0b1010;
- let Inst{27-21} = 0b1001101;
- let Inst{20-16} = Rz;
- let Inst{13} = Mu;
- let Inst{12-11} = MajOp;
- let Inst{10-8} = Nt;
- let Inst{7} = 0b0;
- let Inst{6-3} =
- !if (!eq(!cast<string>(AlignSize), "WordAccess"), offset{5-2},
- !if (!eq(!cast<string>(AlignSize), "HalfWordAccess"), offset{4-1},
- /* ByteAccess */ offset{3-0}));
- let Inst{1} = 0b0;
- }
-
-def S2_storerbnew_pci : T_storenew_pci <"memb", s4_0Imm, 0b00, ByteAccess>;
-def S2_storerhnew_pci : T_storenew_pci <"memh", s4_1Imm, 0b01, HalfWordAccess>;
-def S2_storerinew_pci : T_storenew_pci <"memw", s4_2Imm, 0b10, WordAccess>;
-
-//===----------------------------------------------------------------------===//
-// Circular stores with auto-increment register
-//===----------------------------------------------------------------------===//
-let Uses = [CS], addrMode = PostInc in
-class T_store_pcr <string mnemonic, RegisterClass RC, bits<4>MajOp,
- MemAccessSize AlignSize, string RegSrc = "Rt">
- : STInst <(outs IntRegs:$_dst_),
- (ins IntRegs:$Rz, ModRegs:$Mu, RC:$Rt),
- #mnemonic#"($Rz ++ I:circ($Mu)) = $"#RegSrc#"",
- [],
- "$Rz = $_dst_" > {
- bits<5> Rz;
- bits<1> Mu;
- bits<5> Rt;
-
- let accessSize = AlignSize;
- let isNVStorable = !if(!eq(mnemonic,"memd"), 0,
- !if(!eq(RegSrc,"Rt.h"), 0, 1));
-
- let IClass = 0b1010;
- let Inst{27-25} = 0b100;
- let Inst{24-21} = MajOp;
- let Inst{20-16} = Rz;
- let Inst{13} = Mu;
- let Inst{12-8} = Rt;
- let Inst{7} = 0b0;
- let Inst{1} = 0b1;
- }
-
-def S2_storerb_pcr : T_store_pcr<"memb", IntRegs, 0b1000, ByteAccess>;
-def S2_storerh_pcr : T_store_pcr<"memh", IntRegs, 0b1010, HalfWordAccess>;
-def S2_storeri_pcr : T_store_pcr<"memw", IntRegs, 0b1100, WordAccess>;
-def S2_storerd_pcr : T_store_pcr<"memd", DoubleRegs, 0b1110, DoubleWordAccess>;
-def S2_storerf_pcr : T_store_pcr<"memh", IntRegs, 0b1011,
- HalfWordAccess, "Rt.h">;
-
-//===----------------------------------------------------------------------===//
-// Circular .new stores with auto-increment register
-//===----------------------------------------------------------------------===//
-let Uses = [CS], isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 3,
- addrMode = PostInc in
-class T_storenew_pcr <string mnemonic, bits<2>MajOp,
- MemAccessSize AlignSize>
- : NVInst <(outs IntRegs:$_dst_),
- (ins IntRegs:$Rz, ModRegs:$Mu, IntRegs:$Nt),
- #mnemonic#"($Rz ++ I:circ($Mu)) = $Nt.new" ,
- [] ,
- "$Rz = $_dst_"> {
- bits<5> Rz;
- bits<1> Mu;
- bits<3> Nt;
-
- let accessSize = AlignSize;
-
- let IClass = 0b1010;
- let Inst{27-21} = 0b1001101;
- let Inst{20-16} = Rz;
- let Inst{13} = Mu;
- let Inst{12-11} = MajOp;
- let Inst{10-8} = Nt;
- let Inst{7} = 0b0;
- let Inst{1} = 0b1;
- }
-
-def S2_storerbnew_pcr : T_storenew_pcr <"memb", 0b00, ByteAccess>;
-def S2_storerhnew_pcr : T_storenew_pcr <"memh", 0b01, HalfWordAccess>;
-def S2_storerinew_pcr : T_storenew_pcr <"memw", 0b10, WordAccess>;
-
-//===----------------------------------------------------------------------===//
-// Bit-reversed stores with auto-increment register
-//===----------------------------------------------------------------------===//
-let hasSideEffects = 0, addrMode = PostInc in
-class T_store_pbr<string mnemonic, RegisterClass RC,
- MemAccessSize addrSize, bits<3> majOp,
- bit isHalf = 0>
- : STInst
- <(outs IntRegs:$_dst_),
- (ins IntRegs:$Rz, ModRegs:$Mu, RC:$src),
- #mnemonic#"($Rz ++ $Mu:brev) = $src"#!if (!eq(isHalf, 1), ".h", ""),
- [], "$Rz = $_dst_" > {
-
- let accessSize = addrSize;
-
- bits<5> Rz;
- bits<1> Mu;
- bits<5> src;
-
- let IClass = 0b1010;
-
- let Inst{27-24} = 0b1111;
- let Inst{23-21} = majOp;
- let Inst{7} = 0b0;
- let Inst{20-16} = Rz;
- let Inst{13} = Mu;
- let Inst{12-8} = src;
- }
-
-let isNVStorable = 1 in {
- let BaseOpcode = "S2_storerb_pbr" in
- def S2_storerb_pbr : T_store_pbr<"memb", IntRegs, ByteAccess,
- 0b000>, NewValueRel;
- let BaseOpcode = "S2_storerh_pbr" in
- def S2_storerh_pbr : T_store_pbr<"memh", IntRegs, HalfWordAccess,
- 0b010>, NewValueRel;
- let BaseOpcode = "S2_storeri_pbr" in
- def S2_storeri_pbr : T_store_pbr<"memw", IntRegs, WordAccess,
- 0b100>, NewValueRel;
-}
-
-def S2_storerf_pbr : T_store_pbr<"memh", IntRegs, HalfWordAccess, 0b011, 1>;
-def S2_storerd_pbr : T_store_pbr<"memd", DoubleRegs, DoubleWordAccess, 0b110>;
-
-//===----------------------------------------------------------------------===//
-// Bit-reversed .new stores with auto-increment register
-//===----------------------------------------------------------------------===//
-let isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 3,
- hasSideEffects = 0, addrMode = PostInc in
-class T_storenew_pbr<string mnemonic, MemAccessSize addrSize, bits<2> majOp>
- : NVInst <(outs IntRegs:$_dst_),
- (ins IntRegs:$Rz, ModRegs:$Mu, IntRegs:$Nt),
- #mnemonic#"($Rz ++ $Mu:brev) = $Nt.new", [],
- "$Rz = $_dst_">, NewValueRel {
- let accessSize = addrSize;
- bits<5> Rz;
- bits<1> Mu;
- bits<3> Nt;
-
- let IClass = 0b1010;
-
- let Inst{27-21} = 0b1111101;
- let Inst{12-11} = majOp;
- let Inst{7} = 0b0;
- let Inst{20-16} = Rz;
- let Inst{13} = Mu;
- let Inst{10-8} = Nt;
- }
-
-let BaseOpcode = "S2_storerb_pbr" in
-def S2_storerbnew_pbr : T_storenew_pbr<"memb", ByteAccess, 0b00>;
-
-let BaseOpcode = "S2_storerh_pbr" in
-def S2_storerhnew_pbr : T_storenew_pbr<"memh", HalfWordAccess, 0b01>;
-
-let BaseOpcode = "S2_storeri_pbr" in
-def S2_storerinew_pbr : T_storenew_pbr<"memw", WordAccess, 0b10>;
-
-//===----------------------------------------------------------------------===//
-// ST -
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// Template class for S_2op instructions.
-//===----------------------------------------------------------------------===//
-let hasSideEffects = 0 in
-class T_S2op_1 <string mnemonic, bits<4> RegTyBits, RegisterClass RCOut,
- RegisterClass RCIn, bits<2> MajOp, bits<3> MinOp, bit isSat>
- : SInst <(outs RCOut:$dst), (ins RCIn:$src),
- "$dst = "#mnemonic#"($src)"#!if(isSat, ":sat", ""),
- [], "", S_2op_tc_1_SLOT23 > {
- bits<5> dst;
- bits<5> src;
-
- let IClass = 0b1000;
-
- let Inst{27-24} = RegTyBits;
- let Inst{23-22} = MajOp;
- let Inst{21} = 0b0;
- let Inst{20-16} = src;
- let Inst{7-5} = MinOp;
- let Inst{4-0} = dst;
- }
-
-class T_S2op_1_di <string mnemonic, bits<2> MajOp, bits<3> MinOp>
- : T_S2op_1 <mnemonic, 0b0100, DoubleRegs, IntRegs, MajOp, MinOp, 0>;
-
-let hasNewValue = 1 in
-class T_S2op_1_id <string mnemonic, bits<2> MajOp, bits<3> MinOp, bit isSat = 0>
- : T_S2op_1 <mnemonic, 0b1000, IntRegs, DoubleRegs, MajOp, MinOp, isSat>;
-
-let hasNewValue = 1 in
-class T_S2op_1_ii <string mnemonic, bits<2> MajOp, bits<3> MinOp, bit isSat = 0>
- : T_S2op_1 <mnemonic, 0b1100, IntRegs, IntRegs, MajOp, MinOp, isSat>;
-
-// Vector sign/zero extend
-let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
- def S2_vsxtbh : T_S2op_1_di <"vsxtbh", 0b00, 0b000>;
- def S2_vsxthw : T_S2op_1_di <"vsxthw", 0b00, 0b100>;
- def S2_vzxtbh : T_S2op_1_di <"vzxtbh", 0b00, 0b010>;
- def S2_vzxthw : T_S2op_1_di <"vzxthw", 0b00, 0b110>;
-}
-
-// Vector splat bytes/halfwords
-let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
- def S2_vsplatrb : T_S2op_1_ii <"vsplatb", 0b01, 0b111>;
- def S2_vsplatrh : T_S2op_1_di <"vsplath", 0b01, 0b010>;
-}
-
-// Sign extend word to doubleword
-def A2_sxtw : T_S2op_1_di <"sxtw", 0b01, 0b000>;
-
-// Vector saturate and pack
-let Defs = [USR_OVF] in {
- def S2_svsathb : T_S2op_1_ii <"vsathb", 0b10, 0b000>;
- def S2_svsathub : T_S2op_1_ii <"vsathub", 0b10, 0b010>;
- def S2_vsathb : T_S2op_1_id <"vsathb", 0b00, 0b110>;
- def S2_vsathub : T_S2op_1_id <"vsathub", 0b00, 0b000>;
- def S2_vsatwh : T_S2op_1_id <"vsatwh", 0b00, 0b010>;
- def S2_vsatwuh : T_S2op_1_id <"vsatwuh", 0b00, 0b100>;
-}
-
-// Vector truncate
-def S2_vtrunohb : T_S2op_1_id <"vtrunohb", 0b10, 0b000>;
-def S2_vtrunehb : T_S2op_1_id <"vtrunehb", 0b10, 0b010>;
-
-// Swizzle the bytes of a word
-def A2_swiz : T_S2op_1_ii <"swiz", 0b10, 0b111>;
-
-// Saturate
-let Defs = [USR_OVF] in {
- def A2_sat : T_S2op_1_id <"sat", 0b11, 0b000>;
- def A2_satb : T_S2op_1_ii <"satb", 0b11, 0b111>;
- def A2_satub : T_S2op_1_ii <"satub", 0b11, 0b110>;
- def A2_sath : T_S2op_1_ii <"sath", 0b11, 0b100>;
- def A2_satuh : T_S2op_1_ii <"satuh", 0b11, 0b101>;
- def A2_roundsat : T_S2op_1_id <"round", 0b11, 0b001, 0b1>;
-}
-
-let Itinerary = S_2op_tc_2_SLOT23 in {
- // Vector round and pack
- def S2_vrndpackwh : T_S2op_1_id <"vrndwh", 0b10, 0b100>;
-
- let Defs = [USR_OVF] in
- def S2_vrndpackwhs : T_S2op_1_id <"vrndwh", 0b10, 0b110, 1>;
-
- // Bit reverse
- def S2_brev : T_S2op_1_ii <"brev", 0b01, 0b110>;
-
- // Absolute value word
- def A2_abs : T_S2op_1_ii <"abs", 0b10, 0b100>;
-
- let Defs = [USR_OVF] in
- def A2_abssat : T_S2op_1_ii <"abs", 0b10, 0b101, 1>;
-
- // Negate with saturation
- let Defs = [USR_OVF] in
- def A2_negsat : T_S2op_1_ii <"neg", 0b10, 0b110, 1>;
-}
-
-class T_S2op_2 <string mnemonic, bits<4> RegTyBits, RegisterClass RCOut,
- RegisterClass RCIn, bits<3> MajOp, bits<3> MinOp,
- bit isSat, bit isRnd, list<dag> pattern = []>
- : SInst <(outs RCOut:$dst),
- (ins RCIn:$src, u5_0Imm:$u5),
- "$dst = "#mnemonic#"($src, #$u5)"#!if(isSat, ":sat", "")
- #!if(isRnd, ":rnd", ""),
- pattern, "", S_2op_tc_2_SLOT23> {
- bits<5> dst;
- bits<5> src;
- bits<5> u5;
-
- let IClass = 0b1000;
-
- let Inst{27-24} = RegTyBits;
- let Inst{23-21} = MajOp;
- let Inst{20-16} = src;
- let Inst{13} = 0b0;
- let Inst{12-8} = u5;
- let Inst{7-5} = MinOp;
- let Inst{4-0} = dst;
- }
-
-class T_S2op_2_di <string mnemonic, bits<3> MajOp, bits<3> MinOp>
- : T_S2op_2 <mnemonic, 0b1000, DoubleRegs, IntRegs, MajOp, MinOp, 0, 0>;
-
-let hasNewValue = 1 in
-class T_S2op_2_id <string mnemonic, bits<3> MajOp, bits<3> MinOp>
- : T_S2op_2 <mnemonic, 0b1000, IntRegs, DoubleRegs, MajOp, MinOp, 0, 0>;
-
-let hasNewValue = 1 in
-class T_S2op_2_ii <string mnemonic, bits<3> MajOp, bits<3> MinOp,
- bit isSat = 0, bit isRnd = 0, list<dag> pattern = []>
- : T_S2op_2 <mnemonic, 0b1100, IntRegs, IntRegs, MajOp, MinOp,
- isSat, isRnd, pattern>;
-
-class T_S2op_shift <string mnemonic, bits<3> MajOp, bits<3> MinOp, SDNode OpNd>
- : T_S2op_2_ii <mnemonic, MajOp, MinOp, 0, 0, []>;
-
-// Vector arithmetic shift right by immediate with truncate and pack
-def S2_asr_i_svw_trun : T_S2op_2_id <"vasrw", 0b110, 0b010>;
-
-// Arithmetic/logical shift right/left by immediate
-let Itinerary = S_2op_tc_1_SLOT23 in {
- def S2_asr_i_r : T_S2op_shift <"asr", 0b000, 0b000, sra>;
- def S2_lsr_i_r : T_S2op_shift <"lsr", 0b000, 0b001, srl>;
- def S2_asl_i_r : T_S2op_shift <"asl", 0b000, 0b010, shl>;
-}
-
-// Shift left by immediate with saturation
-let Defs = [USR_OVF] in
-def S2_asl_i_r_sat : T_S2op_2_ii <"asl", 0b010, 0b010, 1>;
-
-// Shift right with round
-def S2_asr_i_r_rnd : T_S2op_2_ii <"asr", 0b010, 0b000, 0, 1>;
-
-let isAsmParserOnly = 1 in
-def S2_asr_i_r_rnd_goodsyntax
- : SInst <(outs IntRegs:$dst), (ins IntRegs:$src, u5_0Imm:$u5),
- "$dst = asrrnd($src, #$u5)",
- [], "", S_2op_tc_1_SLOT23>;
-
-let isAsmParserOnly = 1 in
-def A2_not: ALU32_rr<(outs IntRegs:$dst),(ins IntRegs:$src),
- "$dst = not($src)">;
-
-class T_S2op_3<string opc, bits<2>MajOp, bits<3>minOp, bits<1> sat = 0>
- : SInst<(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss),
- "$Rdd = "#opc#"($Rss)"#!if(!eq(sat, 1),":sat","")> {
- bits<5> Rss;
- bits<5> Rdd;
- let IClass = 0b1000;
- let Inst{27-24} = 0;
- let Inst{23-22} = MajOp;
- let Inst{20-16} = Rss;
- let Inst{7-5} = minOp;
- let Inst{4-0} = Rdd;
-}
-
-def A2_absp : T_S2op_3 <"abs", 0b10, 0b110>;
-def A2_negp : T_S2op_3 <"neg", 0b10, 0b101>;
-def A2_notp : T_S2op_3 <"not", 0b10, 0b100>;
-
-// Innterleave/deinterleave
-def S2_interleave : T_S2op_3 <"interleave", 0b11, 0b101>;
-def S2_deinterleave : T_S2op_3 <"deinterleave", 0b11, 0b100>;
-
-// Vector Complex conjugate
-def A2_vconj : T_S2op_3 <"vconj", 0b10, 0b111, 1>;
-
-// Vector saturate without pack
-def S2_vsathb_nopack : T_S2op_3 <"vsathb", 0b00, 0b111>;
-def S2_vsathub_nopack : T_S2op_3 <"vsathub", 0b00, 0b100>;
-def S2_vsatwh_nopack : T_S2op_3 <"vsatwh", 0b00, 0b110>;
-def S2_vsatwuh_nopack : T_S2op_3 <"vsatwuh", 0b00, 0b101>;
-
-// Vector absolute value halfwords with and without saturation
-// Rdd64=vabsh(Rss64)[:sat]
-def A2_vabsh : T_S2op_3 <"vabsh", 0b01, 0b100>;
-def A2_vabshsat : T_S2op_3 <"vabsh", 0b01, 0b101, 1>;
-
-// Vector absolute value words with and without saturation
-def A2_vabsw : T_S2op_3 <"vabsw", 0b01, 0b110>;
-def A2_vabswsat : T_S2op_3 <"vabsw", 0b01, 0b111, 1>;
-
-//===----------------------------------------------------------------------===//
-// STYPE/BIT +
-//===----------------------------------------------------------------------===//
-// Bit count
-
-let hasSideEffects = 0, hasNewValue = 1 in
-class T_COUNT_LEADING<string MnOp, bits<3> MajOp, bits<3> MinOp, bit Is32,
- dag Out, dag Inp>
- : SInst<Out, Inp, "$Rd = "#MnOp#"($Rs)", [], "", S_2op_tc_1_SLOT23> {
- bits<5> Rs;
- bits<5> Rd;
- let IClass = 0b1000;
- let Inst{27} = 0b1;
- let Inst{26} = Is32;
- let Inst{25-24} = 0b00;
- let Inst{23-21} = MajOp;
- let Inst{20-16} = Rs;
- let Inst{7-5} = MinOp;
- let Inst{4-0} = Rd;
-}
-
-class T_COUNT_LEADING_32<string MnOp, bits<3> MajOp, bits<3> MinOp>
- : T_COUNT_LEADING<MnOp, MajOp, MinOp, 0b1,
- (outs IntRegs:$Rd), (ins IntRegs:$Rs)>;
-
-class T_COUNT_LEADING_64<string MnOp, bits<3> MajOp, bits<3> MinOp>
- : T_COUNT_LEADING<MnOp, MajOp, MinOp, 0b0,
- (outs IntRegs:$Rd), (ins DoubleRegs:$Rs)>;
-
-def S2_cl0 : T_COUNT_LEADING_32<"cl0", 0b000, 0b101>;
-def S2_cl1 : T_COUNT_LEADING_32<"cl1", 0b000, 0b110>;
-def S2_ct0 : T_COUNT_LEADING_32<"ct0", 0b010, 0b100>;
-def S2_ct1 : T_COUNT_LEADING_32<"ct1", 0b010, 0b101>;
-def S2_cl0p : T_COUNT_LEADING_64<"cl0", 0b010, 0b010>;
-def S2_cl1p : T_COUNT_LEADING_64<"cl1", 0b010, 0b100>;
-def S2_clb : T_COUNT_LEADING_32<"clb", 0b000, 0b100>;
-def S2_clbp : T_COUNT_LEADING_64<"clb", 0b010, 0b000>;
-def S2_clbnorm : T_COUNT_LEADING_32<"normamt", 0b000, 0b111>;
-
-// The 64-bit counts leading/trailing are defined in HexagonInstrInfoV4.td.
-
-// Bit set/clear/toggle
-
-let hasSideEffects = 0, hasNewValue = 1 in
-class T_SCT_BIT_IMM<string MnOp, bits<3> MinOp>
- : SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, u5_0Imm:$u5),
- "$Rd = "#MnOp#"($Rs, #$u5)", [], "", S_2op_tc_1_SLOT23> {
- bits<5> Rd;
- bits<5> Rs;
- bits<5> u5;
- let IClass = 0b1000;
- let Inst{27-21} = 0b1100110;
- let Inst{20-16} = Rs;
- let Inst{13} = 0b0;
- let Inst{12-8} = u5;
- let Inst{7-5} = MinOp;
- let Inst{4-0} = Rd;
-}
-
-let hasSideEffects = 0, hasNewValue = 1 in
-class T_SCT_BIT_REG<string MnOp, bits<2> MinOp>
- : SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
- "$Rd = "#MnOp#"($Rs, $Rt)", [], "", S_3op_tc_1_SLOT23> {
- bits<5> Rd;
- bits<5> Rs;
- bits<5> Rt;
- let IClass = 0b1100;
- let Inst{27-22} = 0b011010;
- let Inst{20-16} = Rs;
- let Inst{12-8} = Rt;
- let Inst{7-6} = MinOp;
- let Inst{4-0} = Rd;
-}
-
-def S2_clrbit_i : T_SCT_BIT_IMM<"clrbit", 0b001>;
-def S2_setbit_i : T_SCT_BIT_IMM<"setbit", 0b000>;
-def S2_togglebit_i : T_SCT_BIT_IMM<"togglebit", 0b010>;
-def S2_clrbit_r : T_SCT_BIT_REG<"clrbit", 0b01>;
-def S2_setbit_r : T_SCT_BIT_REG<"setbit", 0b00>;
-def S2_togglebit_r : T_SCT_BIT_REG<"togglebit", 0b10>;
-
-// Bit test
-
-let hasSideEffects = 0 in
-class T_TEST_BIT_IMM<string MnOp, bits<3> MajOp>
- : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, u5_0Imm:$u5),
- "$Pd = "#MnOp#"($Rs, #$u5)",
- [], "", S_2op_tc_2early_SLOT23> {
- bits<2> Pd;
- bits<5> Rs;
- bits<5> u5;
- let IClass = 0b1000;
- let Inst{27-24} = 0b0101;
- let Inst{23-21} = MajOp;
- let Inst{20-16} = Rs;
- let Inst{13} = 0;
- let Inst{12-8} = u5;
- let Inst{1-0} = Pd;
-}
-
-let hasSideEffects = 0 in
-class T_TEST_BIT_REG<string MnOp, bit IsNeg>
- : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
- "$Pd = "#MnOp#"($Rs, $Rt)",
- [], "", S_3op_tc_2early_SLOT23> {
- bits<2> Pd;
- bits<5> Rs;
- bits<5> Rt;
- let IClass = 0b1100;
- let Inst{27-22} = 0b011100;
- let Inst{21} = IsNeg;
- let Inst{20-16} = Rs;
- let Inst{12-8} = Rt;
- let Inst{1-0} = Pd;
-}
-
-def S2_tstbit_i : T_TEST_BIT_IMM<"tstbit", 0b000>;
-def S2_tstbit_r : T_TEST_BIT_REG<"tstbit", 0>;
-
-let hasSideEffects = 0 in
-class T_TEST_BITS_IMM<string MnOp, bits<2> MajOp, bit IsNeg>
- : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, u6_0Imm:$u6),
- "$Pd = "#MnOp#"($Rs, #$u6)",
- [], "", S_2op_tc_2early_SLOT23> {
- bits<2> Pd;
- bits<5> Rs;
- bits<6> u6;
- let IClass = 0b1000;
- let Inst{27-24} = 0b0101;
- let Inst{23-22} = MajOp;
- let Inst{21} = IsNeg;
- let Inst{20-16} = Rs;
- let Inst{13-8} = u6;
- let Inst{1-0} = Pd;
-}
-
-let hasSideEffects = 0 in
-class T_TEST_BITS_REG<string MnOp, bits<2> MajOp, bit IsNeg>
- : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
- "$Pd = "#MnOp#"($Rs, $Rt)",
- [], "", S_3op_tc_2early_SLOT23> {
- bits<2> Pd;
- bits<5> Rs;
- bits<5> Rt;
- let IClass = 0b1100;
- let Inst{27-24} = 0b0111;
- let Inst{23-22} = MajOp;
- let Inst{21} = IsNeg;
- let Inst{20-16} = Rs;
- let Inst{12-8} = Rt;
- let Inst{1-0} = Pd;
-}
-
-def C2_bitsclri : T_TEST_BITS_IMM<"bitsclr", 0b10, 0>;
-def C2_bitsclr : T_TEST_BITS_REG<"bitsclr", 0b10, 0>;
-def C2_bitsset : T_TEST_BITS_REG<"bitsset", 0b01, 0>;
-
-//===----------------------------------------------------------------------===//
-// STYPE/BIT -
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// STYPE/COMPLEX +
-//===----------------------------------------------------------------------===//
-//===----------------------------------------------------------------------===//
-// STYPE/COMPLEX -
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// XTYPE/PERM +
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// XTYPE/PERM -
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// STYPE/PRED +
-//===----------------------------------------------------------------------===//
-
-// Predicate transfer.
-let hasSideEffects = 0, hasNewValue = 1 in
-def C2_tfrpr : SInst<(outs IntRegs:$Rd), (ins PredRegs:$Ps),
- "$Rd = $Ps", [], "", S_2op_tc_1_SLOT23> {
- bits<5> Rd;
- bits<2> Ps;
-
- let IClass = 0b1000;
- let Inst{27-24} = 0b1001;
- let Inst{22} = 0b1;
- let Inst{17-16} = Ps;
- let Inst{4-0} = Rd;
-}
-
-// Transfer general register to predicate.
-let hasSideEffects = 0 in
-def C2_tfrrp: SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs),
- "$Pd = $Rs", [], "", S_2op_tc_2early_SLOT23> {
- bits<2> Pd;
- bits<5> Rs;
-
- let IClass = 0b1000;
- let Inst{27-21} = 0b0101010;
- let Inst{20-16} = Rs;
- let Inst{1-0} = Pd;
-}
-
-let hasSideEffects = 0, isCodeGenOnly = 1 in
-def C2_pxfer_map: SInst<(outs PredRegs:$dst), (ins PredRegs:$src),
- "$dst = $src">;
-
-//===----------------------------------------------------------------------===//
-// STYPE/PRED -
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// STYPE/SHIFT +
-//===----------------------------------------------------------------------===//
-class S_2OpInstImm<string Mnemonic, bits<3>MajOp, bits<3>MinOp,
- Operand Imm, list<dag> pattern = [], bit isRnd = 0>
- : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, Imm:$src2),
- "$dst = "#Mnemonic#"($src1, #$src2)"#!if(isRnd, ":rnd", ""),
- pattern> {
- bits<5> src1;
- bits<5> dst;
- let IClass = 0b1000;
- let Inst{27-24} = 0;
- let Inst{23-21} = MajOp;
- let Inst{20-16} = src1;
- let Inst{7-5} = MinOp;
- let Inst{4-0} = dst;
-}
-
-class S_2OpInstImmI6<string Mnemonic, SDNode OpNode, bits<3>MinOp>
- : S_2OpInstImm<Mnemonic, 0b000, MinOp, u6_0Imm, []> {
- bits<6> src2;
- let Inst{13-8} = src2;
-}
-
-// Shift by immediate.
-def S2_asr_i_p : S_2OpInstImmI6<"asr", sra, 0b000>;
-def S2_asl_i_p : S_2OpInstImmI6<"asl", shl, 0b010>;
-def S2_lsr_i_p : S_2OpInstImmI6<"lsr", srl, 0b001>;
-
-// Shift left by small amount and add.
-let AddedComplexity = 100, hasNewValue = 1, hasSideEffects = 0 in
-def S2_addasl_rrri: SInst <(outs IntRegs:$Rd),
- (ins IntRegs:$Rt, IntRegs:$Rs, u3_0Imm:$u3),
- "$Rd = addasl($Rt, $Rs, #$u3)" , [],
- "", S_3op_tc_2_SLOT23> {
- bits<5> Rd;
- bits<5> Rt;
- bits<5> Rs;
- bits<3> u3;
-
- let IClass = 0b1100;
-
- let Inst{27-21} = 0b0100000;
- let Inst{20-16} = Rs;
- let Inst{13} = 0b0;
- let Inst{12-8} = Rt;
- let Inst{7-5} = u3;
- let Inst{4-0} = Rd;
- }
-
-//===----------------------------------------------------------------------===//
-// STYPE/SHIFT -
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// STYPE/VH +
-//===----------------------------------------------------------------------===//
-//===----------------------------------------------------------------------===//
-// STYPE/VH -
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// STYPE/VW +
-//===----------------------------------------------------------------------===//
-//===----------------------------------------------------------------------===//
-// STYPE/VW -
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// SYSTEM/SUPER +
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// SYSTEM/USER +
-//===----------------------------------------------------------------------===//
-let hasSideEffects = 1, isSoloAX = 1 in
-def Y2_barrier : SYSInst<(outs), (ins), "barrier", [],"",ST_tc_st_SLOT0> {
- let Inst{31-28} = 0b1010;
- let Inst{27-21} = 0b1000000;
-}
-
-//===----------------------------------------------------------------------===//
-// SYSTEM/SUPER -
-//===----------------------------------------------------------------------===//
-
-// Generate frameindex addresses. The main reason for the offset operand is
-// that every instruction that is allowed to have frame index as an operand
-// will then have that operand followed by an immediate operand (the offset).
-// This simplifies the frame-index elimination code.
-//
-let isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1,
- isPseudo = 1, isCodeGenOnly = 1, hasSideEffects = 0 in {
- def PS_fi : ALU32_ri<(outs IntRegs:$Rd),
- (ins IntRegs:$fi, s32_0Imm:$off), "">;
- def PS_fia : ALU32_ri<(outs IntRegs:$Rd),
- (ins IntRegs:$Rs, IntRegs:$fi, s32_0Imm:$off), "">;
-}
-
-//===----------------------------------------------------------------------===//
-// CRUSER - Type.
-//===----------------------------------------------------------------------===//
-// HW loop
-let isExtendable = 1, isExtentSigned = 1, opExtentBits = 9, opExtentAlign = 2,
- opExtendable = 0, hasSideEffects = 0 in
-class LOOP_iBase<string mnemonic, Operand brOp, bit mustExtend = 0>
- : CRInst<(outs), (ins brOp:$offset, u10_0Imm:$src2),
- #mnemonic#"($offset, #$src2)",
- [], "" , CR_tc_3x_SLOT3> {
- bits<9> offset;
- bits<10> src2;
-
- let IClass = 0b0110;
-
- let Inst{27-22} = 0b100100;
- let Inst{21} = !if (!eq(mnemonic, "loop0"), 0b0, 0b1);
- let Inst{20-16} = src2{9-5};
- let Inst{12-8} = offset{8-4};
- let Inst{7-5} = src2{4-2};
- let Inst{4-3} = offset{3-2};
- let Inst{1-0} = src2{1-0};
-}
-
-let isExtendable = 1, isExtentSigned = 1, opExtentBits = 9, opExtentAlign = 2,
- opExtendable = 0, hasSideEffects = 0 in
-class LOOP_rBase<string mnemonic, Operand brOp, bit mustExtend = 0>
- : CRInst<(outs), (ins brOp:$offset, IntRegs:$src2),
- #mnemonic#"($offset, $src2)",
- [], "" ,CR_tc_3x_SLOT3> {
- bits<9> offset;
- bits<5> src2;
-
- let IClass = 0b0110;
-
- let Inst{27-22} = 0b000000;
- let Inst{21} = !if (!eq(mnemonic, "loop0"), 0b0, 0b1);
- let Inst{20-16} = src2;
- let Inst{12-8} = offset{8-4};
- let Inst{4-3} = offset{3-2};
- }
-
-multiclass LOOP_ri<string mnemonic> {
- def i : LOOP_iBase<mnemonic, brtarget>;
- def r : LOOP_rBase<mnemonic, brtarget>;
-
- let isCodeGenOnly = 1, isExtended = 1, opExtendable = 0 in {
- def iext: LOOP_iBase<mnemonic, brtargetExt, 1>;
- def rext: LOOP_rBase<mnemonic, brtargetExt, 1>;
- }
-}
-
-
-let Defs = [SA0, LC0, USR] in
-defm J2_loop0 : LOOP_ri<"loop0">;
-
-// Interestingly only loop0's appear to set usr.lpcfg
-let Defs = [SA1, LC1] in
-defm J2_loop1 : LOOP_ri<"loop1">;
-
-let isBranch = 1, isTerminator = 1, hasSideEffects = 0,
- Defs = [PC, LC0], Uses = [SA0, LC0] in {
-def ENDLOOP0 : Endloop<(outs), (ins brtarget:$offset),
- ":endloop0",
- []>;
-}
-
-let isBranch = 1, isTerminator = 1, hasSideEffects = 0,
- Defs = [PC, LC1], Uses = [SA1, LC1] in {
-def ENDLOOP1 : Endloop<(outs), (ins brtarget:$offset),
- ":endloop1",
- []>;
-}
-
-// Pipelined loop instructions, sp[123]loop0
-let Defs = [LC0, SA0, P3, USR], hasSideEffects = 0,
- isExtentSigned = 1, isExtendable = 1, opExtentBits = 9, opExtentAlign = 2,
- opExtendable = 0, isPredicateLate = 1 in
-class SPLOOP_iBase<string SP, bits<2> op>
- : CRInst <(outs), (ins brtarget:$r7_2, u10_0Imm:$U10),
- "p3 = sp"#SP#"loop0($r7_2, #$U10)" > {
- bits<9> r7_2;
- bits<10> U10;
-
- let IClass = 0b0110;
-
- let Inst{22-21} = op;
- let Inst{27-23} = 0b10011;
- let Inst{20-16} = U10{9-5};
- let Inst{12-8} = r7_2{8-4};
- let Inst{7-5} = U10{4-2};
- let Inst{4-3} = r7_2{3-2};
- let Inst{1-0} = U10{1-0};
- }
-
-let Defs = [LC0, SA0, P3, USR], hasSideEffects = 0,
- isExtentSigned = 1, isExtendable = 1, opExtentBits = 9, opExtentAlign = 2,
- opExtendable = 0, isPredicateLate = 1 in
-class SPLOOP_rBase<string SP, bits<2> op>
- : CRInst <(outs), (ins brtarget:$r7_2, IntRegs:$Rs),
- "p3 = sp"#SP#"loop0($r7_2, $Rs)" > {
- bits<9> r7_2;
- bits<5> Rs;
-
- let IClass = 0b0110;
-
- let Inst{22-21} = op;
- let Inst{27-23} = 0b00001;
- let Inst{20-16} = Rs;
- let Inst{12-8} = r7_2{8-4};
- let Inst{4-3} = r7_2{3-2};
- }
-
-multiclass SPLOOP_ri<string mnemonic, bits<2> op> {
- def i : SPLOOP_iBase<mnemonic, op>;
- def r : SPLOOP_rBase<mnemonic, op>;
-}
-
-defm J2_ploop1s : SPLOOP_ri<"1", 0b01>;
-defm J2_ploop2s : SPLOOP_ri<"2", 0b10>;
-defm J2_ploop3s : SPLOOP_ri<"3", 0b11>;
-
-// if (Rs[!>=<]=#0) jump:[t/nt]
-let Defs = [PC], isPredicated = 1, isBranch = 1, hasSideEffects = 0,
- hasSideEffects = 0 in
-class J2_jump_0_Base<string compare, bit isTak, bits<2> op>
- : CRInst <(outs), (ins IntRegs:$Rs, brtarget:$r13_2),
- "if ($Rs"#compare#"#0) jump"#!if(isTak, ":t", ":nt")#" $r13_2" > {
- bits<5> Rs;
- bits<15> r13_2;
-
- let IClass = 0b0110;
-
- let Inst{27-24} = 0b0001;
- let Inst{23-22} = op;
- let Inst{12} = isTak;
- let Inst{21} = r13_2{14};
- let Inst{20-16} = Rs;
- let Inst{11-1} = r13_2{12-2};
- let Inst{13} = r13_2{13};
- }
-
-multiclass J2_jump_compare_0<string compare, bits<2> op> {
- def NAME : J2_jump_0_Base<compare, 0, op>;
- def NAME#pt : J2_jump_0_Base<compare, 1, op>;
-}
-
-defm J2_jumprz : J2_jump_compare_0<"!=", 0b00>;
-defm J2_jumprgtez : J2_jump_compare_0<">=", 0b01>;
-defm J2_jumprnz : J2_jump_compare_0<"==", 0b10>;
-defm J2_jumprltez : J2_jump_compare_0<"<=", 0b11>;
-
-// Transfer to/from Control/GPR Guest/GPR
-let hasSideEffects = 0 in
-class TFR_CR_RS_base<RegisterClass CTRC, RegisterClass RC, bit isDouble>
- : CRInst <(outs CTRC:$dst), (ins RC:$src),
- "$dst = $src", [], "", CR_tc_3x_SLOT3> {
- bits<5> dst;
- bits<5> src;
-
- let IClass = 0b0110;
-
- let Inst{27-25} = 0b001;
- let Inst{24} = isDouble;
- let Inst{23-21} = 0b001;
- let Inst{20-16} = src;
- let Inst{4-0} = dst;
- }
-
-def A2_tfrrcr : TFR_CR_RS_base<CtrRegs, IntRegs, 0b0>;
-def A4_tfrpcp : TFR_CR_RS_base<CtrRegs64, DoubleRegs, 0b1>;
-def : InstAlias<"m0 = $Rs", (A2_tfrrcr C6, IntRegs:$Rs)>;
-def : InstAlias<"m1 = $Rs", (A2_tfrrcr C7, IntRegs:$Rs)>;
-
-let hasSideEffects = 0 in
-class TFR_RD_CR_base<RegisterClass RC, RegisterClass CTRC, bit isSingle>
- : CRInst <(outs RC:$dst), (ins CTRC:$src),
- "$dst = $src", [], "", CR_tc_3x_SLOT3> {
- bits<5> dst;
- bits<5> src;
-
- let IClass = 0b0110;
-
- let Inst{27-26} = 0b10;
- let Inst{25} = isSingle;
- let Inst{24-21} = 0b0000;
- let Inst{20-16} = src;
- let Inst{4-0} = dst;
- }
-
-let hasNewValue = 1, opNewValue = 0 in
-def A2_tfrcrr : TFR_RD_CR_base<IntRegs, CtrRegs, 1>;
-def A4_tfrcpp : TFR_RD_CR_base<DoubleRegs, CtrRegs64, 0>;
-def : InstAlias<"$Rd = m0", (A2_tfrcrr IntRegs:$Rd, C6)>;
-def : InstAlias<"$Rd = m1", (A2_tfrcrr IntRegs:$Rd, C7)>;
-
-// Y4_trace: Send value to etm trace.
-let isSoloAX = 1, hasSideEffects = 0 in
-def Y4_trace: CRInst <(outs), (ins IntRegs:$Rs),
- "trace($Rs)"> {
- bits<5> Rs;
-
- let IClass = 0b0110;
- let Inst{27-21} = 0b0010010;
- let Inst{20-16} = Rs;
- }
-
-// HI/LO Instructions
-let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0,
- hasNewValue = 1, opNewValue = 0 in
-class REG_IMMED<string RegHalf, bit Rs, bits<3> MajOp, bit MinOp>
- : ALU32_ri<(outs IntRegs:$dst),
- (ins u16_0Imm:$imm_value),
- "$dst"#RegHalf#" = $imm_value", []> {
- bits<5> dst;
- bits<32> imm_value;
- let IClass = 0b0111;
-
- let Inst{27} = Rs;
- let Inst{26-24} = MajOp;
- let Inst{21} = MinOp;
- let Inst{20-16} = dst;
- let Inst{23-22} = imm_value{15-14};
- let Inst{13-0} = imm_value{13-0};
-}
-
-let isAsmParserOnly = 1 in {
- def LO : REG_IMMED<".l", 0b0, 0b001, 0b1>;
- def HI : REG_IMMED<".h", 0b0, 0b010, 0b1>;
-}
-
-let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in {
- def CONST32 : CONSTLDInst<(outs IntRegs:$Rd), (ins i32imm:$v),
- "$Rd = CONST32(#$v)", []>;
- def CONST64 : CONSTLDInst<(outs DoubleRegs:$Rd), (ins i64imm:$v),
- "$Rd = CONST64(#$v)", []>;
-}
-
-let hasSideEffects = 0, isReMaterializable = 1, isPseudo = 1,
- isCodeGenOnly = 1 in
-def PS_true : SInst<(outs PredRegs:$dst), (ins), "", []>;
-
-let hasSideEffects = 0, isReMaterializable = 1, isPseudo = 1,
- isCodeGenOnly = 1 in
-def PS_false : SInst<(outs PredRegs:$dst), (ins), "", []>;
-
-let Defs = [R29, R30], Uses = [R31, R30, R29], isPseudo = 1 in
-def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
- ".error \"should not emit\" ", []>;
-
-let Defs = [R29, R30, R31], Uses = [R29], isPseudo = 1 in
-def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
- ".error \"should not emit\" ", []>;
-
-// Call subroutine indirectly.
-let Defs = VolatileV3.Regs in
-def J2_callr : JUMPR_MISC_CALLR<0, 1>;
-
-// Indirect tail-call.
-let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0,
- isTerminator = 1, isCodeGenOnly = 1 in
-def PS_tailcall_r : T_JMPr;
-
-// Direct tail-calls.
-let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0,
- isTerminator = 1, isCodeGenOnly = 1 in
-def PS_tailcall_i : JInst<(outs), (ins calltarget:$dst), "", []>;
-
-// The reason for the custom inserter is to record all ALLOCA instructions
-// in MachineFunctionInfo.
-let Defs = [R29], isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 1 in
-def PS_alloca: ALU32Inst<(outs IntRegs:$Rd),
- (ins IntRegs:$Rs, u32_0Imm:$A), "", []>;
-
-let isCodeGenOnly = 1, isPseudo = 1, Uses = [R30], hasSideEffects = 0 in
-def PS_aligna : ALU32Inst<(outs IntRegs:$Rd), (ins u32_0Imm:$A), "", []>;
-
-// XTYPE/SHIFT
-//
-//===----------------------------------------------------------------------===//
-// Template Class
-// Shift by immediate/register and accumulate/logical
-//===----------------------------------------------------------------------===//
-
-// Rx[+-&|]=asr(Rs,#u5)
-// Rx[+-&|^]=lsr(Rs,#u5)
-// Rx[+-&|^]=asl(Rs,#u5)
-
-let hasNewValue = 1, opNewValue = 0 in
-class T_shift_imm_acc_r <string opc1, string opc2, SDNode OpNode1,
- SDNode OpNode2, bits<3> majOp, bits<2> minOp>
- : SInst_acc<(outs IntRegs:$Rx),
- (ins IntRegs:$src1, IntRegs:$Rs, u5_0Imm:$u5),
- "$Rx "#opc2#opc1#"($Rs, #$u5)", [],
- "$src1 = $Rx", S_2op_tc_2_SLOT23> {
- bits<5> Rx;
- bits<5> Rs;
- bits<5> u5;
-
- let IClass = 0b1000;
-
- let Inst{27-24} = 0b1110;
- let Inst{23-22} = majOp{2-1};
- let Inst{13} = 0b0;
- let Inst{7} = majOp{0};
- let Inst{6-5} = minOp;
- let Inst{4-0} = Rx;
- let Inst{20-16} = Rs;
- let Inst{12-8} = u5;
- }
-
-// Rx[+-&|]=asr(Rs,Rt)
-// Rx[+-&|^]=lsr(Rs,Rt)
-// Rx[+-&|^]=asl(Rs,Rt)
-
-let hasNewValue = 1, opNewValue = 0 in
-class T_shift_reg_acc_r <string opc1, string opc2, SDNode OpNode1,
- SDNode OpNode2, bits<2> majOp, bits<2> minOp>
- : SInst_acc<(outs IntRegs:$Rx),
- (ins IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt),
- "$Rx "#opc2#opc1#"($Rs, $Rt)", [],
- "$src1 = $Rx", S_3op_tc_2_SLOT23 > {
- bits<5> Rx;
- bits<5> Rs;
- bits<5> Rt;
-
- let IClass = 0b1100;
-
- let Inst{27-24} = 0b1100;
- let Inst{23-22} = majOp;
- let Inst{7-6} = minOp;
- let Inst{4-0} = Rx;
- let Inst{20-16} = Rs;
- let Inst{12-8} = Rt;
- }
-
-// Rxx[+-&|]=asr(Rss,#u6)
-// Rxx[+-&|^]=lsr(Rss,#u6)
-// Rxx[+-&|^]=asl(Rss,#u6)
-
-class T_shift_imm_acc_p <string opc1, string opc2, SDNode OpNode1,
- SDNode OpNode2, bits<3> majOp, bits<2> minOp>
- : SInst_acc<(outs DoubleRegs:$Rxx),
- (ins DoubleRegs:$src1, DoubleRegs:$Rss, u6_0Imm:$u6),
- "$Rxx "#opc2#opc1#"($Rss, #$u6)", [],
- "$src1 = $Rxx", S_2op_tc_2_SLOT23> {
- bits<5> Rxx;
- bits<5> Rss;
- bits<6> u6;
-
- let IClass = 0b1000;
-
- let Inst{27-24} = 0b0010;
- let Inst{23-22} = majOp{2-1};
- let Inst{7} = majOp{0};
- let Inst{6-5} = minOp;
- let Inst{4-0} = Rxx;
- let Inst{20-16} = Rss;
- let Inst{13-8} = u6;
- }
-
-
-// Rxx[+-&|]=asr(Rss,Rt)
-// Rxx[+-&|^]=lsr(Rss,Rt)
-// Rxx[+-&|^]=asl(Rss,Rt)
-// Rxx[+-&|^]=lsl(Rss,Rt)
-
-class T_shift_reg_acc_p <string opc1, string opc2, SDNode OpNode1,
- SDNode OpNode2, bits<3> majOp, bits<2> minOp>
- : SInst_acc<(outs DoubleRegs:$Rxx),
- (ins DoubleRegs:$src1, DoubleRegs:$Rss, IntRegs:$Rt),
- "$Rxx "#opc2#opc1#"($Rss, $Rt)", [],
- "$src1 = $Rxx", S_3op_tc_2_SLOT23> {
- bits<5> Rxx;
- bits<5> Rss;
- bits<5> Rt;
-
- let IClass = 0b1100;
-
- let Inst{27-24} = 0b1011;
- let Inst{23-21} = majOp;
- let Inst{20-16} = Rss;
- let Inst{12-8} = Rt;
- let Inst{7-6} = minOp;
- let Inst{4-0} = Rxx;
- }
-
-//===----------------------------------------------------------------------===//
-// Multi-class for the shift instructions with logical/arithmetic operators.
-//===----------------------------------------------------------------------===//
-
-multiclass xtype_imm_base<string OpcStr1, string OpcStr2, SDNode OpNode1,
- SDNode OpNode2, bits<3> majOp, bits<2> minOp > {
- def _i_r#NAME : T_shift_imm_acc_r< OpcStr1, OpcStr2, OpNode1,
- OpNode2, majOp, minOp >;
- def _i_p#NAME : T_shift_imm_acc_p< OpcStr1, OpcStr2, OpNode1,
- OpNode2, majOp, minOp >;
-}
-
-multiclass xtype_imm_acc<string opc1, SDNode OpNode, bits<2>minOp> {
- let AddedComplexity = 100 in
- defm _acc : xtype_imm_base< opc1, "+= ", OpNode, add, 0b001, minOp>;
-
- defm _nac : xtype_imm_base< opc1, "-= ", OpNode, sub, 0b000, minOp>;
- defm _and : xtype_imm_base< opc1, "&= ", OpNode, and, 0b010, minOp>;
- defm _or : xtype_imm_base< opc1, "|= ", OpNode, or, 0b011, minOp>;
-}
-
-multiclass xtype_xor_imm_acc<string opc1, SDNode OpNode, bits<2>minOp> {
-let AddedComplexity = 100 in
- defm _xacc : xtype_imm_base< opc1, "^= ", OpNode, xor, 0b100, minOp>;
-}
-
-defm S2_asr : xtype_imm_acc<"asr", sra, 0b00>;
-
-defm S2_lsr : xtype_imm_acc<"lsr", srl, 0b01>,
- xtype_xor_imm_acc<"lsr", srl, 0b01>;
-
-defm S2_asl : xtype_imm_acc<"asl", shl, 0b10>,
- xtype_xor_imm_acc<"asl", shl, 0b10>;
-
-multiclass xtype_reg_acc_r<string opc1, SDNode OpNode, bits<2>minOp> {
- let AddedComplexity = 100 in
- def _acc : T_shift_reg_acc_r <opc1, "+= ", OpNode, add, 0b11, minOp>;
-
- def _nac : T_shift_reg_acc_r <opc1, "-= ", OpNode, sub, 0b10, minOp>;
- def _and : T_shift_reg_acc_r <opc1, "&= ", OpNode, and, 0b01, minOp>;
- def _or : T_shift_reg_acc_r <opc1, "|= ", OpNode, or, 0b00, minOp>;
-}
-
-multiclass xtype_reg_acc_p<string opc1, SDNode OpNode, bits<2>minOp> {
- let AddedComplexity = 100 in
- def _acc : T_shift_reg_acc_p <opc1, "+= ", OpNode, add, 0b110, minOp>;
-
- def _nac : T_shift_reg_acc_p <opc1, "-= ", OpNode, sub, 0b100, minOp>;
- def _and : T_shift_reg_acc_p <opc1, "&= ", OpNode, and, 0b010, minOp>;
- def _or : T_shift_reg_acc_p <opc1, "|= ", OpNode, or, 0b000, minOp>;
- def _xor : T_shift_reg_acc_p <opc1, "^= ", OpNode, xor, 0b011, minOp>;
-}
-
-multiclass xtype_reg_acc<string OpcStr, SDNode OpNode, bits<2> minOp > {
- defm _r_r : xtype_reg_acc_r <OpcStr, OpNode, minOp>;
- defm _r_p : xtype_reg_acc_p <OpcStr, OpNode, minOp>;
-}
-
-defm S2_asl : xtype_reg_acc<"asl", shl, 0b10>;
-defm S2_asr : xtype_reg_acc<"asr", sra, 0b00>;
-defm S2_lsr : xtype_reg_acc<"lsr", srl, 0b01>;
-defm S2_lsl : xtype_reg_acc<"lsl", shl, 0b11>;
-
-//===----------------------------------------------------------------------===//
-let hasSideEffects = 0 in
-class T_S3op_1 <string mnemonic, RegisterClass RC, bits<2> MajOp, bits<3> MinOp,
- bit SwapOps, bit isSat = 0, bit isRnd = 0, bit hasShift = 0>
- : SInst <(outs RC:$dst),
- (ins DoubleRegs:$src1, DoubleRegs:$src2),
- "$dst = "#mnemonic#"($src1, $src2)"#!if(isRnd, ":rnd", "")
- #!if(hasShift,":>>1","")
- #!if(isSat, ":sat", ""),
- [], "", S_3op_tc_2_SLOT23 > {
- bits<5> dst;
- bits<5> src1;
- bits<5> src2;
-
- let IClass = 0b1100;
-
- let Inst{27-24} = 0b0001;
- let Inst{23-22} = MajOp;
- let Inst{20-16} = !if (SwapOps, src2, src1);
- let Inst{12-8} = !if (SwapOps, src1, src2);
- let Inst{7-5} = MinOp;
- let Inst{4-0} = dst;
- }
-
-class T_S3op_64 <string mnemonic, bits<2> MajOp, bits<3> MinOp, bit SwapOps,
- bit isSat = 0, bit isRnd = 0, bit hasShift = 0 >
- : T_S3op_1 <mnemonic, DoubleRegs, MajOp, MinOp, SwapOps,
- isSat, isRnd, hasShift>;
-
-let Itinerary = S_3op_tc_1_SLOT23 in {
- def S2_shuffeb : T_S3op_64 < "shuffeb", 0b00, 0b010, 0>;
- def S2_shuffeh : T_S3op_64 < "shuffeh", 0b00, 0b110, 0>;
- def S2_shuffob : T_S3op_64 < "shuffob", 0b00, 0b100, 1>;
- def S2_shuffoh : T_S3op_64 < "shuffoh", 0b10, 0b000, 1>;
-
- def S2_vtrunewh : T_S3op_64 < "vtrunewh", 0b10, 0b010, 0>;
- def S2_vtrunowh : T_S3op_64 < "vtrunowh", 0b10, 0b100, 0>;
-}
-
-def S2_lfsp : T_S3op_64 < "lfs", 0b10, 0b110, 0>;
-
-let hasSideEffects = 0 in
-class T_S3op_2 <string mnemonic, bits<3> MajOp, bit SwapOps>
- : SInst < (outs DoubleRegs:$Rdd),
- (ins DoubleRegs:$Rss, DoubleRegs:$Rtt, PredRegs:$Pu),
- "$Rdd = "#mnemonic#"($Rss, $Rtt, $Pu)",
- [], "", S_3op_tc_1_SLOT23 > {
- bits<5> Rdd;
- bits<5> Rss;
- bits<5> Rtt;
- bits<2> Pu;
-
- let IClass = 0b1100;
-
- let Inst{27-24} = 0b0010;
- let Inst{23-21} = MajOp;
- let Inst{20-16} = !if (SwapOps, Rtt, Rss);
- let Inst{12-8} = !if (SwapOps, Rss, Rtt);
- let Inst{6-5} = Pu;
- let Inst{4-0} = Rdd;
- }
-
-def S2_valignrb : T_S3op_2 < "valignb", 0b000, 1>;
-def S2_vsplicerb : T_S3op_2 < "vspliceb", 0b100, 0>;
-
-//===----------------------------------------------------------------------===//
-// Template class used by vector shift, vector rotate, vector neg,
-// 32-bit shift, 64-bit shifts, etc.
-//===----------------------------------------------------------------------===//
-
-let hasSideEffects = 0 in
-class T_S3op_3 <string mnemonic, RegisterClass RC, bits<2> MajOp,
- bits<2> MinOp, bit isSat = 0, list<dag> pattern = [] >
- : SInst <(outs RC:$dst),
- (ins RC:$src1, IntRegs:$src2),
- "$dst = "#mnemonic#"($src1, $src2)"#!if(isSat, ":sat", ""),
- pattern, "", S_3op_tc_1_SLOT23> {
- bits<5> dst;
- bits<5> src1;
- bits<5> src2;
-
- let IClass = 0b1100;
-
- let Inst{27-24} = !if(!eq(!cast<string>(RC), "IntRegs"), 0b0110, 0b0011);
- let Inst{23-22} = MajOp;
- let Inst{20-16} = src1;
- let Inst{12-8} = src2;
- let Inst{7-6} = MinOp;
- let Inst{4-0} = dst;
- }
-
-let hasNewValue = 1 in
-class T_S3op_shift32 <string mnemonic, SDNode OpNode, bits<2> MinOp>
- : T_S3op_3 <mnemonic, IntRegs, 0b01, MinOp, 0, []>;
-
-let hasNewValue = 1, Itinerary = S_3op_tc_2_SLOT23 in
-class T_S3op_shift32_Sat <string mnemonic, bits<2> MinOp>
- : T_S3op_3 <mnemonic, IntRegs, 0b00, MinOp, 1, []>;
-
-
-class T_S3op_shift64 <string mnemonic, SDNode OpNode, bits<2> MinOp>
- : T_S3op_3 <mnemonic, DoubleRegs, 0b10, MinOp, 0, []>;
-
-
-class T_S3op_shiftVect <string mnemonic, bits<2> MajOp, bits<2> MinOp>
- : T_S3op_3 <mnemonic, DoubleRegs, MajOp, MinOp, 0, []>;
-
-
-// Shift by register
-// Rdd=[asr|lsr|asl|lsl](Rss,Rt)
-
-def S2_asr_r_p : T_S3op_shift64 < "asr", sra, 0b00>;
-def S2_lsr_r_p : T_S3op_shift64 < "lsr", srl, 0b01>;
-def S2_asl_r_p : T_S3op_shift64 < "asl", shl, 0b10>;
-def S2_lsl_r_p : T_S3op_shift64 < "lsl", shl, 0b11>;
-
-// Rd=[asr|lsr|asl|lsl](Rs,Rt)
-
-def S2_asr_r_r : T_S3op_shift32<"asr", sra, 0b00>;
-def S2_lsr_r_r : T_S3op_shift32<"lsr", srl, 0b01>;
-def S2_asl_r_r : T_S3op_shift32<"asl", shl, 0b10>;
-def S2_lsl_r_r : T_S3op_shift32<"lsl", shl, 0b11>;
-
-// Shift by register with saturation
-// Rd=asr(Rs,Rt):sat
-// Rd=asl(Rs,Rt):sat
-
-let Defs = [USR_OVF] in {
- def S2_asr_r_r_sat : T_S3op_shift32_Sat<"asr", 0b00>;
- def S2_asl_r_r_sat : T_S3op_shift32_Sat<"asl", 0b10>;
-}
-
-let hasNewValue = 1, hasSideEffects = 0 in
-class T_S3op_8 <string opc, bits<3> MinOp, bit isSat, bit isRnd, bit hasShift, bit hasSplat = 0>
- : SInst < (outs IntRegs:$Rd),
- (ins DoubleRegs:$Rss, IntRegs:$Rt),
- "$Rd = "#opc#"($Rss, $Rt"#!if(hasSplat, "*", "")#")"
- #!if(hasShift, ":<<1", "")
- #!if(isRnd, ":rnd", "")
- #!if(isSat, ":sat", ""),
- [], "", S_3op_tc_1_SLOT23 > {
- bits<5> Rd;
- bits<5> Rss;
- bits<5> Rt;
-
- let IClass = 0b1100;
-
- let Inst{27-24} = 0b0101;
- let Inst{20-16} = Rss;
- let Inst{12-8} = Rt;
- let Inst{7-5} = MinOp;
- let Inst{4-0} = Rd;
- }
-
-def S2_asr_r_svw_trun : T_S3op_8<"vasrw", 0b010, 0, 0, 0>;
-
-let Defs = [USR_OVF], Itinerary = S_3op_tc_2_SLOT23 in
-def S2_vcrotate : T_S3op_shiftVect < "vcrotate", 0b11, 0b00>;
-
-let hasSideEffects = 0 in
-class T_S3op_7 <string mnemonic, bit MajOp >
- : SInst <(outs DoubleRegs:$Rdd),
- (ins DoubleRegs:$Rss, DoubleRegs:$Rtt, u3_0Imm:$u3),
- "$Rdd = "#mnemonic#"($Rss, $Rtt, #$u3)" ,
- [], "", S_3op_tc_1_SLOT23 > {
- bits<5> Rdd;
- bits<5> Rss;
- bits<5> Rtt;
- bits<3> u3;
-
- let IClass = 0b1100;
-
- let Inst{27-24} = 0b0000;
- let Inst{23} = MajOp;
- let Inst{20-16} = !if(MajOp, Rss, Rtt);
- let Inst{12-8} = !if(MajOp, Rtt, Rss);
- let Inst{7-5} = u3;
- let Inst{4-0} = Rdd;
- }
-
-def S2_valignib : T_S3op_7 < "valignb", 0>;
-def S2_vspliceib : T_S3op_7 < "vspliceb", 1>;
-
-//===----------------------------------------------------------------------===//
-// Template class for 'insert bitfield' instructions
-//===----------------------------------------------------------------------===//
-let hasSideEffects = 0 in
-class T_S3op_insert <string mnemonic, RegisterClass RC>
- : SInst <(outs RC:$dst),
- (ins RC:$src1, RC:$src2, DoubleRegs:$src3),
- "$dst = "#mnemonic#"($src2, $src3)" ,
- [], "$src1 = $dst", S_3op_tc_1_SLOT23 > {
- bits<5> dst;
- bits<5> src2;
- bits<5> src3;
-
- let IClass = 0b1100;
-
- let Inst{27-26} = 0b10;
- let Inst{25-24} = !if(!eq(!cast<string>(RC), "IntRegs"), 0b00, 0b10);
- let Inst{23} = 0b0;
- let Inst{20-16} = src2;
- let Inst{12-8} = src3;
- let Inst{4-0} = dst;
- }
-
-let hasSideEffects = 0 in
-class T_S2op_insert <bits<4> RegTyBits, RegisterClass RC, Operand ImmOp>
- : SInst <(outs RC:$dst), (ins RC:$dst2, RC:$src1, ImmOp:$src2, ImmOp:$src3),
- "$dst = insert($src1, #$src2, #$src3)",
- [], "$dst2 = $dst", S_2op_tc_2_SLOT23> {
- bits<5> dst;
- bits<5> src1;
- bits<6> src2;
- bits<6> src3;
- bit bit23;
- bit bit13;
- string ImmOpStr = !cast<string>(ImmOp);
-
- let bit23 = !if (!eq(ImmOpStr, "u6_0Imm"), src3{5}, 0);
- let bit13 = !if (!eq(ImmOpStr, "u6_0Imm"), src2{5}, 0);
-
- let IClass = 0b1000;
-
- let Inst{27-24} = RegTyBits;
- let Inst{23} = bit23;
- let Inst{22-21} = src3{4-3};
- let Inst{20-16} = src1;
- let Inst{13} = bit13;
- let Inst{12-8} = src2{4-0};
- let Inst{7-5} = src3{2-0};
- let Inst{4-0} = dst;
- }
-
-// Rx=insert(Rs,Rtt)
-// Rx=insert(Rs,#u5,#U5)
-let hasNewValue = 1 in {
- def S2_insert_rp : T_S3op_insert <"insert", IntRegs>;
- def S2_insert : T_S2op_insert <0b1111, IntRegs, u5_0Imm>;
-}
-
-// Rxx=insert(Rss,Rtt)
-// Rxx=insert(Rss,#u6,#U6)
-def S2_insertp_rp : T_S3op_insert<"insert", DoubleRegs>;
-def S2_insertp : T_S2op_insert <0b0011, DoubleRegs, u6_0Imm>;
-
-
-//===----------------------------------------------------------------------===//
-// Template class for 'extract bitfield' instructions
-//===----------------------------------------------------------------------===//
-let hasNewValue = 1, hasSideEffects = 0 in
-class T_S3op_extract <string mnemonic, bits<2> MinOp>
- : SInst <(outs IntRegs:$Rd), (ins IntRegs:$Rs, DoubleRegs:$Rtt),
- "$Rd = "#mnemonic#"($Rs, $Rtt)",
- [], "", S_3op_tc_2_SLOT23 > {
- bits<5> Rd;
- bits<5> Rs;
- bits<5> Rtt;
-
- let IClass = 0b1100;
-
- let Inst{27-22} = 0b100100;
- let Inst{20-16} = Rs;
- let Inst{12-8} = Rtt;
- let Inst{7-6} = MinOp;
- let Inst{4-0} = Rd;
- }
-
-let hasSideEffects = 0 in
-class T_S2op_extract <string mnemonic, bits<4> RegTyBits,
- RegisterClass RC, Operand ImmOp>
- : SInst <(outs RC:$dst), (ins RC:$src1, ImmOp:$src2, ImmOp:$src3),
- "$dst = "#mnemonic#"($src1, #$src2, #$src3)",
- [], "", S_2op_tc_2_SLOT23> {
- bits<5> dst;
- bits<5> src1;
- bits<6> src2;
- bits<6> src3;
- bit bit23;
- bit bit13;
- string ImmOpStr = !cast<string>(ImmOp);
-
- let bit23 = !if (!eq(ImmOpStr, "u6_0Imm"), src3{5},
- !if (!eq(mnemonic, "extractu"), 0, 1));
-
- let bit13 = !if (!eq(ImmOpStr, "u6_0Imm"), src2{5}, 0);
-
- let IClass = 0b1000;
-
- let Inst{27-24} = RegTyBits;
- let Inst{23} = bit23;
- let Inst{22-21} = src3{4-3};
- let Inst{20-16} = src1;
- let Inst{13} = bit13;
- let Inst{12-8} = src2{4-0};
- let Inst{7-5} = src3{2-0};
- let Inst{4-0} = dst;
- }
-
-// Extract bitfield
-
-// Rdd=extractu(Rss,Rtt)
-// Rdd=extractu(Rss,#u6,#U6)
-def S2_extractup_rp : T_S3op_64 < "extractu", 0b00, 0b000, 0>;
-def S2_extractup : T_S2op_extract <"extractu", 0b0001, DoubleRegs, u6_0Imm>;
-
-// Rd=extractu(Rs,Rtt)
-// Rd=extractu(Rs,#u5,#U5)
-let hasNewValue = 1 in {
- def S2_extractu_rp : T_S3op_extract<"extractu", 0b00>;
- def S2_extractu : T_S2op_extract <"extractu", 0b1101, IntRegs, u5_0Imm>;
-}
-
-//===----------------------------------------------------------------------===//
-// :raw for of tableindx[bdhw] insns
-//===----------------------------------------------------------------------===//
-
-let hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
-class tableidxRaw<string OpStr, bits<2>MinOp>
- : SInst <(outs IntRegs:$Rx),
- (ins IntRegs:$_dst_, IntRegs:$Rs, u4_0Imm:$u4, s6_0Imm:$S6),
- "$Rx = "#OpStr#"($Rs, #$u4, #$S6):raw",
- [], "$Rx = $_dst_" > {
- bits<5> Rx;
- bits<5> Rs;
- bits<4> u4;
- bits<6> S6;
-
- let IClass = 0b1000;
-
- let Inst{27-24} = 0b0111;
- let Inst{23-22} = MinOp;
- let Inst{21} = u4{3};
- let Inst{20-16} = Rs;
- let Inst{13-8} = S6;
- let Inst{7-5} = u4{2-0};
- let Inst{4-0} = Rx;
- }
-
-def S2_tableidxb : tableidxRaw<"tableidxb", 0b00>;
-def S2_tableidxh : tableidxRaw<"tableidxh", 0b01>;
-def S2_tableidxw : tableidxRaw<"tableidxw", 0b10>;
-def S2_tableidxd : tableidxRaw<"tableidxd", 0b11>;
-
-//===----------------------------------------------------------------------===//
-// Template class for 'table index' instructions which are assembler mapped
-// to their :raw format.
-//===----------------------------------------------------------------------===//
-let isPseudo = 1 in
-class tableidx_goodsyntax <string mnemonic>
- : SInst <(outs IntRegs:$Rx),
- (ins IntRegs:$_dst_, IntRegs:$Rs, u4_0Imm:$u4, u5_0Imm:$u5),
- "$Rx = "#mnemonic#"($Rs, #$u4, #$u5)",
- [], "$Rx = $_dst_" >;
-
-def S2_tableidxb_goodsyntax : tableidx_goodsyntax<"tableidxb">;
-def S2_tableidxh_goodsyntax : tableidx_goodsyntax<"tableidxh">;
-def S2_tableidxw_goodsyntax : tableidx_goodsyntax<"tableidxw">;
-def S2_tableidxd_goodsyntax : tableidx_goodsyntax<"tableidxd">;
-
-//===----------------------------------------------------------------------===//
-// V3 Instructions +
-//===----------------------------------------------------------------------===//
-
-include "HexagonInstrInfoV3.td"
-
-//===----------------------------------------------------------------------===//
-// V3 Instructions -
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// V4 Instructions +
-//===----------------------------------------------------------------------===//
-
-include "HexagonInstrInfoV4.td"
-
-//===----------------------------------------------------------------------===//
-// V4 Instructions -
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// V5 Instructions +
-//===----------------------------------------------------------------------===//
-
-include "HexagonInstrInfoV5.td"
-
-//===----------------------------------------------------------------------===//
-// V5 Instructions -
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// V60 Instructions +
-//===----------------------------------------------------------------------===//
-
-include "HexagonInstrInfoV60.td"
-
-//===----------------------------------------------------------------------===//
-// V60 Instructions -
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// ALU32/64/Vector +
-//===----------------------------------------------------------------------===///
-
-include "HexagonInstrInfoVector.td"
-
-include "HexagonInstrAlias.td"
-include "HexagonSystemInst.td"
-
Removed: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV3.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV3.td?rev=294752&view=auto
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV3.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV3.td (removed)
@@ -1,215 +0,0 @@
-//=- HexagonInstrInfoV3.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file describes the Hexagon V3 instructions in TableGen format.
-//
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// J +
-//===----------------------------------------------------------------------===//
-// Call subroutine.
-let isCall = 1, hasSideEffects = 1, isPredicable = 1,
- isExtended = 0, isExtendable = 1, opExtendable = 0,
- isExtentSigned = 1, opExtentBits = 24, opExtentAlign = 2 in
-class T_Call<bit CSR, string ExtStr>
- : JInst<(outs), (ins calltarget:$dst),
- "call " # ExtStr # "$dst", [], "", J_tc_2early_SLOT23> {
- let BaseOpcode = "call";
- bits<24> dst;
-
- let Defs = !if (CSR, VolatileV3.Regs, []);
- let IClass = 0b0101;
- let Inst{27-25} = 0b101;
- let Inst{24-16,13-1} = dst{23-2};
- let Inst{0} = 0b0;
-}
-
-let isCall = 1, hasSideEffects = 1, isPredicated = 1,
- isExtended = 0, isExtendable = 1, opExtendable = 1,
- isExtentSigned = 1, opExtentBits = 17, opExtentAlign = 2 in
-class T_CallPred<bit CSR, bit IfTrue, string ExtStr>
- : JInst<(outs), (ins PredRegs:$Pu, calltarget:$dst),
- CondStr<"$Pu", IfTrue, 0>.S # "call " # ExtStr # "$dst",
- [], "", J_tc_2early_SLOT23> {
- let BaseOpcode = "call";
- let isPredicatedFalse = !if(IfTrue,0,1);
- bits<2> Pu;
- bits<17> dst;
-
- let Defs = !if (CSR, VolatileV3.Regs, []);
- let IClass = 0b0101;
- let Inst{27-24} = 0b1101;
- let Inst{23-22,20-16,13,7-1} = dst{16-2};
- let Inst{21} = !if(IfTrue,0,1);
- let Inst{11} = 0b0;
- let Inst{9-8} = Pu;
-}
-
-multiclass T_Calls<bit CSR, string ExtStr> {
- def NAME : T_Call<CSR, ExtStr>;
- def t : T_CallPred<CSR, 1, ExtStr>;
- def f : T_CallPred<CSR, 0, ExtStr>;
-}
-
-defm J2_call: T_Calls<1, "">, PredRel;
-
-let isCodeGenOnly = 1, isCall = 1, hasSideEffects = 1,
- Defs = VolatileV3.Regs, isPseudo = 1 in
-def PS_call_nr : T_Call<1, "">, PredRel;
-
-let isCodeGenOnly = 1, isCall = 1, hasSideEffects = 1,
- Defs = [PC, R31, R6, R7, P0] in
-def PS_call_stk : T_Call<0, "">, PredRel;
-
-//===----------------------------------------------------------------------===//
-// J -
-//===----------------------------------------------------------------------===//
-
-
-//===----------------------------------------------------------------------===//
-// JR +
-//===----------------------------------------------------------------------===//
-// Call subroutine from register.
-
-let isCodeGenOnly = 1, Defs = VolatileV3.Regs in {
- def PS_callr_nr : JUMPR_MISC_CALLR<0, 1>; // Call, no return.
-}
-
-//===----------------------------------------------------------------------===//
-// JR -
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// ALU64/ALU +
-//===----------------------------------------------------------------------===//
-
-let Defs = [USR_OVF], Itinerary = ALU64_tc_2_SLOT23 in
-def A2_addpsat : T_ALU64_arith<"add", 0b011, 0b101, 1, 0, 1>;
-
-class T_ALU64_addsp_hl<string suffix, bits<3> MinOp>
- : T_ALU64_rr<"add", suffix, 0b0011, 0b011, MinOp, 0, 0, "">;
-
-def A2_addspl : T_ALU64_addsp_hl<":raw:lo", 0b110>;
-def A2_addsph : T_ALU64_addsp_hl<":raw:hi", 0b111>;
-
-let hasSideEffects = 0, isAsmParserOnly = 1 in
-def A2_addsp : ALU64_rr<(outs DoubleRegs:$Rd),
- (ins IntRegs:$Rs, DoubleRegs:$Rt), "$Rd = add($Rs, $Rt)", [],
- "", ALU64_tc_1_SLOT23>;
-
-
-let hasSideEffects = 0 in
-class T_XTYPE_MIN_MAX_P<bit isMax, bit isUnsigned>
- : ALU64Inst<(outs DoubleRegs:$Rd), (ins DoubleRegs:$Rt, DoubleRegs:$Rs),
- "$Rd = "#!if(isMax,"max","min")#!if(isUnsigned,"u","")
- #"($Rt, $Rs)", [], "", ALU64_tc_2_SLOT23> {
- bits<5> Rd;
- bits<5> Rs;
- bits<5> Rt;
-
- let IClass = 0b1101;
-
- let Inst{27-23} = 0b00111;
- let Inst{22-21} = !if(isMax, 0b10, 0b01);
- let Inst{20-16} = !if(isMax, Rt, Rs);
- let Inst{12-8} = !if(isMax, Rs, Rt);
- let Inst{7} = 0b1;
- let Inst{6} = !if(isMax, 0b0, 0b1);
- let Inst{5} = isUnsigned;
- let Inst{4-0} = Rd;
-}
-
-def A2_minp : T_XTYPE_MIN_MAX_P<0, 0>;
-def A2_minup : T_XTYPE_MIN_MAX_P<0, 1>;
-def A2_maxp : T_XTYPE_MIN_MAX_P<1, 0>;
-def A2_maxup : T_XTYPE_MIN_MAX_P<1, 1>;
-
-//===----------------------------------------------------------------------===//
-// ALU64/ALU -
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// :raw form of vrcmpys:hi/lo insns
-//===----------------------------------------------------------------------===//
-// Vector reduce complex multiply by scalar.
-let Defs = [USR_OVF], hasSideEffects = 0 in
-class T_vrcmpRaw<string HiLo, bits<3>MajOp>:
- MInst<(outs DoubleRegs:$Rdd),
- (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
- "$Rdd = vrcmpys($Rss, $Rtt):<<1:sat:raw:"#HiLo, []> {
- bits<5> Rdd;
- bits<5> Rss;
- bits<5> Rtt;
-
- let IClass = 0b1110;
-
- let Inst{27-24} = 0b1000;
- let Inst{23-21} = MajOp;
- let Inst{20-16} = Rss;
- let Inst{12-8} = Rtt;
- let Inst{7-5} = 0b100;
- let Inst{4-0} = Rdd;
-}
-
-def M2_vrcmpys_s1_h: T_vrcmpRaw<"hi", 0b101>;
-def M2_vrcmpys_s1_l: T_vrcmpRaw<"lo", 0b111>;
-
-// Assembler mapped to M2_vrcmpys_s1_h or M2_vrcmpys_s1_l
-let hasSideEffects = 0, isAsmParserOnly = 1 in
-def M2_vrcmpys_s1
- : MInst<(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss, IntRegs:$Rt),
- "$Rdd=vrcmpys($Rss,$Rt):<<1:sat">;
-
-// Vector reduce complex multiply by scalar with accumulation.
-let Defs = [USR_OVF], hasSideEffects = 0 in
-class T_vrcmpys_acc<string HiLo, bits<3>MajOp>:
- MInst <(outs DoubleRegs:$Rxx),
- (ins DoubleRegs:$_src_, DoubleRegs:$Rss, DoubleRegs:$Rtt),
- "$Rxx += vrcmpys($Rss, $Rtt):<<1:sat:raw:"#HiLo, [],
- "$Rxx = $_src_"> {
- bits<5> Rxx;
- bits<5> Rss;
- bits<5> Rtt;
-
- let IClass = 0b1110;
-
- let Inst{27-24} = 0b1010;
- let Inst{23-21} = MajOp;
- let Inst{20-16} = Rss;
- let Inst{12-8} = Rtt;
- let Inst{7-5} = 0b100;
- let Inst{4-0} = Rxx;
- }
-
-def M2_vrcmpys_acc_s1_h: T_vrcmpys_acc<"hi", 0b101>;
-def M2_vrcmpys_acc_s1_l: T_vrcmpys_acc<"lo", 0b111>;
-
-// Assembler mapped to M2_vrcmpys_acc_s1_h or M2_vrcmpys_acc_s1_l
-
-let isAsmParserOnly = 1 in
-def M2_vrcmpys_acc_s1
- : MInst <(outs DoubleRegs:$dst),
- (ins DoubleRegs:$dst2, DoubleRegs:$src1, IntRegs:$src2),
- "$dst += vrcmpys($src1, $src2):<<1:sat", [],
- "$dst2 = $dst">;
-
-def M2_vrcmpys_s1rp_h : T_MType_vrcmpy <"vrcmpys", 0b101, 0b110, 1>;
-def M2_vrcmpys_s1rp_l : T_MType_vrcmpy <"vrcmpys", 0b101, 0b111, 0>;
-
-// Assembler mapped to M2_vrcmpys_s1rp_h or M2_vrcmpys_s1rp_l
-let isAsmParserOnly = 1 in
-def M2_vrcmpys_s1rp
- : MInst <(outs IntRegs:$Rd), (ins DoubleRegs:$Rss, IntRegs:$Rt),
- "$Rd=vrcmpys($Rss,$Rt):<<1:rnd:sat">;
-
-
-// S2_cabacdecbin: Cabac decode bin.
-let Defs = [P0], isPredicateLate = 1, Itinerary = S_3op_tc_1_SLOT23 in
-def S2_cabacdecbin : T_S3op_64 < "decbin", 0b11, 0b110, 0>;
Removed: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td?rev=294752&view=auto
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td (removed)
@@ -1,3318 +0,0 @@
-//=- HexagonInstrInfoV4.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file describes the Hexagon V4 instructions in TableGen format.
-//
-//===----------------------------------------------------------------------===//
-
-def DuplexIClass0: InstDuplex < 0 >;
-def DuplexIClass1: InstDuplex < 1 >;
-def DuplexIClass2: InstDuplex < 2 >;
-let isExtendable = 1 in {
- def DuplexIClass3: InstDuplex < 3 >;
- def DuplexIClass4: InstDuplex < 4 >;
- def DuplexIClass5: InstDuplex < 5 >;
- def DuplexIClass6: InstDuplex < 6 >;
- def DuplexIClass7: InstDuplex < 7 >;
-}
-def DuplexIClass8: InstDuplex < 8 >;
-def DuplexIClass9: InstDuplex < 9 >;
-def DuplexIClassA: InstDuplex < 0xA >;
-def DuplexIClassB: InstDuplex < 0xB >;
-def DuplexIClassC: InstDuplex < 0xC >;
-def DuplexIClassD: InstDuplex < 0xD >;
-def DuplexIClassE: InstDuplex < 0xE >;
-def DuplexIClassF: InstDuplex < 0xF >;
-
-let hasSideEffects = 0 in
-class T_Immext<Operand ImmType>
- : EXTENDERInst<(outs), (ins ImmType:$imm),
- "immext(#$imm)", []> {
- bits<32> imm;
- let IClass = 0b0000;
-
- let Inst{27-16} = imm{31-20};
- let Inst{13-0} = imm{19-6};
- }
-
-def A4_ext : T_Immext<u26_6Imm>;
-
-// Hexagon V4 Architecture spec defines 8 instruction classes:
-// LD ST ALU32 XTYPE J JR MEMOP NV CR SYSTEM(system is not implemented in the
-// compiler)
-
-// LD Instructions:
-// ========================================
-// Loads (8/16/32/64 bit)
-// Deallocframe
-
-// ST Instructions:
-// ========================================
-// Stores (8/16/32/64 bit)
-// Allocframe
-
-// ALU32 Instructions:
-// ========================================
-// Arithmetic / Logical (32 bit)
-// Vector Halfword
-
-// XTYPE Instructions (32/64 bit):
-// ========================================
-// Arithmetic, Logical, Bit Manipulation
-// Multiply (Integer, Fractional, Complex)
-// Permute / Vector Permute Operations
-// Predicate Operations
-// Shift / Shift with Add/Sub/Logical
-// Vector Byte ALU
-// Vector Halfword (ALU, Shift, Multiply)
-// Vector Word (ALU, Shift)
-
-// J Instructions:
-// ========================================
-// Jump/Call PC-relative
-
-// JR Instructions:
-// ========================================
-// Jump/Call Register
-
-// MEMOP Instructions:
-// ========================================
-// Operation on memory (8/16/32 bit)
-
-// NV Instructions:
-// ========================================
-// New-value Jumps
-// New-value Stores
-
-// CR Instructions:
-// ========================================
-// Control-Register Transfers
-// Hardware Loop Setup
-// Predicate Logicals & Reductions
-
-// SYSTEM Instructions (not implemented in the compiler):
-// ========================================
-// Prefetch
-// Cache Maintenance
-// Bus Operations
-
-
-//===----------------------------------------------------------------------===//
-// ALU32 +
-//===----------------------------------------------------------------------===//
-
-class T_ALU32_3op_not<string mnemonic, bits<3> MajOp, bits<3> MinOp,
- bit OpsRev>
- : T_ALU32_3op<mnemonic, MajOp, MinOp, OpsRev, 0> {
- let AsmString = "$Rd = "#mnemonic#"($Rs, ~$Rt)";
-}
-
-let BaseOpcode = "andn_rr", CextOpcode = "andn" in
-def A4_andn : T_ALU32_3op_not<"and", 0b001, 0b100, 1>;
-let BaseOpcode = "orn_rr", CextOpcode = "orn" in
-def A4_orn : T_ALU32_3op_not<"or", 0b001, 0b101, 1>;
-
-let CextOpcode = "rcmp.eq" in
-def A4_rcmpeq : T_ALU32_3op<"cmp.eq", 0b011, 0b010, 0, 1>;
-let CextOpcode = "!rcmp.eq" in
-def A4_rcmpneq : T_ALU32_3op<"!cmp.eq", 0b011, 0b011, 0, 1>;
-
-def C4_cmpneq : T_ALU32_3op_cmp<"!cmp.eq", 0b00, 1, 1>;
-def C4_cmplte : T_ALU32_3op_cmp<"!cmp.gt", 0b10, 1, 0>;
-def C4_cmplteu : T_ALU32_3op_cmp<"!cmp.gtu", 0b11, 1, 0>;
-
-class T_CMP_rrbh<string mnemonic, bits<3> MinOp, bit IsComm>
- : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
- "$Pd = "#mnemonic#"($Rs, $Rt)", [], "", S_3op_tc_2early_SLOT23>,
- ImmRegRel {
- let InputType = "reg";
- let CextOpcode = mnemonic;
- let isCompare = 1;
- let isCommutable = IsComm;
- let hasSideEffects = 0;
-
- bits<2> Pd;
- bits<5> Rs;
- bits<5> Rt;
-
- let IClass = 0b1100;
- let Inst{27-21} = 0b0111110;
- let Inst{20-16} = Rs;
- let Inst{12-8} = Rt;
- let Inst{7-5} = MinOp;
- let Inst{1-0} = Pd;
-}
-
-def A4_cmpbeq : T_CMP_rrbh<"cmpb.eq", 0b110, 1>;
-def A4_cmpbgt : T_CMP_rrbh<"cmpb.gt", 0b010, 0>;
-def A4_cmpbgtu : T_CMP_rrbh<"cmpb.gtu", 0b111, 0>;
-def A4_cmpheq : T_CMP_rrbh<"cmph.eq", 0b011, 1>;
-def A4_cmphgt : T_CMP_rrbh<"cmph.gt", 0b100, 0>;
-def A4_cmphgtu : T_CMP_rrbh<"cmph.gtu", 0b101, 0>;
-
-class T_CMP_ribh<string mnemonic, bits<2> MajOp, bit IsHalf, bit IsComm,
- Operand ImmType, bit IsImmExt, bit IsImmSigned, int ImmBits>
- : ALU64Inst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, ImmType:$Imm),
- "$Pd = "#mnemonic#"($Rs, #$Imm)", [], "", ALU64_tc_2early_SLOT23>,
- ImmRegRel {
- let InputType = "imm";
- let CextOpcode = mnemonic;
- let isCompare = 1;
- let isCommutable = IsComm;
- let hasSideEffects = 0;
- let isExtendable = IsImmExt;
- let opExtendable = !if (IsImmExt, 2, 0);
- let isExtentSigned = IsImmSigned;
- let opExtentBits = ImmBits;
-
- bits<2> Pd;
- bits<5> Rs;
- bits<8> Imm;
-
- let IClass = 0b1101;
- let Inst{27-24} = 0b1101;
- let Inst{22-21} = MajOp;
- let Inst{20-16} = Rs;
- let Inst{12-5} = Imm;
- let Inst{4} = 0b0;
- let Inst{3} = IsHalf;
- let Inst{1-0} = Pd;
-}
-
-def A4_cmpbeqi : T_CMP_ribh<"cmpb.eq", 0b00, 0, 1, u8_0Imm, 0, 0, 8>;
-def A4_cmpbgti : T_CMP_ribh<"cmpb.gt", 0b01, 0, 0, s8_0Imm, 0, 1, 8>;
-def A4_cmpbgtui : T_CMP_ribh<"cmpb.gtu", 0b10, 0, 0, u7_0Ext, 1, 0, 7>;
-def A4_cmpheqi : T_CMP_ribh<"cmph.eq", 0b00, 1, 1, s8_0Ext, 1, 1, 8>;
-def A4_cmphgti : T_CMP_ribh<"cmph.gt", 0b01, 1, 0, s8_0Ext, 1, 1, 8>;
-def A4_cmphgtui : T_CMP_ribh<"cmph.gtu", 0b10, 1, 0, u7_0Ext, 1, 0, 7>;
-
-class T_RCMP_EQ_ri<string mnemonic, bit IsNeg>
- : ALU32_ri<(outs IntRegs:$Rd), (ins IntRegs:$Rs, s8_0Ext:$s8),
- "$Rd = "#mnemonic#"($Rs, #$s8)", [], "", ALU32_2op_tc_1_SLOT0123>,
- ImmRegRel {
- let InputType = "imm";
- let CextOpcode = !if (IsNeg, "!rcmp.eq", "rcmp.eq");
- let isExtendable = 1;
- let opExtendable = 2;
- let isExtentSigned = 1;
- let opExtentBits = 8;
- let hasNewValue = 1;
-
- bits<5> Rd;
- bits<5> Rs;
- bits<8> s8;
-
- let IClass = 0b0111;
- let Inst{27-24} = 0b0011;
- let Inst{22} = 0b1;
- let Inst{21} = IsNeg;
- let Inst{20-16} = Rs;
- let Inst{13} = 0b1;
- let Inst{12-5} = s8;
- let Inst{4-0} = Rd;
-}
-
-def A4_rcmpeqi : T_RCMP_EQ_ri<"cmp.eq", 0>;
-def A4_rcmpneqi : T_RCMP_EQ_ri<"!cmp.eq", 1>;
-
-//===----------------------------------------------------------------------===//
-// ALU32 -
-//===----------------------------------------------------------------------===//
-
-
-//===----------------------------------------------------------------------===//
-// ALU32/PERM +
-//===----------------------------------------------------------------------===//
-
-// Combine a word and an immediate into a register pair.
-let hasSideEffects = 0, isExtentSigned = 1, isExtendable = 1,
- opExtentBits = 8 in
-class T_Combine1 <bits<2> MajOp, dag ins, string AsmStr>
- : ALU32Inst <(outs DoubleRegs:$Rdd), ins, AsmStr> {
- bits<5> Rdd;
- bits<5> Rs;
- bits<8> s8;
-
- let IClass = 0b0111;
- let Inst{27-24} = 0b0011;
- let Inst{22-21} = MajOp;
- let Inst{20-16} = Rs;
- let Inst{13} = 0b1;
- let Inst{12-5} = s8;
- let Inst{4-0} = Rdd;
- }
-
-let opExtendable = 2 in
-def A4_combineri : T_Combine1<0b00, (ins IntRegs:$Rs, s8_0Ext:$s8),
- "$Rdd = combine($Rs, #$s8)">;
-
-let opExtendable = 1 in
-def A4_combineir : T_Combine1<0b01, (ins s8_0Ext:$s8, IntRegs:$Rs),
- "$Rdd = combine(#$s8, $Rs)">;
-
-// A4_combineii: Set two small immediates.
-let hasSideEffects = 0, isExtendable = 1, opExtentBits = 6, opExtendable = 2 in
-def A4_combineii: ALU32Inst<(outs DoubleRegs:$Rdd), (ins s8_0Imm:$s8, u6_0Ext:$U6),
- "$Rdd = combine(#$s8, #$U6)"> {
- bits<5> Rdd;
- bits<8> s8;
- bits<6> U6;
-
- let IClass = 0b0111;
- let Inst{27-23} = 0b11001;
- let Inst{20-16} = U6{5-1};
- let Inst{13} = U6{0};
- let Inst{12-5} = s8;
- let Inst{4-0} = Rdd;
- }
-
-//===----------------------------------------------------------------------===//
-// ALU32/PERM -
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// LD +
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// Template class for load instructions with Absolute set addressing mode.
-//===----------------------------------------------------------------------===//
-let isExtended = 1, opExtendable = 2, opExtentBits = 6, addrMode = AbsoluteSet,
- hasSideEffects = 0 in
-class T_LD_abs_set<string mnemonic, RegisterClass RC, bits<4>MajOp>:
- LDInst<(outs RC:$dst1, IntRegs:$dst2),
- (ins u6_0Ext:$addr),
- "$dst1 = "#mnemonic#"($dst2 = #$addr)",
- []> {
- bits<7> name;
- bits<5> dst1;
- bits<5> dst2;
- bits<6> addr;
-
- let IClass = 0b1001;
- let Inst{27-25} = 0b101;
- let Inst{24-21} = MajOp;
- let Inst{13-12} = 0b01;
- let Inst{4-0} = dst1;
- let Inst{20-16} = dst2;
- let Inst{11-8} = addr{5-2};
- let Inst{6-5} = addr{1-0};
-}
-
-let accessSize = ByteAccess, hasNewValue = 1 in {
- def L4_loadrb_ap : T_LD_abs_set <"memb", IntRegs, 0b1000>;
- def L4_loadrub_ap : T_LD_abs_set <"memub", IntRegs, 0b1001>;
-}
-
-let accessSize = HalfWordAccess, hasNewValue = 1 in {
- def L4_loadrh_ap : T_LD_abs_set <"memh", IntRegs, 0b1010>;
- def L4_loadruh_ap : T_LD_abs_set <"memuh", IntRegs, 0b1011>;
- def L4_loadbsw2_ap : T_LD_abs_set <"membh", IntRegs, 0b0001>;
- def L4_loadbzw2_ap : T_LD_abs_set <"memubh", IntRegs, 0b0011>;
-}
-
-let accessSize = WordAccess, hasNewValue = 1 in
- def L4_loadri_ap : T_LD_abs_set <"memw", IntRegs, 0b1100>;
-
-let accessSize = WordAccess in {
- def L4_loadbzw4_ap : T_LD_abs_set <"memubh", DoubleRegs, 0b0101>;
- def L4_loadbsw4_ap : T_LD_abs_set <"membh", DoubleRegs, 0b0111>;
-}
-
-let accessSize = DoubleWordAccess in
-def L4_loadrd_ap : T_LD_abs_set <"memd", DoubleRegs, 0b1110>;
-
-let accessSize = ByteAccess in
- def L4_loadalignb_ap : T_LD_abs_set <"memb_fifo", DoubleRegs, 0b0100>;
-
-let accessSize = HalfWordAccess in
-def L4_loadalignh_ap : T_LD_abs_set <"memh_fifo", DoubleRegs, 0b0010>;
-
-// Load - Indirect with long offset
-let InputType = "imm", addrMode = BaseLongOffset, isExtended = 1,
-opExtentBits = 6, opExtendable = 3 in
-class T_LoadAbsReg <string mnemonic, string CextOp, RegisterClass RC,
- bits<4> MajOp>
- : LDInst <(outs RC:$dst), (ins IntRegs:$src1, u2_0Imm:$src2, u6_0Ext:$src3),
- "$dst = "#mnemonic#"($src1<<#$src2 + #$src3)",
- [] >, ImmRegShl {
- bits<5> dst;
- bits<5> src1;
- bits<2> src2;
- bits<6> src3;
- let CextOpcode = CextOp;
- let hasNewValue = !if (!eq(!cast<string>(RC), "DoubleRegs"), 0, 1);
-
- let IClass = 0b1001;
- let Inst{27-25} = 0b110;
- let Inst{24-21} = MajOp;
- let Inst{20-16} = src1;
- let Inst{13} = src2{1};
- let Inst{12} = 0b1;
- let Inst{11-8} = src3{5-2};
- let Inst{7} = src2{0};
- let Inst{6-5} = src3{1-0};
- let Inst{4-0} = dst;
- }
-
-let accessSize = ByteAccess in {
- def L4_loadrb_ur : T_LoadAbsReg<"memb", "LDrib", IntRegs, 0b1000>;
- def L4_loadrub_ur : T_LoadAbsReg<"memub", "LDriub", IntRegs, 0b1001>;
- def L4_loadalignb_ur : T_LoadAbsReg<"memb_fifo", "LDrib_fifo",
- DoubleRegs, 0b0100>;
-}
-
-let accessSize = HalfWordAccess in {
- def L4_loadrh_ur : T_LoadAbsReg<"memh", "LDrih", IntRegs, 0b1010>;
- def L4_loadruh_ur : T_LoadAbsReg<"memuh", "LDriuh", IntRegs, 0b1011>;
- def L4_loadbsw2_ur : T_LoadAbsReg<"membh", "LDribh2", IntRegs, 0b0001>;
- def L4_loadbzw2_ur : T_LoadAbsReg<"memubh", "LDriubh2", IntRegs, 0b0011>;
- def L4_loadalignh_ur : T_LoadAbsReg<"memh_fifo", "LDrih_fifo",
- DoubleRegs, 0b0010>;
-}
-
-let accessSize = WordAccess in {
- def L4_loadri_ur : T_LoadAbsReg<"memw", "LDriw", IntRegs, 0b1100>;
- def L4_loadbsw4_ur : T_LoadAbsReg<"membh", "LDribh4", DoubleRegs, 0b0111>;
- def L4_loadbzw4_ur : T_LoadAbsReg<"memubh", "LDriubh4", DoubleRegs, 0b0101>;
-}
-
-let accessSize = DoubleWordAccess in
-def L4_loadrd_ur : T_LoadAbsReg<"memd", "LDrid", DoubleRegs, 0b1110>;
-
-
-//===----------------------------------------------------------------------===//
-// Template classes for the non-predicated load instructions with
-// base + register offset addressing mode
-//===----------------------------------------------------------------------===//
-class T_load_rr <string mnemonic, RegisterClass RC, bits<3> MajOp>:
- LDInst<(outs RC:$dst), (ins IntRegs:$src1, IntRegs:$src2, u2_0Imm:$u2),
- "$dst = "#mnemonic#"($src1 + $src2<<#$u2)",
- [], "", V4LDST_tc_ld_SLOT01>, ImmRegShl, AddrModeRel {
- bits<5> dst;
- bits<5> src1;
- bits<5> src2;
- bits<2> u2;
-
- let IClass = 0b0011;
-
- let Inst{27-24} = 0b1010;
- let Inst{23-21} = MajOp;
- let Inst{20-16} = src1;
- let Inst{12-8} = src2;
- let Inst{13} = u2{1};
- let Inst{7} = u2{0};
- let Inst{4-0} = dst;
- }
-
-//===----------------------------------------------------------------------===//
-// Template classes for the predicated load instructions with
-// base + register offset addressing mode
-//===----------------------------------------------------------------------===//
-let isPredicated = 1 in
-class T_pload_rr <string mnemonic, RegisterClass RC, bits<3> MajOp,
- bit isNot, bit isPredNew>:
- LDInst <(outs RC:$dst),
- (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2_0Imm:$u2),
- !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
- ") ")#"$dst = "#mnemonic#"($src2+$src3<<#$u2)",
- [], "", V4LDST_tc_ld_SLOT01>, AddrModeRel {
- bits<5> dst;
- bits<2> src1;
- bits<5> src2;
- bits<5> src3;
- bits<2> u2;
-
- let isPredicatedFalse = isNot;
- let isPredicatedNew = isPredNew;
-
- let IClass = 0b0011;
-
- let Inst{27-26} = 0b00;
- let Inst{25} = isPredNew;
- let Inst{24} = isNot;
- let Inst{23-21} = MajOp;
- let Inst{20-16} = src2;
- let Inst{12-8} = src3;
- let Inst{13} = u2{1};
- let Inst{7} = u2{0};
- let Inst{6-5} = src1;
- let Inst{4-0} = dst;
- }
-
-//===----------------------------------------------------------------------===//
-// multiclass for load instructions with base + register offset
-// addressing mode
-//===----------------------------------------------------------------------===//
-let hasSideEffects = 0, addrMode = BaseRegOffset in
-multiclass ld_idxd_shl <string mnemonic, string CextOp, RegisterClass RC,
- bits<3> MajOp > {
- let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl,
- InputType = "reg" in {
- let isPredicable = 1 in
- def L4_#NAME#_rr : T_load_rr <mnemonic, RC, MajOp>;
-
- // Predicated
- def L4_p#NAME#t_rr : T_pload_rr <mnemonic, RC, MajOp, 0, 0>;
- def L4_p#NAME#f_rr : T_pload_rr <mnemonic, RC, MajOp, 1, 0>;
-
- // Predicated new
- def L4_p#NAME#tnew_rr : T_pload_rr <mnemonic, RC, MajOp, 0, 1>;
- def L4_p#NAME#fnew_rr : T_pload_rr <mnemonic, RC, MajOp, 1, 1>;
- }
-}
-
-let hasNewValue = 1, accessSize = ByteAccess in {
- defm loadrb : ld_idxd_shl<"memb", "LDrib", IntRegs, 0b000>;
- defm loadrub : ld_idxd_shl<"memub", "LDriub", IntRegs, 0b001>;
-}
-
-let hasNewValue = 1, accessSize = HalfWordAccess in {
- defm loadrh : ld_idxd_shl<"memh", "LDrih", IntRegs, 0b010>;
- defm loadruh : ld_idxd_shl<"memuh", "LDriuh", IntRegs, 0b011>;
-}
-
-let hasNewValue = 1, accessSize = WordAccess in
-defm loadri : ld_idxd_shl<"memw", "LDriw", IntRegs, 0b100>;
-
-let accessSize = DoubleWordAccess in
-defm loadrd : ld_idxd_shl<"memd", "LDrid", DoubleRegs, 0b110>;
-
-//===----------------------------------------------------------------------===//
-// LD -
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// ST +
-//===----------------------------------------------------------------------===//
-///
-//===----------------------------------------------------------------------===//
-// Template class for store instructions with Absolute set addressing mode.
-//===----------------------------------------------------------------------===//
-let isExtended = 1, opExtendable = 1, opExtentBits = 6,
- addrMode = AbsoluteSet in
-class T_ST_absset <string mnemonic, string BaseOp, RegisterClass RC,
- bits<3> MajOp, MemAccessSize AccessSz, bit isHalf = 0>
- : STInst<(outs IntRegs:$dst),
- (ins u6_0Ext:$addr, RC:$src),
- mnemonic#"($dst = #$addr) = $src"#!if(isHalf, ".h","")>, NewValueRel {
- bits<5> dst;
- bits<6> addr;
- bits<5> src;
- let accessSize = AccessSz;
- let BaseOpcode = BaseOp#"_AbsSet";
-
- // Store upper-half and store doubleword cannot be NV.
- let isNVStorable = !if (!eq(mnemonic, "memd"), 0, !if(isHalf,0,1));
-
- let IClass = 0b1010;
-
- let Inst{27-24} = 0b1011;
- let Inst{23-21} = MajOp;
- let Inst{20-16} = dst;
- let Inst{13} = 0b0;
- let Inst{12-8} = src;
- let Inst{7} = 0b1;
- let Inst{5-0} = addr;
- }
-
-def S4_storerb_ap : T_ST_absset <"memb", "STrib", IntRegs, 0b000, ByteAccess>;
-def S4_storerh_ap : T_ST_absset <"memh", "STrih", IntRegs, 0b010,
- HalfWordAccess>;
-def S4_storeri_ap : T_ST_absset <"memw", "STriw", IntRegs, 0b100, WordAccess>;
-
-let isNVStorable = 0 in {
- def S4_storerf_ap : T_ST_absset <"memh", "STrif", IntRegs,
- 0b011, HalfWordAccess, 1>;
- def S4_storerd_ap : T_ST_absset <"memd", "STrid", DoubleRegs,
- 0b110, DoubleWordAccess>;
-}
-
-let opExtendable = 1, isNewValue = 1, isNVStore = 1, opNewValue = 2,
-isExtended = 1, opExtentBits= 6 in
-class T_ST_absset_nv <string mnemonic, string BaseOp, bits<2> MajOp,
- MemAccessSize AccessSz >
- : NVInst <(outs IntRegs:$dst),
- (ins u6_0Ext:$addr, IntRegs:$src),
- mnemonic#"($dst = #$addr) = $src.new">, NewValueRel {
- bits<5> dst;
- bits<6> addr;
- bits<3> src;
- let accessSize = AccessSz;
- let BaseOpcode = BaseOp#"_AbsSet";
-
- let IClass = 0b1010;
-
- let Inst{27-21} = 0b1011101;
- let Inst{20-16} = dst;
- let Inst{13-11} = 0b000;
- let Inst{12-11} = MajOp;
- let Inst{10-8} = src;
- let Inst{7} = 0b1;
- let Inst{5-0} = addr;
- }
-
-let mayStore = 1, addrMode = AbsoluteSet in {
- def S4_storerbnew_ap : T_ST_absset_nv <"memb", "STrib", 0b00, ByteAccess>;
- def S4_storerhnew_ap : T_ST_absset_nv <"memh", "STrih", 0b01, HalfWordAccess>;
- def S4_storerinew_ap : T_ST_absset_nv <"memw", "STriw", 0b10, WordAccess>;
-}
-
-let isExtended = 1, opExtendable = 2, opExtentBits = 6, InputType = "imm",
- addrMode = BaseLongOffset, AddedComplexity = 40 in
-class T_StoreAbsReg <string mnemonic, string CextOp, RegisterClass RC,
- bits<3> MajOp, MemAccessSize AccessSz, bit isHalf = 0>
- : STInst<(outs),
- (ins IntRegs:$src1, u2_0Imm:$src2, u6_0Ext:$src3, RC:$src4),
- mnemonic#"($src1<<#$src2 + #$src3) = $src4"#!if(isHalf, ".h",""),
- []>, ImmRegShl, NewValueRel {
-
- bits<5> src1;
- bits<2> src2;
- bits<6> src3;
- bits<5> src4;
-
- let accessSize = AccessSz;
- let CextOpcode = CextOp;
- let BaseOpcode = CextOp#"_shl";
-
- // Store upper-half and store doubleword cannot be NV.
- let isNVStorable = !if (!eq(mnemonic, "memd"), 0, !if(isHalf,0,1));
-
- let IClass = 0b1010;
-
- let Inst{27-24} =0b1101;
- let Inst{23-21} = MajOp;
- let Inst{20-16} = src1;
- let Inst{13} = src2{1};
- let Inst{12-8} = src4;
- let Inst{7} = 0b1;
- let Inst{6} = src2{0};
- let Inst{5-0} = src3;
-}
-
-def S4_storerb_ur : T_StoreAbsReg <"memb", "STrib", IntRegs, 0b000, ByteAccess>;
-def S4_storerh_ur : T_StoreAbsReg <"memh", "STrih", IntRegs, 0b010,
- HalfWordAccess>;
-def S4_storerf_ur : T_StoreAbsReg <"memh", "STrif", IntRegs, 0b011,
- HalfWordAccess, 1>;
-def S4_storeri_ur : T_StoreAbsReg <"memw", "STriw", IntRegs, 0b100, WordAccess>;
-def S4_storerd_ur : T_StoreAbsReg <"memd", "STrid", DoubleRegs, 0b110,
- DoubleWordAccess>;
-
-let mayStore = 1, isNVStore = 1, isExtended = 1, addrMode = BaseLongOffset,
- opExtentBits = 6, isNewValue = 1, opNewValue = 3, opExtendable = 2 in
-class T_StoreAbsRegNV <string mnemonic, string CextOp, bits<2> MajOp,
- MemAccessSize AccessSz>
- : NVInst <(outs ),
- (ins IntRegs:$src1, u2_0Imm:$src2, u6_0Ext:$src3, IntRegs:$src4),
- mnemonic#"($src1<<#$src2 + #$src3) = $src4.new">, NewValueRel {
- bits<5> src1;
- bits<2> src2;
- bits<6> src3;
- bits<3> src4;
-
- let CextOpcode = CextOp;
- let BaseOpcode = CextOp#"_shl";
- let IClass = 0b1010;
-
- let Inst{27-21} = 0b1101101;
- let Inst{12-11} = 0b00;
- let Inst{7} = 0b1;
- let Inst{20-16} = src1;
- let Inst{13} = src2{1};
- let Inst{12-11} = MajOp;
- let Inst{10-8} = src4;
- let Inst{6} = src2{0};
- let Inst{5-0} = src3;
- }
-
-def S4_storerbnew_ur : T_StoreAbsRegNV <"memb", "STrib", 0b00, ByteAccess>;
-def S4_storerhnew_ur : T_StoreAbsRegNV <"memh", "STrih", 0b01, HalfWordAccess>;
-def S4_storerinew_ur : T_StoreAbsRegNV <"memw", "STriw", 0b10, WordAccess>;
-
-//===----------------------------------------------------------------------===//
-// Template classes for the non-predicated store instructions with
-// base + register offset addressing mode
-//===----------------------------------------------------------------------===//
-let isPredicable = 1 in
-class T_store_rr <string mnemonic, RegisterClass RC, bits<3> MajOp, bit isH>
- : STInst < (outs ), (ins IntRegs:$Rs, IntRegs:$Ru, u2_0Imm:$u2, RC:$Rt),
- mnemonic#"($Rs + $Ru<<#$u2) = $Rt"#!if(isH, ".h",""),
- [],"",V4LDST_tc_st_SLOT01>, ImmRegShl, AddrModeRel {
-
- bits<5> Rs;
- bits<5> Ru;
- bits<2> u2;
- bits<5> Rt;
-
- // Store upper-half and store doubleword cannot be NV.
- let isNVStorable = !if (!eq(mnemonic, "memd"), 0, !if(isH,0,1));
-
- let IClass = 0b0011;
-
- let Inst{27-24} = 0b1011;
- let Inst{23-21} = MajOp;
- let Inst{20-16} = Rs;
- let Inst{12-8} = Ru;
- let Inst{13} = u2{1};
- let Inst{7} = u2{0};
- let Inst{4-0} = Rt;
- }
-
-//===----------------------------------------------------------------------===//
-// Template classes for the predicated store instructions with
-// base + register offset addressing mode
-//===----------------------------------------------------------------------===//
-let isPredicated = 1 in
-class T_pstore_rr <string mnemonic, RegisterClass RC, bits<3> MajOp,
- bit isNot, bit isPredNew, bit isH>
- : STInst <(outs),
- (ins PredRegs:$Pv, IntRegs:$Rs, IntRegs:$Ru, u2_0Imm:$u2, RC:$Rt),
-
- !if(isNot, "if (!$Pv", "if ($Pv")#!if(isPredNew, ".new) ",
- ") ")#mnemonic#"($Rs+$Ru<<#$u2) = $Rt"#!if(isH, ".h",""),
- [], "", V4LDST_tc_st_SLOT01> , AddrModeRel{
- bits<2> Pv;
- bits<5> Rs;
- bits<5> Ru;
- bits<2> u2;
- bits<5> Rt;
-
- let isPredicatedFalse = isNot;
- let isPredicatedNew = isPredNew;
- // Store upper-half and store doubleword cannot be NV.
- let isNVStorable = !if (!eq(mnemonic, "memd"), 0, !if(isH,0,1));
-
- let IClass = 0b0011;
-
- let Inst{27-26} = 0b01;
- let Inst{25} = isPredNew;
- let Inst{24} = isNot;
- let Inst{23-21} = MajOp;
- let Inst{20-16} = Rs;
- let Inst{12-8} = Ru;
- let Inst{13} = u2{1};
- let Inst{7} = u2{0};
- let Inst{6-5} = Pv;
- let Inst{4-0} = Rt;
- }
-
-//===----------------------------------------------------------------------===//
-// Template classes for the new-value store instructions with
-// base + register offset addressing mode
-//===----------------------------------------------------------------------===//
-let isPredicable = 1, isNewValue = 1, opNewValue = 3 in
-class T_store_new_rr <string mnemonic, bits<2> MajOp> :
- NVInst < (outs ), (ins IntRegs:$Rs, IntRegs:$Ru, u2_0Imm:$u2, IntRegs:$Nt),
- mnemonic#"($Rs + $Ru<<#$u2) = $Nt.new",
- [],"",V4LDST_tc_st_SLOT0>, ImmRegShl, AddrModeRel {
-
- bits<5> Rs;
- bits<5> Ru;
- bits<2> u2;
- bits<3> Nt;
-
- let IClass = 0b0011;
-
- let Inst{27-21} = 0b1011101;
- let Inst{20-16} = Rs;
- let Inst{12-8} = Ru;
- let Inst{13} = u2{1};
- let Inst{7} = u2{0};
- let Inst{4-3} = MajOp;
- let Inst{2-0} = Nt;
- }
-
-//===----------------------------------------------------------------------===//
-// Template classes for the predicated new-value store instructions with
-// base + register offset addressing mode
-//===----------------------------------------------------------------------===//
-let isPredicated = 1, isNewValue = 1, opNewValue = 4 in
-class T_pstore_new_rr <string mnemonic, bits<2> MajOp, bit isNot, bit isPredNew>
- : NVInst<(outs),
- (ins PredRegs:$Pv, IntRegs:$Rs, IntRegs:$Ru, u2_0Imm:$u2, IntRegs:$Nt),
- !if(isNot, "if (!$Pv", "if ($Pv")#!if(isPredNew, ".new) ",
- ") ")#mnemonic#"($Rs+$Ru<<#$u2) = $Nt.new",
- [], "", V4LDST_tc_st_SLOT0>, AddrModeRel {
- bits<2> Pv;
- bits<5> Rs;
- bits<5> Ru;
- bits<2> u2;
- bits<3> Nt;
-
- let isPredicatedFalse = isNot;
- let isPredicatedNew = isPredNew;
-
- let IClass = 0b0011;
- let Inst{27-26} = 0b01;
- let Inst{25} = isPredNew;
- let Inst{24} = isNot;
- let Inst{23-21} = 0b101;
- let Inst{20-16} = Rs;
- let Inst{12-8} = Ru;
- let Inst{13} = u2{1};
- let Inst{7} = u2{0};
- let Inst{6-5} = Pv;
- let Inst{4-3} = MajOp;
- let Inst{2-0} = Nt;
- }
-
-//===----------------------------------------------------------------------===//
-// multiclass for store instructions with base + register offset addressing
-// mode
-//===----------------------------------------------------------------------===//
-let isNVStorable = 1 in
-multiclass ST_Idxd_shl<string mnemonic, string CextOp, RegisterClass RC,
- bits<3> MajOp, bit isH = 0> {
- let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
- def S4_#NAME#_rr : T_store_rr <mnemonic, RC, MajOp, isH>;
-
- // Predicated
- def S4_p#NAME#t_rr : T_pstore_rr <mnemonic, RC, MajOp, 0, 0, isH>;
- def S4_p#NAME#f_rr : T_pstore_rr <mnemonic, RC, MajOp, 1, 0, isH>;
-
- // Predicated new
- def S4_p#NAME#tnew_rr : T_pstore_rr <mnemonic, RC, MajOp, 0, 1, isH>;
- def S4_p#NAME#fnew_rr : T_pstore_rr <mnemonic, RC, MajOp, 1, 1, isH>;
- }
-}
-
-//===----------------------------------------------------------------------===//
-// multiclass for new-value store instructions with base + register offset
-// addressing mode.
-//===----------------------------------------------------------------------===//
-let mayStore = 1, isNVStore = 1 in
-multiclass ST_Idxd_shl_nv <string mnemonic, string CextOp, RegisterClass RC,
- bits<2> MajOp> {
- let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
- def S4_#NAME#new_rr : T_store_new_rr<mnemonic, MajOp>;
-
- // Predicated
- def S4_p#NAME#newt_rr : T_pstore_new_rr <mnemonic, MajOp, 0, 0>;
- def S4_p#NAME#newf_rr : T_pstore_new_rr <mnemonic, MajOp, 1, 0>;
-
- // Predicated new
- def S4_p#NAME#newtnew_rr : T_pstore_new_rr <mnemonic, MajOp, 0, 1>;
- def S4_p#NAME#newfnew_rr : T_pstore_new_rr <mnemonic, MajOp, 1, 1>;
- }
-}
-
-let addrMode = BaseRegOffset, InputType = "reg", hasSideEffects = 0 in {
- let accessSize = ByteAccess in
- defm storerb: ST_Idxd_shl<"memb", "STrib", IntRegs, 0b000>,
- ST_Idxd_shl_nv<"memb", "STrib", IntRegs, 0b00>;
-
- let accessSize = HalfWordAccess in
- defm storerh: ST_Idxd_shl<"memh", "STrih", IntRegs, 0b010>,
- ST_Idxd_shl_nv<"memh", "STrih", IntRegs, 0b01>;
-
- let accessSize = WordAccess in
- defm storeri: ST_Idxd_shl<"memw", "STriw", IntRegs, 0b100>,
- ST_Idxd_shl_nv<"memw", "STriw", IntRegs, 0b10>;
-
- let isNVStorable = 0, accessSize = DoubleWordAccess in
- defm storerd: ST_Idxd_shl<"memd", "STrid", DoubleRegs, 0b110>;
-
- let isNVStorable = 0, accessSize = HalfWordAccess in
- defm storerf: ST_Idxd_shl<"memh", "STrif", IntRegs, 0b011, 1>;
-}
-
-//===----------------------------------------------------------------------===//
-// Template class
-//===----------------------------------------------------------------------===//
-let isPredicable = 1, isExtendable = 1, isExtentSigned = 1, opExtentBits = 8,
- opExtendable = 2 in
-class T_StoreImm <string mnemonic, Operand OffsetOp, bits<2> MajOp >
- : STInst <(outs ), (ins IntRegs:$Rs, OffsetOp:$offset, s8_0Ext:$S8),
- mnemonic#"($Rs+#$offset)=#$S8",
- [], "", V4LDST_tc_st_SLOT01>,
- ImmRegRel, PredNewRel {
- bits<5> Rs;
- bits<8> S8;
- bits<8> offset;
- bits<6> offsetBits;
-
- string OffsetOpStr = !cast<string>(OffsetOp);
- let offsetBits = !if (!eq(OffsetOpStr, "u6_2Imm"), offset{7-2},
- !if (!eq(OffsetOpStr, "u6_1Imm"), offset{6-1},
- /* u6_0Imm */ offset{5-0}));
-
- let IClass = 0b0011;
-
- let Inst{27-25} = 0b110;
- let Inst{22-21} = MajOp;
- let Inst{20-16} = Rs;
- let Inst{12-7} = offsetBits;
- let Inst{13} = S8{7};
- let Inst{6-0} = S8{6-0};
- }
-
-let isPredicated = 1, isExtendable = 1, isExtentSigned = 1, opExtentBits = 6,
- opExtendable = 3 in
-class T_StoreImm_pred <string mnemonic, Operand OffsetOp, bits<2> MajOp,
- bit isPredNot, bit isPredNew >
- : STInst <(outs ),
- (ins PredRegs:$Pv, IntRegs:$Rs, OffsetOp:$offset, s6_0Ext:$S6),
- !if(isPredNot, "if (!$Pv", "if ($Pv")#!if(isPredNew, ".new) ",
- ") ")#mnemonic#"($Rs+#$offset)=#$S6",
- [], "", V4LDST_tc_st_SLOT01>,
- ImmRegRel, PredNewRel {
- bits<2> Pv;
- bits<5> Rs;
- bits<6> S6;
- bits<8> offset;
- bits<6> offsetBits;
-
- string OffsetOpStr = !cast<string>(OffsetOp);
- let offsetBits = !if (!eq(OffsetOpStr, "u6_2Imm"), offset{7-2},
- !if (!eq(OffsetOpStr, "u6_1Imm"), offset{6-1},
- /* u6_0Imm */ offset{5-0}));
- let isPredicatedNew = isPredNew;
- let isPredicatedFalse = isPredNot;
-
- let IClass = 0b0011;
-
- let Inst{27-25} = 0b100;
- let Inst{24} = isPredNew;
- let Inst{23} = isPredNot;
- let Inst{22-21} = MajOp;
- let Inst{20-16} = Rs;
- let Inst{13} = S6{5};
- let Inst{12-7} = offsetBits;
- let Inst{6-5} = Pv;
- let Inst{4-0} = S6{4-0};
- }
-
-
-//===----------------------------------------------------------------------===//
-// multiclass for store instructions with base + immediate offset
-// addressing mode and immediate stored value.
-// mem[bhw](Rx++#s4:3)=#s8
-// if ([!]Pv[.new]) mem[bhw](Rx++#s4:3)=#s6
-//===----------------------------------------------------------------------===//
-
-multiclass ST_Imm_Pred <string mnemonic, Operand OffsetOp, bits<2> MajOp,
- bit PredNot> {
- def _io : T_StoreImm_pred <mnemonic, OffsetOp, MajOp, PredNot, 0>;
- // Predicate new
- def new_io : T_StoreImm_pred <mnemonic, OffsetOp, MajOp, PredNot, 1>;
-}
-
-multiclass ST_Imm <string mnemonic, string CextOp, Operand OffsetOp,
- bits<2> MajOp> {
- let CextOpcode = CextOp, BaseOpcode = CextOp#_imm in {
- def _io : T_StoreImm <mnemonic, OffsetOp, MajOp>;
-
- defm t : ST_Imm_Pred <mnemonic, OffsetOp, MajOp, 0>;
- defm f : ST_Imm_Pred <mnemonic, OffsetOp, MajOp, 1>;
- }
-}
-
-let hasSideEffects = 0, addrMode = BaseImmOffset,
- InputType = "imm" in {
- let accessSize = ByteAccess in
- defm S4_storeirb : ST_Imm<"memb", "STrib", u6_0Imm, 0b00>;
-
- let accessSize = HalfWordAccess in
- defm S4_storeirh : ST_Imm<"memh", "STrih", u6_1Imm, 0b01>;
-
- let accessSize = WordAccess in
- defm S4_storeiri : ST_Imm<"memw", "STriw", u6_2Imm, 0b10>;
-}
-
-//===----------------------------------------------------------------------===
-// ST -
-//===----------------------------------------------------------------------===
-
-
-//===----------------------------------------------------------------------===//
-// NV/ST +
-//===----------------------------------------------------------------------===//
-
-let opNewValue = 2, opExtendable = 1, isExtentSigned = 1, isPredicable = 1 in
-class T_store_io_nv <string mnemonic, RegisterClass RC,
- Operand ImmOp, bits<2>MajOp>
- : NVInst_V4 <(outs),
- (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
- mnemonic#"($src1+#$src2) = $src3.new",
- [],"",ST_tc_st_SLOT0> {
- bits<5> src1;
- bits<13> src2; // Actual address offset
- bits<3> src3;
- bits<11> offsetBits; // Represents offset encoding
-
- let opExtentBits = !if (!eq(mnemonic, "memb"), 11,
- !if (!eq(mnemonic, "memh"), 12,
- !if (!eq(mnemonic, "memw"), 13, 0)));
-
- let opExtentAlign = !if (!eq(mnemonic, "memb"), 0,
- !if (!eq(mnemonic, "memh"), 1,
- !if (!eq(mnemonic, "memw"), 2, 0)));
-
- let offsetBits = !if (!eq(mnemonic, "memb"), src2{10-0},
- !if (!eq(mnemonic, "memh"), src2{11-1},
- !if (!eq(mnemonic, "memw"), src2{12-2}, 0)));
-
- let IClass = 0b1010;
-
- let Inst{27} = 0b0;
- let Inst{26-25} = offsetBits{10-9};
- let Inst{24-21} = 0b1101;
- let Inst{20-16} = src1;
- let Inst{13} = offsetBits{8};
- let Inst{12-11} = MajOp;
- let Inst{10-8} = src3;
- let Inst{7-0} = offsetBits{7-0};
- }
-
-let opExtendable = 2, opNewValue = 3, isPredicated = 1 in
-class T_pstore_io_nv <string mnemonic, RegisterClass RC, Operand predImmOp,
- bits<2>MajOp, bit PredNot, bit isPredNew>
- : NVInst_V4 <(outs),
- (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC:$src4),
- !if(PredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
- ") ")#mnemonic#"($src2+#$src3) = $src4.new",
- [],"",V2LDST_tc_st_SLOT0> {
- bits<2> src1;
- bits<5> src2;
- bits<9> src3;
- bits<3> src4;
- bits<6> offsetBits; // Represents offset encoding
-
- let isPredicatedNew = isPredNew;
- let isPredicatedFalse = PredNot;
- let opExtentBits = !if (!eq(mnemonic, "memb"), 6,
- !if (!eq(mnemonic, "memh"), 7,
- !if (!eq(mnemonic, "memw"), 8, 0)));
-
- let opExtentAlign = !if (!eq(mnemonic, "memb"), 0,
- !if (!eq(mnemonic, "memh"), 1,
- !if (!eq(mnemonic, "memw"), 2, 0)));
-
- let offsetBits = !if (!eq(mnemonic, "memb"), src3{5-0},
- !if (!eq(mnemonic, "memh"), src3{6-1},
- !if (!eq(mnemonic, "memw"), src3{7-2}, 0)));
-
- let IClass = 0b0100;
-
- let Inst{27} = 0b0;
- let Inst{26} = PredNot;
- let Inst{25} = isPredNew;
- let Inst{24-21} = 0b0101;
- let Inst{20-16} = src2;
- let Inst{13} = offsetBits{5};
- let Inst{12-11} = MajOp;
- let Inst{10-8} = src4;
- let Inst{7-3} = offsetBits{4-0};
- let Inst{2} = 0b0;
- let Inst{1-0} = src1;
- }
-
-// multiclass for new-value store instructions with base + immediate offset.
-//
-let mayStore = 1, isNVStore = 1, isNewValue = 1, hasSideEffects = 0,
- isExtendable = 1 in
-multiclass ST_Idxd_nv<string mnemonic, string CextOp, RegisterClass RC,
- Operand ImmOp, Operand predImmOp, bits<2> MajOp> {
-
- let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
- def S2_#NAME#new_io : T_store_io_nv <mnemonic, RC, ImmOp, MajOp>;
- // Predicated
- def S2_p#NAME#newt_io :T_pstore_io_nv <mnemonic, RC, predImmOp, MajOp, 0, 0>;
- def S2_p#NAME#newf_io :T_pstore_io_nv <mnemonic, RC, predImmOp, MajOp, 1, 0>;
- // Predicated new
- def S4_p#NAME#newtnew_io :T_pstore_io_nv <mnemonic, RC, predImmOp,
- MajOp, 0, 1>;
- def S4_p#NAME#newfnew_io :T_pstore_io_nv <mnemonic, RC, predImmOp,
- MajOp, 1, 1>;
- }
-}
-
-let addrMode = BaseImmOffset, InputType = "imm" in {
- let accessSize = ByteAccess in
- defm storerb: ST_Idxd_nv<"memb", "STrib", IntRegs, s11_0Ext,
- u6_0Ext, 0b00>, AddrModeRel;
-
- let accessSize = HalfWordAccess, opExtentAlign = 1 in
- defm storerh: ST_Idxd_nv<"memh", "STrih", IntRegs, s11_1Ext,
- u6_1Ext, 0b01>, AddrModeRel;
-
- let accessSize = WordAccess, opExtentAlign = 2 in
- defm storeri: ST_Idxd_nv<"memw", "STriw", IntRegs, s11_2Ext,
- u6_2Ext, 0b10>, AddrModeRel;
-}
-
-//===----------------------------------------------------------------------===//
-// Post increment loads with register offset.
-//===----------------------------------------------------------------------===//
-
-let hasNewValue = 1 in
-def L2_loadbsw2_pr : T_load_pr <"membh", IntRegs, 0b0001, HalfWordAccess>;
-
-def L2_loadbsw4_pr : T_load_pr <"membh", DoubleRegs, 0b0111, WordAccess>;
-
-let hasSideEffects = 0, addrMode = PostInc in
-class T_loadalign_pr <string mnemonic, bits<4> MajOp, MemAccessSize AccessSz>
- : LDInstPI <(outs DoubleRegs:$dst, IntRegs:$_dst_),
- (ins DoubleRegs:$src1, IntRegs:$src2, ModRegs:$src3),
- "$dst = "#mnemonic#"($src2++$src3)", [],
- "$src1 = $dst, $src2 = $_dst_"> {
- bits<5> dst;
- bits<5> src2;
- bits<1> src3;
-
- let accessSize = AccessSz;
- let IClass = 0b1001;
-
- let Inst{27-25} = 0b110;
- let Inst{24-21} = MajOp;
- let Inst{20-16} = src2;
- let Inst{13} = src3;
- let Inst{12} = 0b0;
- let Inst{7} = 0b0;
- let Inst{4-0} = dst;
- }
-
-def L2_loadalignb_pr : T_loadalign_pr <"memb_fifo", 0b0100, ByteAccess>;
-def L2_loadalignh_pr : T_loadalign_pr <"memh_fifo", 0b0010, HalfWordAccess>;
-
-//===----------------------------------------------------------------------===//
-// Template class for non-predicated post increment .new stores
-// mem[bhwd](Rx++#s4:[0123])=Nt.new
-//===----------------------------------------------------------------------===//
-let isPredicable = 1, hasSideEffects = 0, addrMode = PostInc, isNVStore = 1,
- isNewValue = 1, opNewValue = 3 in
-class T_StorePI_nv <string mnemonic, Operand ImmOp, bits<2> MajOp >
- : NVInstPI_V4 <(outs IntRegs:$_dst_),
- (ins IntRegs:$src1, ImmOp:$offset, IntRegs:$src2),
- mnemonic#"($src1++#$offset) = $src2.new",
- [], "$src1 = $_dst_">,
- AddrModeRel {
- bits<5> src1;
- bits<3> src2;
- bits<7> offset;
- bits<4> offsetBits;
-
- string ImmOpStr = !cast<string>(ImmOp);
- let offsetBits = !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
- !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
- /* s4_0Imm */ offset{3-0}));
- let IClass = 0b1010;
-
- let Inst{27-21} = 0b1011101;
- let Inst{20-16} = src1;
- let Inst{13} = 0b0;
- let Inst{12-11} = MajOp;
- let Inst{10-8} = src2;
- let Inst{7} = 0b0;
- let Inst{6-3} = offsetBits;
- let Inst{1} = 0b0;
- }
-
-//===----------------------------------------------------------------------===//
-// Template class for predicated post increment .new stores
-// if([!]Pv[.new]) mem[bhwd](Rx++#s4:[0123])=Nt.new
-//===----------------------------------------------------------------------===//
-let isPredicated = 1, hasSideEffects = 0, addrMode = PostInc, isNVStore = 1,
- isNewValue = 1, opNewValue = 4 in
-class T_StorePI_nv_pred <string mnemonic, Operand ImmOp,
- bits<2> MajOp, bit isPredNot, bit isPredNew >
- : NVInstPI_V4 <(outs IntRegs:$_dst_),
- (ins PredRegs:$src1, IntRegs:$src2,
- ImmOp:$offset, IntRegs:$src3),
- !if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
- ") ")#mnemonic#"($src2++#$offset) = $src3.new",
- [], "$src2 = $_dst_">,
- AddrModeRel {
- bits<2> src1;
- bits<5> src2;
- bits<3> src3;
- bits<7> offset;
- bits<4> offsetBits;
-
- string ImmOpStr = !cast<string>(ImmOp);
- let offsetBits = !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
- !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
- /* s4_0Imm */ offset{3-0}));
- let isPredicatedNew = isPredNew;
- let isPredicatedFalse = isPredNot;
-
- let IClass = 0b1010;
-
- let Inst{27-21} = 0b1011101;
- let Inst{20-16} = src2;
- let Inst{13} = 0b1;
- let Inst{12-11} = MajOp;
- let Inst{10-8} = src3;
- let Inst{7} = isPredNew;
- let Inst{6-3} = offsetBits;
- let Inst{2} = isPredNot;
- let Inst{1-0} = src1;
- }
-
-multiclass ST_PostInc_Pred_nv<string mnemonic, Operand ImmOp,
- bits<2> MajOp, bit PredNot> {
- def _pi : T_StorePI_nv_pred <mnemonic, ImmOp, MajOp, PredNot, 0>;
-
- // Predicate new
- def new_pi : T_StorePI_nv_pred <mnemonic, ImmOp, MajOp, PredNot, 1>;
-}
-
-multiclass ST_PostInc_nv<string mnemonic, string BaseOp, Operand ImmOp,
- bits<2> MajOp> {
- let BaseOpcode = "POST_"#BaseOp in {
- def S2_#NAME#_pi : T_StorePI_nv <mnemonic, ImmOp, MajOp>;
-
- // Predicated
- defm S2_p#NAME#t : ST_PostInc_Pred_nv <mnemonic, ImmOp, MajOp, 0>;
- defm S2_p#NAME#f : ST_PostInc_Pred_nv <mnemonic, ImmOp, MajOp, 1>;
- }
-}
-
-let accessSize = ByteAccess in
-defm storerbnew: ST_PostInc_nv <"memb", "STrib", s4_0Imm, 0b00>;
-
-let accessSize = HalfWordAccess in
-defm storerhnew: ST_PostInc_nv <"memh", "STrih", s4_1Imm, 0b01>;
-
-let accessSize = WordAccess in
-defm storerinew: ST_PostInc_nv <"memw", "STriw", s4_2Imm, 0b10>;
-
-//===----------------------------------------------------------------------===//
-// Template class for post increment .new stores with register offset
-//===----------------------------------------------------------------------===//
-let isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 3 in
-class T_StorePI_RegNV <string mnemonic, bits<2> MajOp, MemAccessSize AccessSz>
- : NVInstPI_V4 <(outs IntRegs:$_dst_),
- (ins IntRegs:$src1, ModRegs:$src2, IntRegs:$src3),
- #mnemonic#"($src1++$src2) = $src3.new",
- [], "$src1 = $_dst_"> {
- bits<5> src1;
- bits<1> src2;
- bits<3> src3;
- let accessSize = AccessSz;
-
- let IClass = 0b1010;
-
- let Inst{27-21} = 0b1101101;
- let Inst{20-16} = src1;
- let Inst{13} = src2;
- let Inst{12-11} = MajOp;
- let Inst{10-8} = src3;
- let Inst{7} = 0b0;
- }
-
-def S2_storerbnew_pr : T_StorePI_RegNV<"memb", 0b00, ByteAccess>;
-def S2_storerhnew_pr : T_StorePI_RegNV<"memh", 0b01, HalfWordAccess>;
-def S2_storerinew_pr : T_StorePI_RegNV<"memw", 0b10, WordAccess>;
-
-// memb(Rx++#s4:0:circ(Mu))=Nt.new
-// memb(Rx++I:circ(Mu))=Nt.new
-// memb(Rx++Mu:brev)=Nt.new
-// memh(Rx++#s4:1:circ(Mu))=Nt.new
-// memh(Rx++I:circ(Mu))=Nt.new
-// memh(Rx++Mu)=Nt.new
-// memh(Rx++Mu:brev)=Nt.new
-
-// memw(Rx++#s4:2:circ(Mu))=Nt.new
-// memw(Rx++I:circ(Mu))=Nt.new
-// memw(Rx++Mu)=Nt.new
-// memw(Rx++Mu:brev)=Nt.new
-
-//===----------------------------------------------------------------------===//
-// NV/ST -
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// NV/J +
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// multiclass/template class for the new-value compare jumps with the register
-// operands.
-//===----------------------------------------------------------------------===//
-
-let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 11,
- opExtentAlign = 2 in
-class NVJrr_template<string mnemonic, bits<3> majOp, bit NvOpNum,
- bit isNegCond, bit isTak>
- : NVInst_V4<(outs),
- (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
- "if ("#!if(isNegCond, "!","")#mnemonic#
- "($src1"#!if(!eq(NvOpNum, 0),".new, ",", ")#
- "$src2"#!if(!eq(NvOpNum, 1),".new))","))")#" jump:"
- #!if(isTak, "t","nt")#" $offset", []> {
-
- bits<5> src1;
- bits<5> src2;
- bits<3> Ns; // New-Value Operand
- bits<5> RegOp; // Non-New-Value Operand
- bits<11> offset;
-
- let isTaken = isTak;
- let isPredicatedFalse = isNegCond;
- let opNewValue{0} = NvOpNum;
-
- let Ns = !if(!eq(NvOpNum, 0), src1{2-0}, src2{2-0});
- let RegOp = !if(!eq(NvOpNum, 0), src2, src1);
-
- let IClass = 0b0010;
- let Inst{27-26} = 0b00;
- let Inst{25-23} = majOp;
- let Inst{22} = isNegCond;
- let Inst{18-16} = Ns;
- let Inst{13} = isTak;
- let Inst{12-8} = RegOp;
- let Inst{21-20} = offset{10-9};
- let Inst{7-1} = offset{8-2};
-}
-
-
-multiclass NVJrr_cond<string mnemonic, bits<3> majOp, bit NvOpNum,
- bit isNegCond> {
- // Branch not taken:
- def _nt: NVJrr_template<mnemonic, majOp, NvOpNum, isNegCond, 0>;
- // Branch taken:
- def _t : NVJrr_template<mnemonic, majOp, NvOpNum, isNegCond, 1>;
-}
-
-// NvOpNum = 0 -> First Operand is a new-value Register
-// NvOpNum = 1 -> Second Operand is a new-value Register
-
-multiclass NVJrr_base<string mnemonic, string BaseOp, bits<3> majOp,
- bit NvOpNum> {
- let BaseOpcode = BaseOp#_NVJ in {
- defm _t_jumpnv : NVJrr_cond<mnemonic, majOp, NvOpNum, 0>; // True cond
- defm _f_jumpnv : NVJrr_cond<mnemonic, majOp, NvOpNum, 1>; // False cond
- }
-}
-
-// if ([!]cmp.eq(Ns.new,Rt)) jump:[n]t #r9:2
-// if ([!]cmp.gt(Ns.new,Rt)) jump:[n]t #r9:2
-// if ([!]cmp.gtu(Ns.new,Rt)) jump:[n]t #r9:2
-// if ([!]cmp.gt(Rt,Ns.new)) jump:[n]t #r9:2
-// if ([!]cmp.gtu(Rt,Ns.new)) jump:[n]t #r9:2
-
-let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1,
- Defs = [PC], hasSideEffects = 0 in {
- defm J4_cmpeq : NVJrr_base<"cmp.eq", "CMPEQ", 0b000, 0>, PredRel;
- defm J4_cmpgt : NVJrr_base<"cmp.gt", "CMPGT", 0b001, 0>, PredRel;
- defm J4_cmpgtu : NVJrr_base<"cmp.gtu", "CMPGTU", 0b010, 0>, PredRel;
- defm J4_cmplt : NVJrr_base<"cmp.gt", "CMPLT", 0b011, 1>, PredRel;
- defm J4_cmpltu : NVJrr_base<"cmp.gtu", "CMPLTU", 0b100, 1>, PredRel;
-}
-
-//===----------------------------------------------------------------------===//
-// multiclass/template class for the new-value compare jumps instruction
-// with a register and an unsigned immediate (U5) operand.
-//===----------------------------------------------------------------------===//
-
-let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 11,
- opExtentAlign = 2 in
-class NVJri_template<string mnemonic, bits<3> majOp, bit isNegCond,
- bit isTak>
- : NVInst_V4<(outs),
- (ins IntRegs:$src1, u5_0Imm:$src2, brtarget:$offset),
- "if ("#!if(isNegCond, "!","")#mnemonic#"($src1.new, #$src2)) jump:"
- #!if(isTak, "t","nt")#" $offset", []> {
-
- let isTaken = isTak;
- let isPredicatedFalse = isNegCond;
- let isTaken = isTak;
-
- bits<3> src1;
- bits<5> src2;
- bits<11> offset;
-
- let IClass = 0b0010;
- let Inst{26} = 0b1;
- let Inst{25-23} = majOp;
- let Inst{22} = isNegCond;
- let Inst{18-16} = src1;
- let Inst{13} = isTak;
- let Inst{12-8} = src2;
- let Inst{21-20} = offset{10-9};
- let Inst{7-1} = offset{8-2};
-}
-
-multiclass NVJri_cond<string mnemonic, bits<3> majOp, bit isNegCond> {
- // Branch not taken:
- def _nt: NVJri_template<mnemonic, majOp, isNegCond, 0>;
- // Branch taken:
- def _t : NVJri_template<mnemonic, majOp, isNegCond, 1>;
-}
-
-multiclass NVJri_base<string mnemonic, string BaseOp, bits<3> majOp> {
- let BaseOpcode = BaseOp#_NVJri in {
- defm _t_jumpnv : NVJri_cond<mnemonic, majOp, 0>; // True Cond
- defm _f_jumpnv : NVJri_cond<mnemonic, majOp, 1>; // False cond
- }
-}
-
-// if ([!]cmp.eq(Ns.new,#U5)) jump:[n]t #r9:2
-// if ([!]cmp.gt(Ns.new,#U5)) jump:[n]t #r9:2
-// if ([!]cmp.gtu(Ns.new,#U5)) jump:[n]t #r9:2
-
-let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1,
- Defs = [PC], hasSideEffects = 0 in {
- defm J4_cmpeqi : NVJri_base<"cmp.eq", "CMPEQ", 0b000>, PredRel;
- defm J4_cmpgti : NVJri_base<"cmp.gt", "CMPGT", 0b001>, PredRel;
- defm J4_cmpgtui : NVJri_base<"cmp.gtu", "CMPGTU", 0b010>, PredRel;
-}
-
-//===----------------------------------------------------------------------===//
-// multiclass/template class for the new-value compare jumps instruction
-// with a register and an hardcoded 0/-1 immediate value.
-//===----------------------------------------------------------------------===//
-
-let isExtendable = 1, isExtentSigned = 1, opExtentBits = 11,
- opExtentAlign = 2 in
-class NVJ_ConstImm_template<string mnemonic, bits<3> majOp, string ImmVal,
- bit isNegCond, bit isTak>
- : NVInst_V4<(outs),
- !if(!eq(ImmVal, "{-1}"),
- (ins IntRegs:$src1, n1Const:$n1, brtarget:$offset),
- (ins IntRegs:$src1, brtarget:$offset)),
- "if ("#!if(isNegCond, "!","")#mnemonic
- #"($src1.new, #" # !if(!eq(ImmVal, "{-1}"), "$n1", ImmVal) # ")) jump:"
- #!if(isTak, "t","nt")#" $offset", []> {
-
- let isTaken = isTak;
- let isPredicatedFalse = isNegCond;
- let isTaken = isTak;
- let opExtendable = !if(!eq(ImmVal, "{-1}"), 2, 1);
-
- bits<3> src1;
- bits<11> offset;
- let IClass = 0b0010;
- let Inst{26} = 0b1;
- let Inst{25-23} = majOp;
- let Inst{22} = isNegCond;
- let Inst{18-16} = src1;
- let Inst{13} = isTak;
- let Inst{21-20} = offset{10-9};
- let Inst{7-1} = offset{8-2};
-}
-
-multiclass NVJ_ConstImm_cond<string mnemonic, bits<3> majOp, string ImmVal,
- bit isNegCond> {
- // Branch not taken:
- def _nt: NVJ_ConstImm_template<mnemonic, majOp, ImmVal, isNegCond, 0>;
- // Branch taken:
- def _t : NVJ_ConstImm_template<mnemonic, majOp, ImmVal, isNegCond, 1>;
-}
-
-multiclass NVJ_ConstImm_base<string mnemonic, string BaseOp, bits<3> majOp,
- string ImmVal> {
- let BaseOpcode = BaseOp#_NVJ_ConstImm in {
- defm _t_jumpnv : NVJ_ConstImm_cond<mnemonic, majOp, ImmVal, 0>; // True
- defm _f_jumpnv : NVJ_ConstImm_cond<mnemonic, majOp, ImmVal, 1>; // False
- }
-}
-
-// if ([!]tstbit(Ns.new,#0)) jump:[n]t #r9:2
-// if ([!]cmp.eq(Ns.new,#-1)) jump:[n]t #r9:2
-// if ([!]cmp.gt(Ns.new,#-1)) jump:[n]t #r9:2
-
-let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator=1,
- Defs = [PC], hasSideEffects = 0 in {
- defm J4_tstbit0 : NVJ_ConstImm_base<"tstbit", "TSTBIT", 0b011, "0">, PredRel;
- defm J4_cmpeqn1 : NVJ_ConstImm_base<"cmp.eq", "CMPEQ", 0b100, "{-1}">, PredRel;
- defm J4_cmpgtn1 : NVJ_ConstImm_base<"cmp.gt", "CMPGT", 0b101, "{-1}">, PredRel;
-}
-
-// J4_hintjumpr: Hint indirect conditional jump.
-let isBranch = 1, isIndirectBranch = 1, hasSideEffects = 0 in
-def J4_hintjumpr: JRInst <
- (outs),
- (ins IntRegs:$Rs),
- "hintjr($Rs)"> {
- bits<5> Rs;
- let IClass = 0b0101;
- let Inst{27-21} = 0b0010101;
- let Inst{20-16} = Rs;
- }
-
-//===----------------------------------------------------------------------===//
-// NV/J -
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// CR +
-//===----------------------------------------------------------------------===//
-
-// PC-relative add
-let hasNewValue = 1, isExtendable = 1, opExtendable = 1,
- isExtentSigned = 0, opExtentBits = 6, hasSideEffects = 0, Uses = [PC] in
-def C4_addipc : CRInst <(outs IntRegs:$Rd), (ins u6_0Ext:$u6),
- "$Rd = add(pc, #$u6)", [], "", CR_tc_2_SLOT3 > {
- bits<5> Rd;
- bits<6> u6;
-
- let IClass = 0b0110;
- let Inst{27-16} = 0b101001001001;
- let Inst{12-7} = u6;
- let Inst{4-0} = Rd;
- }
-
-
-
-let hasSideEffects = 0 in
-class T_LOGICAL_3OP<string MnOp1, string MnOp2, bits<2> OpBits, bit IsNeg>
- : CRInst<(outs PredRegs:$Pd),
- (ins PredRegs:$Ps, PredRegs:$Pt, PredRegs:$Pu),
- "$Pd = " # MnOp1 # "($Ps, " # MnOp2 # "($Pt, " #
- !if (IsNeg,"!","") # "$Pu))",
- [], "", CR_tc_2early_SLOT23> {
- bits<2> Pd;
- bits<2> Ps;
- bits<2> Pt;
- bits<2> Pu;
-
- let IClass = 0b0110;
- let Inst{27-24} = 0b1011;
- let Inst{23} = IsNeg;
- let Inst{22-21} = OpBits;
- let Inst{20} = 0b1;
- let Inst{17-16} = Ps;
- let Inst{13} = 0b0;
- let Inst{9-8} = Pt;
- let Inst{7-6} = Pu;
- let Inst{1-0} = Pd;
-}
-
-def C4_and_and : T_LOGICAL_3OP<"and", "and", 0b00, 0>;
-def C4_and_or : T_LOGICAL_3OP<"and", "or", 0b01, 0>;
-def C4_or_and : T_LOGICAL_3OP<"or", "and", 0b10, 0>;
-def C4_or_or : T_LOGICAL_3OP<"or", "or", 0b11, 0>;
-def C4_and_andn : T_LOGICAL_3OP<"and", "and", 0b00, 1>;
-def C4_and_orn : T_LOGICAL_3OP<"and", "or", 0b01, 1>;
-def C4_or_andn : T_LOGICAL_3OP<"or", "and", 0b10, 1>;
-def C4_or_orn : T_LOGICAL_3OP<"or", "or", 0b11, 1>;
-
-//===----------------------------------------------------------------------===//
-// CR -
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// XTYPE/ALU +
-//===----------------------------------------------------------------------===//
-
-// Logical with-not instructions.
-def A4_andnp : T_ALU64_logical<"and", 0b001, 1, 0, 1>;
-def A4_ornp : T_ALU64_logical<"or", 0b011, 1, 0, 1>;
-
-let hasNewValue = 1, hasSideEffects = 0 in
-def S4_parity: ALU64Inst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
- "$Rd = parity($Rs, $Rt)", [], "", ALU64_tc_2_SLOT23> {
- bits<5> Rd;
- bits<5> Rs;
- bits<5> Rt;
-
- let IClass = 0b1101;
- let Inst{27-21} = 0b0101111;
- let Inst{20-16} = Rs;
- let Inst{12-8} = Rt;
- let Inst{4-0} = Rd;
-}
-
-// Add and accumulate.
-// Rd=add(Rs,add(Ru,#s6))
-let isExtentSigned = 1, hasNewValue = 1, isExtendable = 1, opExtentBits = 6,
- opExtendable = 3 in
-def S4_addaddi : ALU64Inst <(outs IntRegs:$Rd),
- (ins IntRegs:$Rs, IntRegs:$Ru, s6_0Ext:$s6),
- "$Rd = add($Rs, add($Ru, #$s6))" , [],
- "", ALU64_tc_2_SLOT23> {
- bits<5> Rd;
- bits<5> Rs;
- bits<5> Ru;
- bits<6> s6;
-
- let IClass = 0b1101;
-
- let Inst{27-23} = 0b10110;
- let Inst{22-21} = s6{5-4};
- let Inst{20-16} = Rs;
- let Inst{13} = s6{3};
- let Inst{12-8} = Rd;
- let Inst{7-5} = s6{2-0};
- let Inst{4-0} = Ru;
- }
-
-let isExtentSigned = 1, hasSideEffects = 0, hasNewValue = 1, isExtendable = 1,
- opExtentBits = 6, opExtendable = 2 in
-def S4_subaddi: ALU64Inst <(outs IntRegs:$Rd),
- (ins IntRegs:$Rs, s6_0Ext:$s6, IntRegs:$Ru),
- "$Rd = add($Rs, sub(#$s6, $Ru))",
- [], "", ALU64_tc_2_SLOT23> {
- bits<5> Rd;
- bits<5> Rs;
- bits<6> s6;
- bits<5> Ru;
-
- let IClass = 0b1101;
-
- let Inst{27-23} = 0b10111;
- let Inst{22-21} = s6{5-4};
- let Inst{20-16} = Rs;
- let Inst{13} = s6{3};
- let Inst{12-8} = Rd;
- let Inst{7-5} = s6{2-0};
- let Inst{4-0} = Ru;
- }
-
-def S4_extractp_rp : T_S3op_64 < "extract", 0b11, 0b100, 0>;
-def S4_extractp : T_S2op_extract <"extract", 0b1010, DoubleRegs, u6_0Imm>;
-
-let hasNewValue = 1 in {
- def S4_extract_rp : T_S3op_extract<"extract", 0b01>;
- def S4_extract : T_S2op_extract <"extract", 0b1101, IntRegs, u5_0Imm>;
-}
-
-// Complex add/sub halfwords/words
-let Defs = [USR_OVF] in {
- def S4_vxaddsubh : T_S3op_64 < "vxaddsubh", 0b01, 0b100, 0, 1>;
- def S4_vxaddsubw : T_S3op_64 < "vxaddsubw", 0b01, 0b000, 0, 1>;
- def S4_vxsubaddh : T_S3op_64 < "vxsubaddh", 0b01, 0b110, 0, 1>;
- def S4_vxsubaddw : T_S3op_64 < "vxsubaddw", 0b01, 0b010, 0, 1>;
-}
-
-let Defs = [USR_OVF] in {
- def S4_vxaddsubhr : T_S3op_64 < "vxaddsubh", 0b11, 0b000, 0, 1, 1, 1>;
- def S4_vxsubaddhr : T_S3op_64 < "vxsubaddh", 0b11, 0b010, 0, 1, 1, 1>;
-}
-
-let Itinerary = M_tc_3x_SLOT23, Defs = [USR_OVF] in {
- def M4_mac_up_s1_sat: T_MType_acc_rr<"+= mpy", 0b011, 0b000, 0, [], 0, 1, 1>;
- def M4_nac_up_s1_sat: T_MType_acc_rr<"-= mpy", 0b011, 0b001, 0, [], 0, 1, 1>;
-}
-
-// Logical xor with xor accumulation.
-// Rxx^=xor(Rss,Rtt)
-let hasSideEffects = 0 in
-def M4_xor_xacc
- : SInst <(outs DoubleRegs:$Rxx),
- (ins DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt),
- "$Rxx ^= xor($Rss, $Rtt)", [],
- "$dst2 = $Rxx", S_3op_tc_1_SLOT23> {
- bits<5> Rxx;
- bits<5> Rss;
- bits<5> Rtt;
-
- let IClass = 0b1100;
-
- let Inst{27-22} = 0b101010;
- let Inst{20-16} = Rss;
- let Inst{12-8} = Rtt;
- let Inst{7-5} = 0b000;
- let Inst{4-0} = Rxx;
- }
-
-// Rotate and reduce bytes
-// Rdd=vrcrotate(Rss,Rt,#u2)
-let hasSideEffects = 0 in
-def S4_vrcrotate
- : SInst <(outs DoubleRegs:$Rdd),
- (ins DoubleRegs:$Rss, IntRegs:$Rt, u2_0Imm:$u2),
- "$Rdd = vrcrotate($Rss, $Rt, #$u2)",
- [], "", S_3op_tc_3x_SLOT23> {
- bits<5> Rdd;
- bits<5> Rss;
- bits<5> Rt;
- bits<2> u2;
-
- let IClass = 0b1100;
-
- let Inst{27-22} = 0b001111;
- let Inst{20-16} = Rss;
- let Inst{13} = u2{1};
- let Inst{12-8} = Rt;
- let Inst{7-6} = 0b11;
- let Inst{5} = u2{0};
- let Inst{4-0} = Rdd;
- }
-
-// Rotate and reduce bytes with accumulation
-// Rxx+=vrcrotate(Rss,Rt,#u2)
-let hasSideEffects = 0 in
-def S4_vrcrotate_acc
- : SInst <(outs DoubleRegs:$Rxx),
- (ins DoubleRegs:$dst2, DoubleRegs:$Rss, IntRegs:$Rt, u2_0Imm:$u2),
- "$Rxx += vrcrotate($Rss, $Rt, #$u2)", [],
- "$dst2 = $Rxx", S_3op_tc_3x_SLOT23> {
- bits<5> Rxx;
- bits<5> Rss;
- bits<5> Rt;
- bits<2> u2;
-
- let IClass = 0b1100;
-
- let Inst{27-21} = 0b1011101;
- let Inst{20-16} = Rss;
- let Inst{13} = u2{1};
- let Inst{12-8} = Rt;
- let Inst{5} = u2{0};
- let Inst{4-0} = Rxx;
- }
-
-// Vector reduce conditional negate halfwords
-let hasSideEffects = 0 in
-def S2_vrcnegh
- : SInst <(outs DoubleRegs:$Rxx),
- (ins DoubleRegs:$dst2, DoubleRegs:$Rss, IntRegs:$Rt),
- "$Rxx += vrcnegh($Rss, $Rt)", [],
- "$dst2 = $Rxx", S_3op_tc_3x_SLOT23> {
- bits<5> Rxx;
- bits<5> Rss;
- bits<5> Rt;
-
- let IClass = 0b1100;
-
- let Inst{27-21} = 0b1011001;
- let Inst{20-16} = Rss;
- let Inst{13} = 0b1;
- let Inst{12-8} = Rt;
- let Inst{7-5} = 0b111;
- let Inst{4-0} = Rxx;
- }
-
-// Split bitfield
-def A4_bitspliti : T_S2op_2_di <"bitsplit", 0b110, 0b100>;
-
-// Arithmetic/Convergent round
-def A4_cround_ri : T_S2op_2_ii <"cround", 0b111, 0b000>;
-
-def A4_round_ri : T_S2op_2_ii <"round", 0b111, 0b100>;
-
-let Defs = [USR_OVF] in
-def A4_round_ri_sat : T_S2op_2_ii <"round", 0b111, 0b110, 1>;
-
-// Logical-logical words.
-// Compound or-and -- Rx=or(Ru,and(Rx,#s10))
-let isExtentSigned = 1, hasNewValue = 1, isExtendable = 1, opExtentBits = 10,
- opExtendable = 3 in
-def S4_or_andix:
- ALU64Inst<(outs IntRegs:$Rx),
- (ins IntRegs:$Ru, IntRegs:$_src_, s10_0Ext:$s10),
- "$Rx = or($Ru, and($_src_, #$s10))" , [] ,
- "$_src_ = $Rx", ALU64_tc_2_SLOT23> {
- bits<5> Rx;
- bits<5> Ru;
- bits<10> s10;
-
- let IClass = 0b1101;
-
- let Inst{27-22} = 0b101001;
- let Inst{20-16} = Rx;
- let Inst{21} = s10{9};
- let Inst{13-5} = s10{8-0};
- let Inst{4-0} = Ru;
- }
-
-// Miscellaneous ALU64 instructions.
-//
-let hasNewValue = 1, hasSideEffects = 0 in
-def A4_modwrapu: ALU64Inst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
- "$Rd = modwrap($Rs, $Rt)", [], "", ALU64_tc_2_SLOT23> {
- bits<5> Rd;
- bits<5> Rs;
- bits<5> Rt;
-
- let IClass = 0b1101;
- let Inst{27-21} = 0b0011111;
- let Inst{20-16} = Rs;
- let Inst{12-8} = Rt;
- let Inst{7-5} = 0b111;
- let Inst{4-0} = Rd;
-}
-
-let hasSideEffects = 0 in
-def A4_bitsplit: ALU64Inst<(outs DoubleRegs:$Rd),
- (ins IntRegs:$Rs, IntRegs:$Rt),
- "$Rd = bitsplit($Rs, $Rt)", [], "", ALU64_tc_1_SLOT23> {
- bits<5> Rd;
- bits<5> Rs;
- bits<5> Rt;
-
- let IClass = 0b1101;
- let Inst{27-24} = 0b0100;
- let Inst{21} = 0b1;
- let Inst{20-16} = Rs;
- let Inst{12-8} = Rt;
- let Inst{4-0} = Rd;
-}
-
-let hasSideEffects = 0 in
-def dep_S2_packhl: ALU64Inst<(outs DoubleRegs:$Rd),
- (ins IntRegs:$Rs, IntRegs:$Rt),
- "$Rd = packhl($Rs, $Rt):deprecated", [], "", ALU64_tc_1_SLOT23> {
- bits<5> Rd;
- bits<5> Rs;
- bits<5> Rt;
-
- let IClass = 0b1101;
- let Inst{27-24} = 0b0100;
- let Inst{21} = 0b0;
- let Inst{20-16} = Rs;
- let Inst{12-8} = Rt;
- let Inst{4-0} = Rd;
-}
-
-let hasNewValue = 1, hasSideEffects = 0 in
-def dep_A2_addsat: ALU64Inst<(outs IntRegs:$Rd),
- (ins IntRegs:$Rs, IntRegs:$Rt),
- "$Rd = add($Rs, $Rt):sat:deprecated", [], "", ALU64_tc_2_SLOT23> {
- bits<5> Rd;
- bits<5> Rs;
- bits<5> Rt;
-
- let IClass = 0b1101;
- let Inst{27-21} = 0b0101100;
- let Inst{20-16} = Rs;
- let Inst{12-8} = Rt;
- let Inst{7} = 0b0;
- let Inst{4-0} = Rd;
-}
-
-let hasNewValue = 1, hasSideEffects = 0 in
-def dep_A2_subsat: ALU64Inst<(outs IntRegs:$Rd),
- (ins IntRegs:$Rs, IntRegs:$Rt),
- "$Rd = sub($Rs, $Rt):sat:deprecated", [], "", ALU64_tc_2_SLOT23> {
- bits<5> Rd;
- bits<5> Rs;
- bits<5> Rt;
-
- let IClass = 0b1101;
- let Inst{27-21} = 0b0101100;
- let Inst{20-16} = Rt;
- let Inst{12-8} = Rs;
- let Inst{7} = 0b1;
- let Inst{4-0} = Rd;
-}
-
-// Rx[&|]=xor(Rs,Rt)
-def M4_or_xor : T_MType_acc_rr < "|= xor", 0b110, 0b001, 0>;
-def M4_and_xor : T_MType_acc_rr < "&= xor", 0b010, 0b010, 0>;
-
-// Rx[&|^]=or(Rs,Rt)
-def M4_xor_or : T_MType_acc_rr < "^= or", 0b110, 0b011, 0>;
-
-let CextOpcode = "ORr_ORr" in
-def M4_or_or : T_MType_acc_rr < "|= or", 0b110, 0b000, 0>;
-def M4_and_or : T_MType_acc_rr < "&= or", 0b010, 0b001, 0>;
-
-// Rx[&|^]=and(Rs,Rt)
-def M4_xor_and : T_MType_acc_rr < "^= and", 0b110, 0b010, 0>;
-
-let CextOpcode = "ORr_ANDr" in
-def M4_or_and : T_MType_acc_rr < "|= and", 0b010, 0b011, 0>;
-def M4_and_and : T_MType_acc_rr < "&= and", 0b010, 0b000, 0>;
-
-// Rx[&|^]=and(Rs,~Rt)
-def M4_xor_andn : T_MType_acc_rr < "^= and", 0b001, 0b010, 0, [], 1>;
-def M4_or_andn : T_MType_acc_rr < "|= and", 0b001, 0b000, 0, [], 1>;
-def M4_and_andn : T_MType_acc_rr < "&= and", 0b001, 0b001, 0, [], 1>;
-
-// Compound or-or and or-and
-let isExtentSigned = 1, InputType = "imm", hasNewValue = 1, isExtendable = 1,
- opExtentBits = 10, opExtendable = 3 in
-class T_CompOR <string mnemonic, bits<2> MajOp, SDNode OpNode>
- : MInst_acc <(outs IntRegs:$Rx),
- (ins IntRegs:$src1, IntRegs:$Rs, s10_0Ext:$s10),
- "$Rx |= "#mnemonic#"($Rs, #$s10)", [],
- "$src1 = $Rx", ALU64_tc_2_SLOT23>, ImmRegRel {
- bits<5> Rx;
- bits<5> Rs;
- bits<10> s10;
-
- let IClass = 0b1101;
-
- let Inst{27-24} = 0b1010;
- let Inst{23-22} = MajOp;
- let Inst{20-16} = Rs;
- let Inst{21} = s10{9};
- let Inst{13-5} = s10{8-0};
- let Inst{4-0} = Rx;
- }
-
-let CextOpcode = "ORr_ANDr" in
-def S4_or_andi : T_CompOR <"and", 0b00, and>;
-
-let CextOpcode = "ORr_ORr" in
-def S4_or_ori : T_CompOR <"or", 0b10, or>;
-
-// Modulo wrap
-// Rd=modwrap(Rs,Rt)
-// Round
-// Rd=cround(Rs,#u5)
-// Rd=cround(Rs,Rt)
-// Rd=round(Rs,#u5)[:sat]
-// Rd=round(Rs,Rt)[:sat]
-// Vector reduce add unsigned halfwords
-// Rd=vraddh(Rss,Rtt)
-// Vector add bytes
-// Rdd=vaddb(Rss,Rtt)
-// Vector conditional negate
-// Rdd=vcnegh(Rss,Rt)
-// Rxx+=vrcnegh(Rss,Rt)
-// Vector maximum bytes
-// Rdd=vmaxb(Rtt,Rss)
-// Vector reduce maximum halfwords
-// Rxx=vrmaxh(Rss,Ru)
-// Rxx=vrmaxuh(Rss,Ru)
-// Vector reduce maximum words
-// Rxx=vrmaxuw(Rss,Ru)
-// Rxx=vrmaxw(Rss,Ru)
-// Vector minimum bytes
-// Rdd=vminb(Rtt,Rss)
-// Vector reduce minimum halfwords
-// Rxx=vrminh(Rss,Ru)
-// Rxx=vrminuh(Rss,Ru)
-// Vector reduce minimum words
-// Rxx=vrminuw(Rss,Ru)
-// Rxx=vrminw(Rss,Ru)
-// Vector subtract bytes
-// Rdd=vsubb(Rss,Rtt)
-
-//===----------------------------------------------------------------------===//
-// XTYPE/ALU -
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// XTYPE/BIT +
-//===----------------------------------------------------------------------===//
-
-// Bit reverse
-def S2_brevp : T_S2op_3 <"brev", 0b11, 0b110>;
-
-// Bit count
-def S2_ct0p : T_COUNT_LEADING_64<"ct0", 0b111, 0b010>;
-def S2_ct1p : T_COUNT_LEADING_64<"ct1", 0b111, 0b100>;
-def S4_clbpnorm : T_COUNT_LEADING_64<"normamt", 0b011, 0b000>;
-
-let hasSideEffects = 0, hasNewValue = 1 in
-def S4_clbaddi : SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, s6_0Imm:$s6),
- "$Rd = add(clb($Rs), #$s6)", [], "", S_2op_tc_2_SLOT23> {
- bits<5> Rs;
- bits<5> Rd;
- bits<6> s6;
- let IClass = 0b1000;
- let Inst{27-24} = 0b1100;
- let Inst{23-21} = 0b001;
- let Inst{20-16} = Rs;
- let Inst{13-8} = s6;
- let Inst{7-5} = 0b000;
- let Inst{4-0} = Rd;
-}
-
-let hasSideEffects = 0, hasNewValue = 1 in
-def S4_clbpaddi : SInst<(outs IntRegs:$Rd), (ins DoubleRegs:$Rs, s6_0Imm:$s6),
- "$Rd = add(clb($Rs), #$s6)", [], "", S_2op_tc_2_SLOT23> {
- bits<5> Rs;
- bits<5> Rd;
- bits<6> s6;
- let IClass = 0b1000;
- let Inst{27-24} = 0b1000;
- let Inst{23-21} = 0b011;
- let Inst{20-16} = Rs;
- let Inst{13-8} = s6;
- let Inst{7-5} = 0b010;
- let Inst{4-0} = Rd;
-}
-
-
-// Bit test/set/clear
-def S4_ntstbit_i : T_TEST_BIT_IMM<"!tstbit", 0b001>;
-def S4_ntstbit_r : T_TEST_BIT_REG<"!tstbit", 1>;
-
-def C4_nbitsset : T_TEST_BITS_REG<"!bitsset", 0b01, 1>;
-def C4_nbitsclr : T_TEST_BITS_REG<"!bitsclr", 0b10, 1>;
-def C4_nbitsclri : T_TEST_BITS_IMM<"!bitsclr", 0b10, 1>;
-
-//===----------------------------------------------------------------------===//
-// XTYPE/BIT -
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// XTYPE/MPY +
-//===----------------------------------------------------------------------===//
-
-// Rd=add(#u6,mpyi(Rs,#U6)) -- Multiply by immed and add immed.
-
-let hasNewValue = 1, isExtendable = 1, opExtentBits = 6, opExtendable = 1 in
-def M4_mpyri_addi : MInst<(outs IntRegs:$Rd),
- (ins u6_0Ext:$u6, IntRegs:$Rs, u6_0Imm:$U6),
- "$Rd = add(#$u6, mpyi($Rs, #$U6))" , [],"",ALU64_tc_3x_SLOT23> {
- bits<5> Rd;
- bits<6> u6;
- bits<5> Rs;
- bits<6> U6;
-
- let IClass = 0b1101;
-
- let Inst{27-24} = 0b1000;
- let Inst{23} = U6{5};
- let Inst{22-21} = u6{5-4};
- let Inst{20-16} = Rs;
- let Inst{13} = u6{3};
- let Inst{12-8} = Rd;
- let Inst{7-5} = u6{2-0};
- let Inst{4-0} = U6{4-0};
- }
-
-// Rd=add(#u6,mpyi(Rs,Rt))
-let CextOpcode = "ADD_MPY", InputType = "imm", hasNewValue = 1,
- isExtendable = 1, opExtentBits = 6, opExtendable = 1 in
-def M4_mpyrr_addi : MInst <(outs IntRegs:$Rd),
- (ins u6_0Ext:$u6, IntRegs:$Rs, IntRegs:$Rt),
- "$Rd = add(#$u6, mpyi($Rs, $Rt))" , [], "", ALU64_tc_3x_SLOT23>, ImmRegRel {
- bits<5> Rd;
- bits<6> u6;
- bits<5> Rs;
- bits<5> Rt;
-
- let IClass = 0b1101;
-
- let Inst{27-23} = 0b01110;
- let Inst{22-21} = u6{5-4};
- let Inst{20-16} = Rs;
- let Inst{13} = u6{3};
- let Inst{12-8} = Rt;
- let Inst{7-5} = u6{2-0};
- let Inst{4-0} = Rd;
- }
-
-let hasNewValue = 1 in
-class T_AddMpy <bit MajOp, PatLeaf ImmPred, dag ins>
- : ALU64Inst <(outs IntRegs:$dst), ins,
- "$dst = add($src1, mpyi("#!if(MajOp,"$src3, #$src2))",
- "#$src2, $src3))"), [],
- "", ALU64_tc_3x_SLOT23> {
- bits<5> dst;
- bits<5> src1;
- bits<8> src2;
- bits<5> src3;
-
- let IClass = 0b1101;
-
- bits<6> ImmValue = !if(MajOp, src2{5-0}, src2{7-2});
-
- let Inst{27-24} = 0b1111;
- let Inst{23} = MajOp;
- let Inst{22-21} = ImmValue{5-4};
- let Inst{20-16} = src3;
- let Inst{13} = ImmValue{3};
- let Inst{12-8} = dst;
- let Inst{7-5} = ImmValue{2-0};
- let Inst{4-0} = src1;
- }
-
-def M4_mpyri_addr_u2 : T_AddMpy<0b0, u6_2ImmPred,
- (ins IntRegs:$src1, u6_2Imm:$src2, IntRegs:$src3)>;
-
-let isExtendable = 1, opExtentBits = 6, opExtendable = 3,
- CextOpcode = "ADD_MPY", InputType = "imm" in
-def M4_mpyri_addr : T_AddMpy<0b1, u32_0ImmPred,
- (ins IntRegs:$src1, IntRegs:$src3, u6_0Ext:$src2)>, ImmRegRel;
-
-// Rx=add(Ru,mpyi(Rx,Rs))
-let CextOpcode = "ADD_MPY", InputType = "reg", hasNewValue = 1 in
-def M4_mpyrr_addr: MInst_acc <(outs IntRegs:$Rx),
- (ins IntRegs:$Ru, IntRegs:$_src_, IntRegs:$Rs),
- "$Rx = add($Ru, mpyi($_src_, $Rs))", [],
- "$_src_ = $Rx", M_tc_3x_SLOT23>, ImmRegRel {
- bits<5> Rx;
- bits<5> Ru;
- bits<5> Rs;
-
- let IClass = 0b1110;
-
- let Inst{27-21} = 0b0011000;
- let Inst{12-8} = Rx;
- let Inst{4-0} = Ru;
- let Inst{20-16} = Rs;
- }
-
-
-// Vector reduce multiply word by signed half (32x16)
-//Rdd=vrmpyweh(Rss,Rtt)[:<<1]
-def M4_vrmpyeh_s0 : T_M2_vmpy<"vrmpyweh", 0b010, 0b100, 0, 0, 0>;
-def M4_vrmpyeh_s1 : T_M2_vmpy<"vrmpyweh", 0b110, 0b100, 1, 0, 0>;
-
-//Rdd=vrmpywoh(Rss,Rtt)[:<<1]
-def M4_vrmpyoh_s0 : T_M2_vmpy<"vrmpywoh", 0b001, 0b010, 0, 0, 0>;
-def M4_vrmpyoh_s1 : T_M2_vmpy<"vrmpywoh", 0b101, 0b010, 1, 0, 0>;
-
-//Rdd+=vrmpyweh(Rss,Rtt)[:<<1]
-def M4_vrmpyeh_acc_s0: T_M2_vmpy_acc<"vrmpyweh", 0b001, 0b110, 0, 0>;
-def M4_vrmpyeh_acc_s1: T_M2_vmpy_acc<"vrmpyweh", 0b101, 0b110, 1, 0>;
-
-//Rdd=vrmpywoh(Rss,Rtt)[:<<1]
-def M4_vrmpyoh_acc_s0: T_M2_vmpy_acc<"vrmpywoh", 0b011, 0b110, 0, 0>;
-def M4_vrmpyoh_acc_s1: T_M2_vmpy_acc<"vrmpywoh", 0b111, 0b110, 1, 0>;
-
-// Vector multiply halfwords, signed by unsigned
-// Rdd=vmpyhsu(Rs,Rt)[:<<]:sat
-def M2_vmpy2su_s0 : T_XTYPE_mpy64 < "vmpyhsu", 0b000, 0b111, 1, 0, 0>;
-def M2_vmpy2su_s1 : T_XTYPE_mpy64 < "vmpyhsu", 0b100, 0b111, 1, 1, 0>;
-
-// Rxx+=vmpyhsu(Rs,Rt)[:<<1]:sat
-def M2_vmac2su_s0 : T_XTYPE_mpy64_acc < "vmpyhsu", "+", 0b011, 0b101, 1, 0, 0>;
-def M2_vmac2su_s1 : T_XTYPE_mpy64_acc < "vmpyhsu", "+", 0b111, 0b101, 1, 1, 0>;
-
-// Vector polynomial multiply halfwords
-// Rdd=vpmpyh(Rs,Rt)
-def M4_vpmpyh : T_XTYPE_mpy64 < "vpmpyh", 0b110, 0b111, 0, 0, 0>;
-
-// Rxx^=vpmpyh(Rs,Rt)
-def M4_vpmpyh_acc : T_XTYPE_mpy64_acc < "vpmpyh", "^", 0b101, 0b111, 0, 0, 0>;
-
-// Polynomial multiply words
-// Rdd=pmpyw(Rs,Rt)
-def M4_pmpyw : T_XTYPE_mpy64 < "pmpyw", 0b010, 0b111, 0, 0, 0>;
-
-// Rxx^=pmpyw(Rs,Rt)
-def M4_pmpyw_acc : T_XTYPE_mpy64_acc < "pmpyw", "^", 0b001, 0b111, 0, 0, 0>;
-
-//===----------------------------------------------------------------------===//
-// XTYPE/MPY -
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// ALU64/Vector compare
-//===----------------------------------------------------------------------===//
-//===----------------------------------------------------------------------===//
-// Template class for vector compare
-//===----------------------------------------------------------------------===//
-
-let hasSideEffects = 0 in
-class T_vcmpImm <string Str, bits<2> cmpOp, bits<2> minOp, Operand ImmOprnd>
- : ALU64_rr <(outs PredRegs:$Pd),
- (ins DoubleRegs:$Rss, ImmOprnd:$Imm),
- "$Pd = "#Str#"($Rss, #$Imm)",
- [], "", ALU64_tc_2early_SLOT23> {
- bits<2> Pd;
- bits<5> Rss;
- bits<32> Imm;
- bits<8> ImmBits;
- let ImmBits{6-0} = Imm{6-0};
- let ImmBits{7} = !if (!eq(cmpOp,0b10), 0b0, Imm{7}); // 0 for vcmp[bhw].gtu
-
- let IClass = 0b1101;
-
- let Inst{27-24} = 0b1100;
- let Inst{22-21} = cmpOp;
- let Inst{20-16} = Rss;
- let Inst{12-5} = ImmBits;
- let Inst{4-3} = minOp;
- let Inst{1-0} = Pd;
- }
-
-// Vector compare bytes
-def A4_vcmpbgt : T_vcmp <"vcmpb.gt", 0b1010>;
-
-let AsmString = "$Pd = any8(vcmpb.eq($Rss, $Rtt))" in
-def A4_vcmpbeq_any : T_vcmp <"any8(vcmpb.gt", 0b1000>;
-
-def A4_vcmpbeqi : T_vcmpImm <"vcmpb.eq", 0b00, 0b00, u8_0Imm>;
-def A4_vcmpbgti : T_vcmpImm <"vcmpb.gt", 0b01, 0b00, s8_0Imm>;
-def A4_vcmpbgtui : T_vcmpImm <"vcmpb.gtu", 0b10, 0b00, u7_0Imm>;
-
-// Vector compare halfwords
-def A4_vcmpheqi : T_vcmpImm <"vcmph.eq", 0b00, 0b01, s8_0Imm>;
-def A4_vcmphgti : T_vcmpImm <"vcmph.gt", 0b01, 0b01, s8_0Imm>;
-def A4_vcmphgtui : T_vcmpImm <"vcmph.gtu", 0b10, 0b01, u7_0Imm>;
-
-// Vector compare words
-def A4_vcmpweqi : T_vcmpImm <"vcmpw.eq", 0b00, 0b10, s8_0Imm>;
-def A4_vcmpwgti : T_vcmpImm <"vcmpw.gt", 0b01, 0b10, s8_0Imm>;
-def A4_vcmpwgtui : T_vcmpImm <"vcmpw.gtu", 0b10, 0b10, u7_0Imm>;
-
-//===----------------------------------------------------------------------===//
-// XTYPE/SHIFT +
-//===----------------------------------------------------------------------===//
-// Shift by immediate and accumulate/logical.
-// Rx=add(#u8,asl(Rx,#U5)) Rx=add(#u8,lsr(Rx,#U5))
-// Rx=sub(#u8,asl(Rx,#U5)) Rx=sub(#u8,lsr(Rx,#U5))
-// Rx=and(#u8,asl(Rx,#U5)) Rx=and(#u8,lsr(Rx,#U5))
-// Rx=or(#u8,asl(Rx,#U5)) Rx=or(#u8,lsr(Rx,#U5))
-let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
- hasNewValue = 1, opNewValue = 0 in
-class T_S4_ShiftOperate<string MnOp, string MnSh, bit asl_lsr,
- bits<2> MajOp, InstrItinClass Itin>
- : MInst_acc<(outs IntRegs:$Rd), (ins u8_0Ext:$u8, IntRegs:$Rx, u5_0Imm:$U5),
- "$Rd = "#MnOp#"(#$u8, "#MnSh#"($Rx, #$U5))",
- [], "$Rd = $Rx", Itin> {
-
- bits<5> Rd;
- bits<8> u8;
- bits<5> Rx;
- bits<5> U5;
-
- let IClass = 0b1101;
- let Inst{27-24} = 0b1110;
- let Inst{23-21} = u8{7-5};
- let Inst{20-16} = Rd;
- let Inst{13} = u8{4};
- let Inst{12-8} = U5;
- let Inst{7-5} = u8{3-1};
- let Inst{4} = asl_lsr;
- let Inst{3} = u8{0};
- let Inst{2-1} = MajOp;
-}
-
-multiclass T_ShiftOperate<string mnemonic, bits<2> MajOp, InstrItinClass Itin> {
- def _asl_ri : T_S4_ShiftOperate<mnemonic, "asl", 0, MajOp, Itin>;
- def _lsr_ri : T_S4_ShiftOperate<mnemonic, "lsr", 1, MajOp, Itin>;
-}
-
-defm S4_addi : T_ShiftOperate<"add", 0b10, ALU64_tc_2_SLOT23>;
-defm S4_andi : T_ShiftOperate<"and", 0b00, ALU64_tc_2_SLOT23>;
-defm S4_ori : T_ShiftOperate<"or", 0b01, ALU64_tc_1_SLOT23>;
-defm S4_subi : T_ShiftOperate<"sub", 0b11, ALU64_tc_1_SLOT23>;
-
-// Vector conditional negate
-// Rdd=vcnegh(Rss,Rt)
-let Defs = [USR_OVF], Itinerary = S_3op_tc_2_SLOT23 in
-def S2_vcnegh : T_S3op_shiftVect < "vcnegh", 0b11, 0b01>;
-
-// Rd=[cround|round](Rs,Rt)
-let hasNewValue = 1, Itinerary = S_3op_tc_2_SLOT23 in {
- def A4_cround_rr : T_S3op_3 < "cround", IntRegs, 0b11, 0b00>;
- def A4_round_rr : T_S3op_3 < "round", IntRegs, 0b11, 0b10>;
-}
-
-// Rd=round(Rs,Rt):sat
-let hasNewValue = 1, Defs = [USR_OVF], Itinerary = S_3op_tc_2_SLOT23 in
-def A4_round_rr_sat : T_S3op_3 < "round", IntRegs, 0b11, 0b11, 1>;
-
-// Rd=[cmpyiwh|cmpyrwh](Rss,Rt):<<1:rnd:sat
-let Defs = [USR_OVF], Itinerary = S_3op_tc_3x_SLOT23 in {
- def M4_cmpyi_wh : T_S3op_8<"cmpyiwh", 0b100, 1, 1, 1>;
- def M4_cmpyr_wh : T_S3op_8<"cmpyrwh", 0b110, 1, 1, 1>;
-}
-
-// Rdd=[add|sub](Rss,Rtt,Px):carry
-let isPredicateLate = 1, hasSideEffects = 0 in
-class T_S3op_carry <string mnemonic, bits<3> MajOp>
- : SInst < (outs DoubleRegs:$Rdd, PredRegs:$Px),
- (ins DoubleRegs:$Rss, DoubleRegs:$Rtt, PredRegs:$Pu),
- "$Rdd = "#mnemonic#"($Rss, $Rtt, $Pu):carry",
- [], "$Px = $Pu", S_3op_tc_1_SLOT23 > {
- bits<5> Rdd;
- bits<5> Rss;
- bits<5> Rtt;
- bits<2> Pu;
-
- let IClass = 0b1100;
-
- let Inst{27-24} = 0b0010;
- let Inst{23-21} = MajOp;
- let Inst{20-16} = Rss;
- let Inst{12-8} = Rtt;
- let Inst{6-5} = Pu;
- let Inst{4-0} = Rdd;
- }
-
-def A4_addp_c : T_S3op_carry < "add", 0b110 >;
-def A4_subp_c : T_S3op_carry < "sub", 0b111 >;
-
-let Itinerary = S_3op_tc_3_SLOT23, hasSideEffects = 0 in
-class T_S3op_6 <string mnemonic, bits<3> MinOp, bit isUnsigned>
- : SInst <(outs DoubleRegs:$Rxx),
- (ins DoubleRegs:$dst2, DoubleRegs:$Rss, IntRegs:$Ru),
- "$Rxx = "#mnemonic#"($Rss, $Ru)" ,
- [] , "$dst2 = $Rxx"> {
- bits<5> Rxx;
- bits<5> Rss;
- bits<5> Ru;
-
- let IClass = 0b1100;
-
- let Inst{27-21} = 0b1011001;
- let Inst{20-16} = Rss;
- let Inst{13} = isUnsigned;
- let Inst{12-8} = Rxx;
- let Inst{7-5} = MinOp;
- let Inst{4-0} = Ru;
- }
-
-// Vector reduce maximum halfwords
-// Rxx=vrmax[u]h(Rss,Ru)
-def A4_vrmaxh : T_S3op_6 < "vrmaxh", 0b001, 0>;
-def A4_vrmaxuh : T_S3op_6 < "vrmaxuh", 0b001, 1>;
-
-// Vector reduce maximum words
-// Rxx=vrmax[u]w(Rss,Ru)
-def A4_vrmaxw : T_S3op_6 < "vrmaxw", 0b010, 0>;
-def A4_vrmaxuw : T_S3op_6 < "vrmaxuw", 0b010, 1>;
-
-// Vector reduce minimum halfwords
-// Rxx=vrmin[u]h(Rss,Ru)
-def A4_vrminh : T_S3op_6 < "vrminh", 0b101, 0>;
-def A4_vrminuh : T_S3op_6 < "vrminuh", 0b101, 1>;
-
-// Vector reduce minimum words
-// Rxx=vrmin[u]w(Rss,Ru)
-def A4_vrminw : T_S3op_6 < "vrminw", 0b110, 0>;
-def A4_vrminuw : T_S3op_6 < "vrminuw", 0b110, 1>;
-
-// Shift an immediate left by register amount.
-let hasNewValue = 1, hasSideEffects = 0 in
-def S4_lsli: SInst <(outs IntRegs:$Rd), (ins s6_0Imm:$s6, IntRegs:$Rt),
- "$Rd = lsl(#$s6, $Rt)" , [], "", S_3op_tc_1_SLOT23> {
- bits<5> Rd;
- bits<6> s6;
- bits<5> Rt;
-
- let IClass = 0b1100;
-
- let Inst{27-22} = 0b011010;
- let Inst{20-16} = s6{5-1};
- let Inst{12-8} = Rt;
- let Inst{7-6} = 0b11;
- let Inst{4-0} = Rd;
- let Inst{5} = s6{0};
- }
-
-//===----------------------------------------------------------------------===//
-// XTYPE/SHIFT -
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// MEMOP
-//===----------------------------------------------------------------------===//
-
-
-//===----------------------------------------------------------------------===//
-// Template class for MemOp instructions with the register value.
-//===----------------------------------------------------------------------===//
-class MemOp_rr_base <string opc, bits<2> opcBits, Operand ImmOp,
- string memOp, bits<2> memOpBits> :
- MEMInst_V4<(outs),
- (ins IntRegs:$base, ImmOp:$offset, IntRegs:$delta),
- opc#"($base+#$offset)"#memOp#"$delta",
- []>,
- Requires<[UseMEMOP]> {
-
- bits<5> base;
- bits<5> delta;
- bits<32> offset;
- bits<6> offsetBits; // memb - u6:0 , memh - u6:1, memw - u6:2
-
- let offsetBits = !if (!eq(opcBits, 0b00), offset{5-0},
- !if (!eq(opcBits, 0b01), offset{6-1},
- !if (!eq(opcBits, 0b10), offset{7-2},0)));
-
- let opExtentAlign = opcBits;
- let IClass = 0b0011;
- let Inst{27-24} = 0b1110;
- let Inst{22-21} = opcBits;
- let Inst{20-16} = base;
- let Inst{13} = 0b0;
- let Inst{12-7} = offsetBits;
- let Inst{6-5} = memOpBits;
- let Inst{4-0} = delta;
-}
-
-//===----------------------------------------------------------------------===//
-// Template class for MemOp instructions with the immediate value.
-//===----------------------------------------------------------------------===//
-class MemOp_ri_base <string opc, bits<2> opcBits, Operand ImmOp,
- string memOp, bits<2> memOpBits> :
- MEMInst_V4 <(outs),
- (ins IntRegs:$base, ImmOp:$offset, u5_0Imm:$delta),
- opc#"($base+#$offset)"#memOp#"#$delta"
- #!if(memOpBits{1},")", ""), // clrbit, setbit - include ')'
- []>,
- Requires<[UseMEMOP]> {
-
- bits<5> base;
- bits<5> delta;
- bits<32> offset;
- bits<6> offsetBits; // memb - u6:0 , memh - u6:1, memw - u6:2
-
- let offsetBits = !if (!eq(opcBits, 0b00), offset{5-0},
- !if (!eq(opcBits, 0b01), offset{6-1},
- !if (!eq(opcBits, 0b10), offset{7-2},0)));
-
- let opExtentAlign = opcBits;
- let IClass = 0b0011;
- let Inst{27-24} = 0b1111;
- let Inst{22-21} = opcBits;
- let Inst{20-16} = base;
- let Inst{13} = 0b0;
- let Inst{12-7} = offsetBits;
- let Inst{6-5} = memOpBits;
- let Inst{4-0} = delta;
-}
-
-// multiclass to define MemOp instructions with register operand.
-multiclass MemOp_rr<string opc, bits<2> opcBits, Operand ImmOp> {
- def L4_add#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " += ", 0b00>; // add
- def L4_sub#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " -= ", 0b01>; // sub
- def L4_and#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " &= ", 0b10>; // and
- def L4_or#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " |= ", 0b11>; // or
-}
-
-// multiclass to define MemOp instructions with immediate Operand.
-multiclass MemOp_ri<string opc, bits<2> opcBits, Operand ImmOp> {
- def L4_iadd#NAME : MemOp_ri_base <opc, opcBits, ImmOp, " += ", 0b00 >;
- def L4_isub#NAME : MemOp_ri_base <opc, opcBits, ImmOp, " -= ", 0b01 >;
- def L4_iand#NAME : MemOp_ri_base<opc, opcBits, ImmOp, " = clrbit(", 0b10>;
- def L4_ior#NAME : MemOp_ri_base<opc, opcBits, ImmOp, " = setbit(", 0b11>;
-}
-
-multiclass MemOp_base <string opc, bits<2> opcBits, Operand ImmOp> {
- defm _#NAME : MemOp_rr <opc, opcBits, ImmOp>;
- defm _#NAME : MemOp_ri <opc, opcBits, ImmOp>;
-}
-
-// Define MemOp instructions.
-let isExtendable = 1, opExtendable = 1, isExtentSigned = 0 in {
- let opExtentBits = 6, accessSize = ByteAccess in
- defm memopb_io : MemOp_base <"memb", 0b00, u6_0Ext>;
-
- let opExtentBits = 7, accessSize = HalfWordAccess in
- defm memoph_io : MemOp_base <"memh", 0b01, u6_1Ext>;
-
- let opExtentBits = 8, accessSize = WordAccess in
- defm memopw_io : MemOp_base <"memw", 0b10, u6_2Ext>;
-}
-
-
-//===----------------------------------------------------------------------===//
-// XTYPE/PRED +
-//===----------------------------------------------------------------------===//
-
-// Hexagon V4 only supports these flavors of byte/half compare instructions:
-// EQ/GT/GTU. Other flavors like GE/GEU/LT/LTU/LE/LEU are not supported by
-// hardware. However, compiler can still implement these patterns through
-// appropriate patterns combinations based on current implemented patterns.
-// The implemented patterns are: EQ/GT/GTU.
-// Missing patterns are: GE/GEU/LT/LTU/LE/LEU.
-
-// Following instruction is not being extended as it results into the
-// incorrect code for negative numbers.
-// Pd=cmpb.eq(Rs,#u8)
-
-// p=!cmp.eq(r1,#s10)
-def C4_cmpneqi : T_CMP <"cmp.eq", 0b00, 1, s10_0Ext>;
-def C4_cmpltei : T_CMP <"cmp.gt", 0b01, 1, s10_0Ext>;
-def C4_cmplteui : T_CMP <"cmp.gtu", 0b10, 1, u9_0Ext>;
-
-//===----------------------------------------------------------------------===//
-// XTYPE/PRED -
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// Multiclass for DeallocReturn
-//===----------------------------------------------------------------------===//
-class L4_RETURN<string mnemonic, bit isNot, bit isPredNew, bit isTak>
- : LD0Inst<(outs), (ins PredRegs:$src),
- !if(isNot, "if (!$src", "if ($src")#
- !if(isPredNew, ".new) ", ") ")#mnemonic#
- !if(isPredNew, #!if(isTak,":t", ":nt"),""),
- [], "", LD_tc_3or4stall_SLOT0> {
-
- bits<2> src;
- let BaseOpcode = "L4_RETURN";
- let isPredicatedFalse = isNot;
- let isPredicatedNew = isPredNew;
- let isTaken = isTak;
- let IClass = 0b1001;
-
- let Inst{27-16} = 0b011000011110;
-
- let Inst{13} = isNot;
- let Inst{12} = isTak;
- let Inst{11} = isPredNew;
- let Inst{10} = 0b0;
- let Inst{9-8} = src;
- let Inst{4-0} = 0b11110;
- }
-
-// Produce all predicated forms, p, !p, p.new, !p.new, :t, :nt
-multiclass L4_RETURN_PRED<string mnemonic, bit PredNot> {
- let isPredicated = 1 in {
- def _#NAME# : L4_RETURN <mnemonic, PredNot, 0, 1>;
- def _#NAME#new_pnt : L4_RETURN <mnemonic, PredNot, 1, 0>;
- def _#NAME#new_pt : L4_RETURN <mnemonic, PredNot, 1, 1>;
- }
-}
-
-multiclass LD_MISC_L4_RETURN<string mnemonic> {
- let isBarrier = 1, isPredicable = 1 in
- def NAME : LD0Inst <(outs), (ins), mnemonic, [], "",
- LD_tc_3or4stall_SLOT0> {
- let BaseOpcode = "L4_RETURN";
- let IClass = 0b1001;
- let Inst{27-16} = 0b011000011110;
- let Inst{13-10} = 0b0000;
- let Inst{4-0} = 0b11110;
- }
- defm t : L4_RETURN_PRED<mnemonic, 0 >;
- defm f : L4_RETURN_PRED<mnemonic, 1 >;
-}
-
-let isReturn = 1, isTerminator = 1,
- Defs = [R29, R30, R31, PC], Uses = [R30], hasSideEffects = 0 in
-defm L4_return: LD_MISC_L4_RETURN <"dealloc_return">, PredNewRel;
-
-// Restore registers and dealloc return function call.
-let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,
- Defs = [R29, R30, R31, PC], isPredicable = 0, isAsmParserOnly = 1 in {
- def RESTORE_DEALLOC_RET_JMP_V4 : T_JMP<"">;
-
- let isExtended = 1, opExtendable = 0 in
- def RESTORE_DEALLOC_RET_JMP_V4_EXT : T_JMP<"">;
-
- let Defs = [R14, R15, R28, R29, R30, R31, PC] in {
- def RESTORE_DEALLOC_RET_JMP_V4_PIC : T_JMP<"">;
-
- let isExtended = 1, opExtendable = 0 in
- def RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC : T_JMP<"">;
- }
-}
-
-// Restore registers and dealloc frame before a tail call.
-let isCall = 1, Defs = [R29, R30, R31, PC], isAsmParserOnly = 1 in {
- def RESTORE_DEALLOC_BEFORE_TAILCALL_V4 : T_Call<0, "">, PredRel;
-
- let isExtended = 1, opExtendable = 0 in
- def RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT : T_Call<0, "">, PredRel;
-
- let Defs = [R14, R15, R28, R29, R30, R31, PC] in {
- def RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC : T_Call<0, "">, PredRel;
-
- let isExtended = 1, opExtendable = 0 in
- def RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC : T_Call<0, "">, PredRel;
- }
-}
-
-// Save registers function call.
-let isCall = 1, Uses = [R29, R31], isAsmParserOnly = 1 in {
- def SAVE_REGISTERS_CALL_V4 : T_Call<0, "">, PredRel;
-
- let isExtended = 1, opExtendable = 0 in
- def SAVE_REGISTERS_CALL_V4_EXT : T_Call<0, "">, PredRel;
-
- let Defs = [P0] in
- def SAVE_REGISTERS_CALL_V4STK : T_Call<0, "">, PredRel;
-
- let Defs = [P0], isExtended = 1, opExtendable = 0 in
- def SAVE_REGISTERS_CALL_V4STK_EXT : T_Call<0, "">, PredRel;
-
- let Defs = [R14, R15, R28] in
- def SAVE_REGISTERS_CALL_V4_PIC : T_Call<0, "">, PredRel;
-
- let Defs = [R14, R15, R28], isExtended = 1, opExtendable = 0 in
- def SAVE_REGISTERS_CALL_V4_EXT_PIC : T_Call<0, "">, PredRel;
-
- let Defs = [R14, R15, R28, P0] in
- def SAVE_REGISTERS_CALL_V4STK_PIC : T_Call<0, "">, PredRel;
-
- let Defs = [R14, R15, R28, P0], isExtended = 1, opExtendable = 0 in
- def SAVE_REGISTERS_CALL_V4STK_EXT_PIC : T_Call<0, "">, PredRel;
-}
-
-//===----------------------------------------------------------------------===//
-// Template class for non predicated store instructions with
-// GP-Relative or absolute addressing.
-//===----------------------------------------------------------------------===//
-let hasSideEffects = 0, isPredicable = 1 in
-class T_StoreAbsGP <string mnemonic, RegisterClass RC, Operand ImmOp,
- bits<2>MajOp, bit isAbs, bit isHalf>
- : STInst<(outs), (ins ImmOp:$addr, RC:$src),
- mnemonic # "(" # !if(isAbs,"","gp+") # "#$addr) = $src" # !if(isHalf,".h",""),
- [], "", V2LDST_tc_st_SLOT01> {
- bits<19> addr;
- bits<5> src;
- bits<16> offsetBits;
-
- string ImmOpStr = !cast<string>(ImmOp);
- let offsetBits = !if (!eq(ImmOpStr, "u16_3Imm"), addr{18-3},
- !if (!eq(ImmOpStr, "u16_2Imm"), addr{17-2},
- !if (!eq(ImmOpStr, "u16_1Imm"), addr{16-1},
- /* u16_0Imm */ addr{15-0})));
- let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19,
- !if (!eq(ImmOpStr, "u16_2Imm"), 18,
- !if (!eq(ImmOpStr, "u16_1Imm"), 17,
- /* u16_0Imm */ 16)));
- let opExtentAlign = !if (!eq(ImmOpStr, "u16_3Imm"), 3,
- !if (!eq(ImmOpStr, "u16_2Imm"), 2,
- !if (!eq(ImmOpStr, "u16_1Imm"), 1,
- /* u16_0Imm */ 0)));
- // Store upper-half and store doubleword cannot be NV.
- let isNVStorable = !if (!eq(mnemonic, "memd"), 0, !if(isHalf,0,1));
- let Uses = !if (isAbs, [], [GP]);
-
- let IClass = 0b0100;
- let Inst{27} = 1;
- let Inst{26-25} = offsetBits{15-14};
- let Inst{24} = 0b0;
- let Inst{23-22} = MajOp;
- let Inst{21} = isHalf;
- let Inst{20-16} = offsetBits{13-9};
- let Inst{13} = offsetBits{8};
- let Inst{12-8} = src;
- let Inst{7-0} = offsetBits{7-0};
- }
-
-//===----------------------------------------------------------------------===//
-// Template class for predicated store instructions with
-// GP-Relative or absolute addressing.
-//===----------------------------------------------------------------------===//
-let hasSideEffects = 0, isPredicated = 1, opExtentBits = 6, opExtendable = 1 in
-class T_StoreAbs_Pred <string mnemonic, RegisterClass RC, bits<2> MajOp,
- bit isHalf, bit isNot, bit isNew>
- : STInst<(outs), (ins PredRegs:$src1, u32_0MustExt:$absaddr, RC: $src2),
- !if(isNot, "if (!$src1", "if ($src1")#!if(isNew, ".new) ",
- ") ")#mnemonic#"(#$absaddr) = $src2"#!if(isHalf, ".h",""),
- [], "", ST_tc_st_SLOT01>, AddrModeRel {
- bits<2> src1;
- bits<6> absaddr;
- bits<5> src2;
-
- let isPredicatedNew = isNew;
- let isPredicatedFalse = isNot;
- // Store upper-half and store doubleword cannot be NV.
- let isNVStorable = !if (!eq(mnemonic, "memd"), 0, !if(isHalf,0,1));
-
- let IClass = 0b1010;
-
- let Inst{27-24} = 0b1111;
- let Inst{23-22} = MajOp;
- let Inst{21} = isHalf;
- let Inst{17-16} = absaddr{5-4};
- let Inst{13} = isNew;
- let Inst{12-8} = src2;
- let Inst{7} = 0b1;
- let Inst{6-3} = absaddr{3-0};
- let Inst{2} = isNot;
- let Inst{1-0} = src1;
- }
-
-//===----------------------------------------------------------------------===//
-// Template class for predicated store instructions with absolute addressing.
-//===----------------------------------------------------------------------===//
-class T_StoreAbs <string mnemonic, RegisterClass RC, Operand ImmOp,
- bits<2> MajOp, bit isHalf>
- : T_StoreAbsGP <mnemonic, RC, u32_0MustExt, MajOp, 1, isHalf>,
- AddrModeRel {
- string ImmOpStr = !cast<string>(ImmOp);
- let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19,
- !if (!eq(ImmOpStr, "u16_2Imm"), 18,
- !if (!eq(ImmOpStr, "u16_1Imm"), 17,
- /* u16_0Imm */ 16)));
-
- let opExtentAlign = !if (!eq(ImmOpStr, "u16_3Imm"), 3,
- !if (!eq(ImmOpStr, "u16_2Imm"), 2,
- !if (!eq(ImmOpStr, "u16_1Imm"), 1,
- /* u16_0Imm */ 0)));
-}
-
-//===----------------------------------------------------------------------===//
-// Multiclass for store instructions with absolute addressing.
-//===----------------------------------------------------------------------===//
-let addrMode = Absolute, isExtended = 1 in
-multiclass ST_Abs<string mnemonic, string CextOp, RegisterClass RC,
- Operand ImmOp, bits<2> MajOp, bit isHalf = 0> {
- let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
- let opExtendable = 0, isPredicable = 1 in
- def PS_#NAME#abs : T_StoreAbs <mnemonic, RC, ImmOp, MajOp, isHalf>;
-
- // Predicated
- def S4_p#NAME#t_abs : T_StoreAbs_Pred<mnemonic, RC, MajOp, isHalf, 0, 0>;
- def S4_p#NAME#f_abs : T_StoreAbs_Pred<mnemonic, RC, MajOp, isHalf, 1, 0>;
-
- // .new Predicated
- def S4_p#NAME#tnew_abs : T_StoreAbs_Pred<mnemonic, RC, MajOp, isHalf, 0, 1>;
- def S4_p#NAME#fnew_abs : T_StoreAbs_Pred<mnemonic, RC, MajOp, isHalf, 1, 1>;
- }
-}
-
-//===----------------------------------------------------------------------===//
-// Template class for non predicated new-value store instructions with
-// GP-Relative or absolute addressing.
-//===----------------------------------------------------------------------===//
-let hasSideEffects = 0, isPredicable = 1, mayStore = 1, isNVStore = 1,
- isNewValue = 1, opNewValue = 1 in
-class T_StoreAbsGP_NV <string mnemonic, Operand ImmOp, bits<2>MajOp, bit isAbs>
- : NVInst_V4<(outs), (ins ImmOp:$addr, IntRegs:$src),
- mnemonic #"(" # !if(isAbs, "", "gp+") # "#$addr) = $src.new",
- [], "", V2LDST_tc_st_SLOT0> {
- bits<19> addr;
- bits<3> src;
- bits<16> offsetBits;
-
- string ImmOpStr = !cast<string>(ImmOp);
- let offsetBits = !if (!eq(ImmOpStr, "u16_3Imm"), addr{18-3},
- !if (!eq(ImmOpStr, "u16_2Imm"), addr{17-2},
- !if (!eq(ImmOpStr, "u16_1Imm"), addr{16-1},
- /* u16_0Imm */ addr{15-0})));
- let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19,
- !if (!eq(ImmOpStr, "u16_2Imm"), 18,
- !if (!eq(ImmOpStr, "u16_1Imm"), 17,
- /* u16_0Imm */ 16)));
- let opExtentAlign = !if (!eq(ImmOpStr, "u16_3Imm"), 3,
- !if (!eq(ImmOpStr, "u16_2Imm"), 2,
- !if (!eq(ImmOpStr, "u16_1Imm"), 1,
- /* u16_0Imm */ 0)));
- let IClass = 0b0100;
-
- let Inst{27} = 1;
- let Inst{26-25} = offsetBits{15-14};
- let Inst{24-21} = 0b0101;
- let Inst{20-16} = offsetBits{13-9};
- let Inst{13} = offsetBits{8};
- let Inst{12-11} = MajOp;
- let Inst{10-8} = src;
- let Inst{7-0} = offsetBits{7-0};
- }
-
-//===----------------------------------------------------------------------===//
-// Template class for predicated new-value store instructions with
-// absolute addressing.
-//===----------------------------------------------------------------------===//
-let hasSideEffects = 0, isPredicated = 1, mayStore = 1, isNVStore = 1,
- isNewValue = 1, opNewValue = 2, opExtentBits = 6, opExtendable = 1 in
-class T_StoreAbs_NV_Pred <string mnemonic, bits<2> MajOp, bit isNot, bit isNew>
- : NVInst_V4<(outs), (ins PredRegs:$src1, u32_0MustExt:$absaddr, IntRegs:$src2),
- !if(isNot, "if (!$src1", "if ($src1")#!if(isNew, ".new) ",
- ") ")#mnemonic#"(#$absaddr) = $src2.new",
- [], "", ST_tc_st_SLOT0>, AddrModeRel {
- bits<2> src1;
- bits<6> absaddr;
- bits<3> src2;
-
- let isPredicatedNew = isNew;
- let isPredicatedFalse = isNot;
-
- let IClass = 0b1010;
-
- let Inst{27-24} = 0b1111;
- let Inst{23-21} = 0b101;
- let Inst{17-16} = absaddr{5-4};
- let Inst{13} = isNew;
- let Inst{12-11} = MajOp;
- let Inst{10-8} = src2;
- let Inst{7} = 0b1;
- let Inst{6-3} = absaddr{3-0};
- let Inst{2} = isNot;
- let Inst{1-0} = src1;
-}
-
-//===----------------------------------------------------------------------===//
-// Template class for non-predicated new-value store instructions with
-// absolute addressing.
-//===----------------------------------------------------------------------===//
-class T_StoreAbs_NV <string mnemonic, Operand ImmOp, bits<2> MajOp>
- : T_StoreAbsGP_NV <mnemonic, u32_0MustExt, MajOp, 1>, AddrModeRel {
-
- string ImmOpStr = !cast<string>(ImmOp);
- let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19,
- !if (!eq(ImmOpStr, "u16_2Imm"), 18,
- !if (!eq(ImmOpStr, "u16_1Imm"), 17,
- /* u16_0Imm */ 16)));
-
- let opExtentAlign = !if (!eq(ImmOpStr, "u16_3Imm"), 3,
- !if (!eq(ImmOpStr, "u16_2Imm"), 2,
- !if (!eq(ImmOpStr, "u16_1Imm"), 1,
- /* u16_0Imm */ 0)));
-}
-
-//===----------------------------------------------------------------------===//
-// Multiclass for new-value store instructions with absolute addressing.
-//===----------------------------------------------------------------------===//
-let addrMode = Absolute, isExtended = 1 in
-multiclass ST_Abs_NV <string mnemonic, string CextOp, Operand ImmOp,
- bits<2> MajOp> {
- let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
- let opExtendable = 0, isPredicable = 1 in
- def PS_#NAME#newabs : T_StoreAbs_NV <mnemonic, ImmOp, MajOp>;
-
- // Predicated
- def S4_p#NAME#newt_abs : T_StoreAbs_NV_Pred <mnemonic, MajOp, 0, 0>;
- def S4_p#NAME#newf_abs : T_StoreAbs_NV_Pred <mnemonic, MajOp, 1, 0>;
-
- // .new Predicated
- def S4_p#NAME#newtnew_abs : T_StoreAbs_NV_Pred <mnemonic, MajOp, 0, 1>;
- def S4_p#NAME#newfnew_abs : T_StoreAbs_NV_Pred <mnemonic, MajOp, 1, 1>;
- }
-}
-
-//===----------------------------------------------------------------------===//
-// Stores with absolute addressing
-//===----------------------------------------------------------------------===//
-let accessSize = ByteAccess in
-defm storerb : ST_Abs <"memb", "STrib", IntRegs, u16_0Imm, 0b00>,
- ST_Abs_NV <"memb", "STrib", u16_0Imm, 0b00>;
-
-let accessSize = HalfWordAccess in
-defm storerh : ST_Abs <"memh", "STrih", IntRegs, u16_1Imm, 0b01>,
- ST_Abs_NV <"memh", "STrih", u16_1Imm, 0b01>;
-
-let accessSize = WordAccess in
-defm storeri : ST_Abs <"memw", "STriw", IntRegs, u16_2Imm, 0b10>,
- ST_Abs_NV <"memw", "STriw", u16_2Imm, 0b10>;
-
-let isNVStorable = 0, accessSize = DoubleWordAccess in
-defm storerd : ST_Abs <"memd", "STrid", DoubleRegs, u16_3Imm, 0b11>;
-
-let isNVStorable = 0, accessSize = HalfWordAccess in
-defm storerf : ST_Abs <"memh", "STrif", IntRegs, u16_1Imm, 0b01, 1>;
-
-//===----------------------------------------------------------------------===//
-// GP-relative stores.
-// mem[bhwd](#global)=Rt
-// Once predicated, these instructions map to absolute addressing mode.
-// if ([!]Pv[.new]) mem[bhwd](##global)=Rt
-//===----------------------------------------------------------------------===//
-
-let Uses = [GP], isAsmParserOnly = 1 in
-class T_StoreGP <string mnemonic, string BaseOp, RegisterClass RC,
- Operand ImmOp, bits<2> MajOp, bit isHalf = 0>
- : T_StoreAbsGP <mnemonic, RC, ImmOp, MajOp, 0, isHalf> {
- // Set BaseOpcode same as absolute addressing instructions so that
- // non-predicated GP-Rel instructions can have relate with predicated
- // Absolute instruction.
- let BaseOpcode = BaseOp#_abs;
- }
-
-let Uses = [GP], isAsmParserOnly = 1 in
-multiclass ST_GP <string mnemonic, string BaseOp, Operand ImmOp,
- bits<2> MajOp, bit isHalf = 0> {
- // Set BaseOpcode same as absolute addressing instructions so that
- // non-predicated GP-Rel instructions can have relate with predicated
- // Absolute instruction.
- let BaseOpcode = BaseOp#_abs in {
- def NAME#gp : T_StoreAbsGP <mnemonic, IntRegs, ImmOp, MajOp,
- 0, isHalf>;
- // New-value store
- def NAME#newgp : T_StoreAbsGP_NV <mnemonic, ImmOp, MajOp, 0> ;
- }
-}
-
-let accessSize = ByteAccess in
-defm S2_storerb : ST_GP<"memb", "STrib", u16_0Imm, 0b00>, NewValueRel;
-
-let accessSize = HalfWordAccess in
-defm S2_storerh : ST_GP<"memh", "STrih", u16_1Imm, 0b01>, NewValueRel;
-
-let accessSize = WordAccess in
-defm S2_storeri : ST_GP<"memw", "STriw", u16_2Imm, 0b10>, NewValueRel;
-
-let isNVStorable = 0, accessSize = DoubleWordAccess in
-def S2_storerdgp : T_StoreGP <"memd", "STrid", DoubleRegs,
- u16_3Imm, 0b11>, PredNewRel;
-
-let isNVStorable = 0, accessSize = HalfWordAccess in
-def S2_storerfgp : T_StoreGP <"memh", "STrif", IntRegs,
- u16_1Imm, 0b01, 1>, PredNewRel;
-
-//===----------------------------------------------------------------------===//
-// Template class for non predicated load instructions with
-// absolute addressing mode.
-//===----------------------------------------------------------------------===//
-let isPredicable = 1, hasSideEffects = 0 in
-class T_LoadAbsGP <string mnemonic, RegisterClass RC, Operand ImmOp,
- bits<3> MajOp, bit isAbs>
- : LDInst <(outs RC:$dst), (ins ImmOp:$addr),
- "$dst = " # mnemonic # "(" # !if(isAbs, "", "gp+") # "#$addr)",
- [], "", V2LDST_tc_ld_SLOT01> {
- bits<5> dst;
- bits<19> addr;
- bits<16> offsetBits;
-
- string ImmOpStr = !cast<string>(ImmOp);
- let offsetBits = !if (!eq(ImmOpStr, "u16_3Imm"), addr{18-3},
- !if (!eq(ImmOpStr, "u16_2Imm"), addr{17-2},
- !if (!eq(ImmOpStr, "u16_1Imm"), addr{16-1},
- /* u16_0Imm */ addr{15-0})));
- let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19,
- !if (!eq(ImmOpStr, "u16_2Imm"), 18,
- !if (!eq(ImmOpStr, "u16_1Imm"), 17,
- /* u16_0Imm */ 16)));
- let opExtentAlign = !if (!eq(ImmOpStr, "u16_3Imm"), 3,
- !if (!eq(ImmOpStr, "u16_2Imm"), 2,
- !if (!eq(ImmOpStr, "u16_1Imm"), 1,
- /* u16_0Imm */ 0)));
-
- let IClass = 0b0100;
-
- let Inst{27} = 0b1;
- let Inst{26-25} = offsetBits{15-14};
- let Inst{24} = 0b1;
- let Inst{23-21} = MajOp;
- let Inst{20-16} = offsetBits{13-9};
- let Inst{13-5} = offsetBits{8-0};
- let Inst{4-0} = dst;
- }
-
-class T_LoadAbs <string mnemonic, RegisterClass RC, Operand ImmOp,
- bits<3> MajOp>
- : T_LoadAbsGP <mnemonic, RC, u32_0MustExt, MajOp, 1>, AddrModeRel {
-
- string ImmOpStr = !cast<string>(ImmOp);
- let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19,
- !if (!eq(ImmOpStr, "u16_2Imm"), 18,
- !if (!eq(ImmOpStr, "u16_1Imm"), 17,
- /* u16_0Imm */ 16)));
-
- let opExtentAlign = !if (!eq(ImmOpStr, "u16_3Imm"), 3,
- !if (!eq(ImmOpStr, "u16_2Imm"), 2,
- !if (!eq(ImmOpStr, "u16_1Imm"), 1,
- /* u16_0Imm */ 0)));
- }
-
-//===----------------------------------------------------------------------===//
-// Template class for predicated load instructions with
-// absolute addressing mode.
-//===----------------------------------------------------------------------===//
-let isPredicated = 1, hasSideEffects = 0, hasNewValue = 1, opExtentBits = 6,
- opExtendable = 2 in
-class T_LoadAbs_Pred <string mnemonic, RegisterClass RC, bits<3> MajOp,
- bit isPredNot, bit isPredNew>
- : LDInst <(outs RC:$dst), (ins PredRegs:$src1, u32_0MustExt:$absaddr),
- !if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
- ") ")#"$dst = "#mnemonic#"(#$absaddr)">, AddrModeRel {
- bits<5> dst;
- bits<2> src1;
- bits<6> absaddr;
-
- let isPredicatedNew = isPredNew;
- let isPredicatedFalse = isPredNot;
- let hasNewValue = !if (!eq(!cast<string>(RC), "DoubleRegs"), 0, 1);
-
- let IClass = 0b1001;
-
- let Inst{27-24} = 0b1111;
- let Inst{23-21} = MajOp;
- let Inst{20-16} = absaddr{5-1};
- let Inst{13} = 0b1;
- let Inst{12} = isPredNew;
- let Inst{11} = isPredNot;
- let Inst{10-9} = src1;
- let Inst{8} = absaddr{0};
- let Inst{7} = 0b1;
- let Inst{4-0} = dst;
- }
-
-//===----------------------------------------------------------------------===//
-// Multiclass for the load instructions with absolute addressing mode.
-//===----------------------------------------------------------------------===//
-multiclass LD_Abs_Pred<string mnemonic, RegisterClass RC, bits<3> MajOp,
- bit PredNot> {
- def _abs : T_LoadAbs_Pred <mnemonic, RC, MajOp, PredNot, 0>;
- // Predicate new
- def new_abs : T_LoadAbs_Pred <mnemonic, RC, MajOp, PredNot, 1>;
-}
-
-let addrMode = Absolute, isExtended = 1 in
-multiclass LD_Abs<string mnemonic, string CextOp, RegisterClass RC,
- Operand ImmOp, bits<3> MajOp> {
- let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
- let opExtendable = 1, isPredicable = 1 in
- def PS_#NAME#abs: T_LoadAbs <mnemonic, RC, ImmOp, MajOp>;
-
- // Predicated
- defm L4_p#NAME#t : LD_Abs_Pred<mnemonic, RC, MajOp, 0>;
- defm L4_p#NAME#f : LD_Abs_Pred<mnemonic, RC, MajOp, 1>;
- }
-}
-
-let accessSize = ByteAccess, hasNewValue = 1 in {
- defm loadrb : LD_Abs<"memb", "LDrib", IntRegs, u16_0Imm, 0b000>;
- defm loadrub : LD_Abs<"memub", "LDriub", IntRegs, u16_0Imm, 0b001>;
-}
-
-let accessSize = HalfWordAccess, hasNewValue = 1 in {
- defm loadrh : LD_Abs<"memh", "LDrih", IntRegs, u16_1Imm, 0b010>;
- defm loadruh : LD_Abs<"memuh", "LDriuh", IntRegs, u16_1Imm, 0b011>;
-}
-
-let accessSize = WordAccess, hasNewValue = 1 in
-defm loadri : LD_Abs<"memw", "LDriw", IntRegs, u16_2Imm, 0b100>;
-
-let accessSize = DoubleWordAccess in
-defm loadrd : LD_Abs<"memd", "LDrid", DoubleRegs, u16_3Imm, 0b110>;
-
-//===----------------------------------------------------------------------===//
-// multiclass for load instructions with GP-relative addressing mode.
-// Rx=mem[bhwd](##global)
-// Once predicated, these instructions map to absolute addressing mode.
-// if ([!]Pv[.new]) Rx=mem[bhwd](##global)
-//===----------------------------------------------------------------------===//
-
-let isAsmParserOnly = 1, Uses = [GP] in
-class T_LoadGP <string mnemonic, string BaseOp, RegisterClass RC, Operand ImmOp,
- bits<3> MajOp>
- : T_LoadAbsGP <mnemonic, RC, ImmOp, MajOp, 0>, PredNewRel {
- let BaseOpcode = BaseOp#_abs;
- }
-
-let accessSize = ByteAccess, hasNewValue = 1 in {
- def L2_loadrbgp : T_LoadGP<"memb", "LDrib", IntRegs, u16_0Imm, 0b000>;
- def L2_loadrubgp : T_LoadGP<"memub", "LDriub", IntRegs, u16_0Imm, 0b001>;
-}
-
-let accessSize = HalfWordAccess, hasNewValue = 1 in {
- def L2_loadrhgp : T_LoadGP<"memh", "LDrih", IntRegs, u16_1Imm, 0b010>;
- def L2_loadruhgp : T_LoadGP<"memuh", "LDriuh", IntRegs, u16_1Imm, 0b011>;
-}
-
-let accessSize = WordAccess, hasNewValue = 1 in
-def L2_loadrigp : T_LoadGP<"memw", "LDriw", IntRegs, u16_2Imm, 0b100>;
-
-let accessSize = DoubleWordAccess in
-def L2_loadrdgp : T_LoadGP<"memd", "LDrid", DoubleRegs, u16_3Imm, 0b110>;
-
-//===----------------------------------------------------------------------===//
-// :raw for of boundscheck:hi:lo insns
-//===----------------------------------------------------------------------===//
-
-// A4_boundscheck_lo: Detect if a register is within bounds.
-let hasSideEffects = 0 in
-def A4_boundscheck_lo: ALU64Inst <
- (outs PredRegs:$Pd),
- (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
- "$Pd = boundscheck($Rss, $Rtt):raw:lo"> {
- bits<2> Pd;
- bits<5> Rss;
- bits<5> Rtt;
-
- let IClass = 0b1101;
-
- let Inst{27-23} = 0b00100;
- let Inst{13} = 0b1;
- let Inst{7-5} = 0b100;
- let Inst{1-0} = Pd;
- let Inst{20-16} = Rss;
- let Inst{12-8} = Rtt;
- }
-
-// A4_boundscheck_hi: Detect if a register is within bounds.
-let hasSideEffects = 0 in
-def A4_boundscheck_hi: ALU64Inst <
- (outs PredRegs:$Pd),
- (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
- "$Pd = boundscheck($Rss, $Rtt):raw:hi"> {
- bits<2> Pd;
- bits<5> Rss;
- bits<5> Rtt;
-
- let IClass = 0b1101;
-
- let Inst{27-23} = 0b00100;
- let Inst{13} = 0b1;
- let Inst{7-5} = 0b101;
- let Inst{1-0} = Pd;
- let Inst{20-16} = Rss;
- let Inst{12-8} = Rtt;
- }
-
-let hasSideEffects = 0, isAsmParserOnly = 1 in
-def A4_boundscheck : MInst <
- (outs PredRegs:$Pd), (ins IntRegs:$Rs, DoubleRegs:$Rtt),
- "$Pd=boundscheck($Rs,$Rtt)">;
-
-// A4_tlbmatch: Detect if a VA/ASID matches a TLB entry.
-let isPredicateLate = 1, hasSideEffects = 0 in
-def A4_tlbmatch : ALU64Inst<(outs PredRegs:$Pd),
- (ins DoubleRegs:$Rs, IntRegs:$Rt),
- "$Pd = tlbmatch($Rs, $Rt)",
- [], "", ALU64_tc_2early_SLOT23> {
- bits<2> Pd;
- bits<5> Rs;
- bits<5> Rt;
-
- let IClass = 0b1101;
- let Inst{27-23} = 0b00100;
- let Inst{20-16} = Rs;
- let Inst{13} = 0b1;
- let Inst{12-8} = Rt;
- let Inst{7-5} = 0b011;
- let Inst{1-0} = Pd;
- }
-
-// Use LD0Inst for dcfetch, but set "mayLoad" to 0 because this doesn't
-// really do a load.
-let hasSideEffects = 1, mayLoad = 0 in
-def Y2_dcfetchbo : LD0Inst<(outs), (ins IntRegs:$Rs, u11_3Imm:$u11_3),
- "dcfetch($Rs + #$u11_3)",
- [], "", LD_tc_ld_SLOT0> {
- bits<5> Rs;
- bits<14> u11_3;
-
- let IClass = 0b1001;
- let Inst{27-21} = 0b0100000;
- let Inst{20-16} = Rs;
- let Inst{13} = 0b0;
- let Inst{10-0} = u11_3{13-3};
-}
-
-
-//===----------------------------------------------------------------------===//
-// Compound instructions
-//===----------------------------------------------------------------------===//
-
-let isBranch = 1, hasSideEffects = 0, isExtentSigned = 1,
- isPredicated = 1, isPredicatedNew = 1, isExtendable = 1,
- opExtentBits = 11, opExtentAlign = 2, opExtendable = 1,
- isTerminator = 1 in
-class CJInst_tstbit_R0<string px, bit np, string tnt>
- : InstHexagon<(outs), (ins IntRegs:$Rs, brtarget:$r9_2),
- ""#px#" = tstbit($Rs, #0); if ("
- #!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2",
- [], "", COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, OpcodeHexagon {
- bits<4> Rs;
- bits<11> r9_2;
-
- // np: !p[01]
- let isPredicatedFalse = np;
- // tnt: Taken/Not Taken
- let isBrTaken = !if (!eq(tnt, "t"), "true", "false");
- let isTaken = !if (!eq(tnt, "t"), 1, 0);
-
- let IClass = 0b0001;
- let Inst{27-26} = 0b00;
- let Inst{25} = !if (!eq(px, "!p1"), 1,
- !if (!eq(px, "p1"), 1, 0));
- let Inst{24-23} = 0b11;
- let Inst{22} = np;
- let Inst{21-20} = r9_2{10-9};
- let Inst{19-16} = Rs;
- let Inst{13} = !if (!eq(tnt, "t"), 1, 0);
- let Inst{9-8} = 0b11;
- let Inst{7-1} = r9_2{8-2};
-}
-
-let Defs = [PC, P0], Uses = [P0] in {
- def J4_tstbit0_tp0_jump_nt : CJInst_tstbit_R0<"p0", 0, "nt">;
- def J4_tstbit0_tp0_jump_t : CJInst_tstbit_R0<"p0", 0, "t">;
- def J4_tstbit0_fp0_jump_nt : CJInst_tstbit_R0<"p0", 1, "nt">;
- def J4_tstbit0_fp0_jump_t : CJInst_tstbit_R0<"p0", 1, "t">;
-}
-
-let Defs = [PC, P1], Uses = [P1] in {
- def J4_tstbit0_tp1_jump_nt : CJInst_tstbit_R0<"p1", 0, "nt">;
- def J4_tstbit0_tp1_jump_t : CJInst_tstbit_R0<"p1", 0, "t">;
- def J4_tstbit0_fp1_jump_nt : CJInst_tstbit_R0<"p1", 1, "nt">;
- def J4_tstbit0_fp1_jump_t : CJInst_tstbit_R0<"p1", 1, "t">;
-}
-
-
-let isBranch = 1, hasSideEffects = 0,
- isExtentSigned = 1, isPredicated = 1, isPredicatedNew = 1,
- isExtendable = 1, opExtentBits = 11, opExtentAlign = 2,
- opExtendable = 2, isTerminator = 1 in
-class CJInst_RR<string px, string op, bit np, string tnt>
- : InstHexagon<(outs), (ins IntRegs:$Rs, IntRegs:$Rt, brtarget:$r9_2),
- ""#px#" = cmp."#op#"($Rs, $Rt); if ("
- #!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2",
- [], "", COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, OpcodeHexagon {
- bits<4> Rs;
- bits<4> Rt;
- bits<11> r9_2;
-
- // np: !p[01]
- let isPredicatedFalse = np;
- // tnt: Taken/Not Taken
- let isBrTaken = !if (!eq(tnt, "t"), "true", "false");
- let isTaken = !if (!eq(tnt, "t"), 1, 0);
-
- let IClass = 0b0001;
- let Inst{27-23} = !if (!eq(op, "eq"), 0b01000,
- !if (!eq(op, "gt"), 0b01001,
- !if (!eq(op, "gtu"), 0b01010, 0)));
- let Inst{22} = np;
- let Inst{21-20} = r9_2{10-9};
- let Inst{19-16} = Rs;
- let Inst{13} = !if (!eq(tnt, "t"), 1, 0);
- // px: Predicate reg 0/1
- let Inst{12} = !if (!eq(px, "!p1"), 1,
- !if (!eq(px, "p1"), 1, 0));
- let Inst{11-8} = Rt;
- let Inst{7-1} = r9_2{8-2};
-}
-
-// P[10] taken/not taken.
-multiclass T_tnt_CJInst_RR<string op, bit np> {
- let Defs = [PC, P0], Uses = [P0] in {
- def NAME#p0_jump_nt : CJInst_RR<"p0", op, np, "nt">;
- def NAME#p0_jump_t : CJInst_RR<"p0", op, np, "t">;
- }
- let Defs = [PC, P1], Uses = [P1] in {
- def NAME#p1_jump_nt : CJInst_RR<"p1", op, np, "nt">;
- def NAME#p1_jump_t : CJInst_RR<"p1", op, np, "t">;
- }
-}
-// Predicate / !Predicate
-multiclass T_pnp_CJInst_RR<string op>{
- defm J4_cmp#NAME#_t : T_tnt_CJInst_RR<op, 0>;
- defm J4_cmp#NAME#_f : T_tnt_CJInst_RR<op, 1>;
-}
-// TypeCJ Instructions compare RR and jump
-defm eq : T_pnp_CJInst_RR<"eq">;
-defm gt : T_pnp_CJInst_RR<"gt">;
-defm gtu : T_pnp_CJInst_RR<"gtu">;
-
-let isBranch = 1, hasSideEffects = 0, isExtentSigned = 1,
- isPredicated = 1, isPredicatedNew = 1, isExtendable = 1, opExtentBits = 11,
- opExtentAlign = 2, opExtendable = 2, isTerminator = 1 in
-class CJInst_RU5<string px, string op, bit np, string tnt>
- : InstHexagon<(outs), (ins IntRegs:$Rs, u5_0Imm:$U5, brtarget:$r9_2),
- ""#px#" = cmp."#op#"($Rs, #$U5); if ("
- #!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2",
- [], "", COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, OpcodeHexagon {
- bits<4> Rs;
- bits<5> U5;
- bits<11> r9_2;
-
- // np: !p[01]
- let isPredicatedFalse = np;
- // tnt: Taken/Not Taken
- let isBrTaken = !if (!eq(tnt, "t"), "true", "false");
- let isTaken = !if (!eq(tnt, "t"), 1, 0);
-
- let IClass = 0b0001;
- let Inst{27-26} = 0b00;
- // px: Predicate reg 0/1
- let Inst{25} = !if (!eq(px, "!p1"), 1,
- !if (!eq(px, "p1"), 1, 0));
- let Inst{24-23} = !if (!eq(op, "eq"), 0b00,
- !if (!eq(op, "gt"), 0b01,
- !if (!eq(op, "gtu"), 0b10, 0)));
- let Inst{22} = np;
- let Inst{21-20} = r9_2{10-9};
- let Inst{19-16} = Rs;
- let Inst{13} = !if (!eq(tnt, "t"), 1, 0);
- let Inst{12-8} = U5;
- let Inst{7-1} = r9_2{8-2};
-}
-// P[10] taken/not taken.
-multiclass T_tnt_CJInst_RU5<string op, bit np> {
- let Defs = [PC, P0], Uses = [P0] in {
- def NAME#p0_jump_nt : CJInst_RU5<"p0", op, np, "nt">;
- def NAME#p0_jump_t : CJInst_RU5<"p0", op, np, "t">;
- }
- let Defs = [PC, P1], Uses = [P1] in {
- def NAME#p1_jump_nt : CJInst_RU5<"p1", op, np, "nt">;
- def NAME#p1_jump_t : CJInst_RU5<"p1", op, np, "t">;
- }
-}
-// Predicate / !Predicate
-multiclass T_pnp_CJInst_RU5<string op>{
- defm J4_cmp#NAME#i_t : T_tnt_CJInst_RU5<op, 0>;
- defm J4_cmp#NAME#i_f : T_tnt_CJInst_RU5<op, 1>;
-}
-// TypeCJ Instructions compare RI and jump
-defm eq : T_pnp_CJInst_RU5<"eq">;
-defm gt : T_pnp_CJInst_RU5<"gt">;
-defm gtu : T_pnp_CJInst_RU5<"gtu">;
-
-let isBranch = 1, hasSideEffects = 0, isExtentSigned = 1,
- isPredicated = 1, isPredicatedFalse = 1, isPredicatedNew = 1,
- isExtendable = 1, opExtentBits = 11, opExtentAlign = 2, opExtendable = 2,
- isTerminator = 1 in
-class CJInst_Rn1<string px, string op, bit np, string tnt>
- : InstHexagon<(outs), (ins IntRegs:$Rs, n1Const:$n1, brtarget:$r9_2),
- ""#px#" = cmp."#op#"($Rs,#$n1); if ("
- #!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2",
- [], "", COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, OpcodeHexagon {
- bits<4> Rs;
- bits<11> r9_2;
-
- // np: !p[01]
- let isPredicatedFalse = np;
- // tnt: Taken/Not Taken
- let isBrTaken = !if (!eq(tnt, "t"), "true", "false");
- let isTaken = !if (!eq(tnt, "t"), 1, 0);
-
- let IClass = 0b0001;
- let Inst{27-26} = 0b00;
- let Inst{25} = !if (!eq(px, "!p1"), 1,
- !if (!eq(px, "p1"), 1, 0));
-
- let Inst{24-23} = 0b11;
- let Inst{22} = np;
- let Inst{21-20} = r9_2{10-9};
- let Inst{19-16} = Rs;
- let Inst{13} = !if (!eq(tnt, "t"), 1, 0);
- let Inst{9-8} = !if (!eq(op, "eq"), 0b00,
- !if (!eq(op, "gt"), 0b01, 0));
- let Inst{7-1} = r9_2{8-2};
-}
-
-// P[10] taken/not taken.
-multiclass T_tnt_CJInst_Rn1<string op, bit np> {
- let Defs = [PC, P0], Uses = [P0] in {
- def NAME#p0_jump_nt : CJInst_Rn1<"p0", op, np, "nt">;
- def NAME#p0_jump_t : CJInst_Rn1<"p0", op, np, "t">;
- }
- let Defs = [PC, P1], Uses = [P1] in {
- def NAME#p1_jump_nt : CJInst_Rn1<"p1", op, np, "nt">;
- def NAME#p1_jump_t : CJInst_Rn1<"p1", op, np, "t">;
- }
-}
-// Predicate / !Predicate
-multiclass T_pnp_CJInst_Rn1<string op>{
- defm J4_cmp#NAME#n1_t : T_tnt_CJInst_Rn1<op, 0>;
- defm J4_cmp#NAME#n1_f : T_tnt_CJInst_Rn1<op, 1>;
-}
-// TypeCJ Instructions compare -1 and jump
-defm eq : T_pnp_CJInst_Rn1<"eq">;
-defm gt : T_pnp_CJInst_Rn1<"gt">;
-
-// J4_jumpseti: Direct unconditional jump and set register to immediate.
-let Defs = [PC], isBranch = 1, hasSideEffects = 0, hasNewValue = 1,
- isExtentSigned = 1, opNewValue = 0, isExtendable = 1, opExtentBits = 11,
- opExtentAlign = 2, opExtendable = 2 in
-def J4_jumpseti: CJInst_JMPSET <
- (outs IntRegs:$Rd),
- (ins u6_0Imm:$U6, brtarget:$r9_2),
- "$Rd = #$U6 ; jump $r9_2"> {
- bits<4> Rd;
- bits<6> U6;
- bits<11> r9_2;
-
- let IClass = 0b0001;
- let Inst{27-24} = 0b0110;
- let Inst{21-20} = r9_2{10-9};
- let Inst{19-16} = Rd;
- let Inst{13-8} = U6;
- let Inst{7-1} = r9_2{8-2};
- }
-
-// J4_jumpsetr: Direct unconditional jump and transfer register.
-let Defs = [PC], isBranch = 1, hasSideEffects = 0, hasNewValue = 1,
- isExtentSigned = 1, opNewValue = 0, isExtendable = 1, opExtentBits = 11,
- opExtentAlign = 2, opExtendable = 2 in
-def J4_jumpsetr: CJInst_JMPSET <
- (outs IntRegs:$Rd),
- (ins IntRegs:$Rs, brtarget:$r9_2),
- "$Rd = $Rs ; jump $r9_2"> {
- bits<4> Rd;
- bits<4> Rs;
- bits<11> r9_2;
-
- let IClass = 0b0001;
- let Inst{27-24} = 0b0111;
- let Inst{21-20} = r9_2{10-9};
- let Inst{11-8} = Rd;
- let Inst{19-16} = Rs;
- let Inst{7-1} = r9_2{8-2};
- }
-
-// Duplex instructions
-//===----------------------------------------------------------------------===//
-include "HexagonIsetDx.td"
Removed: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV5.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV5.td?rev=294752&view=auto
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV5.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV5.td (removed)
@@ -1,497 +0,0 @@
-//=- HexagonInstrInfoV5.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file describes the Hexagon V5 instructions in TableGen format.
-//
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// XTYPE/MPY
-//===----------------------------------------------------------------------===//
-
- //Rdd[+]=vrmpybsu(Rss,Rtt)
-let Predicates = [HasV5T] in {
- def M5_vrmpybsu: T_XTYPE_Vect<"vrmpybsu", 0b110, 0b001, 0>;
- def M5_vrmacbsu: T_XTYPE_Vect_acc<"vrmpybsu", 0b110, 0b001, 0>;
-
- //Rdd[+]=vrmpybu(Rss,Rtt)
- def M5_vrmpybuu: T_XTYPE_Vect<"vrmpybu", 0b100, 0b001, 0>;
- def M5_vrmacbuu: T_XTYPE_Vect_acc<"vrmpybu", 0b100, 0b001, 0>;
-
- def M5_vdmpybsu: T_M2_vmpy<"vdmpybsu", 0b101, 0b001, 0, 0, 1>;
- def M5_vdmacbsu: T_M2_vmpy_acc_sat <"vdmpybsu", 0b001, 0b001, 0, 0>;
-}
-
-// Vector multiply bytes
-// Rdd=vmpyb[s]u(Rs,Rt)
-let Predicates = [HasV5T] in {
- def M5_vmpybsu: T_XTYPE_mpy64 <"vmpybsu", 0b010, 0b001, 0, 0, 0>;
- def M5_vmpybuu: T_XTYPE_mpy64 <"vmpybu", 0b100, 0b001, 0, 0, 0>;
-
- // Rxx+=vmpyb[s]u(Rs,Rt)
- def M5_vmacbsu: T_XTYPE_mpy64_acc <"vmpybsu", "+", 0b110, 0b001, 0, 0, 0>;
- def M5_vmacbuu: T_XTYPE_mpy64_acc <"vmpybu", "+", 0b100, 0b001, 0, 0, 0>;
-
- // Rd=vaddhub(Rss,Rtt):sat
- let hasNewValue = 1, opNewValue = 0 in
- def A5_vaddhubs: T_S3op_1 <"vaddhub", IntRegs, 0b01, 0b001, 0, 1>;
-}
-
-def S2_asr_i_p_rnd : S_2OpInstImm<"asr", 0b110, 0b111, u6_0Imm, [], 1>,
- Requires<[HasV5T]> {
- bits<6> src2;
- let Inst{13-8} = src2;
-}
-
-let isAsmParserOnly = 1 in
-def S2_asr_i_p_rnd_goodsyntax
- : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6_0Imm:$src2),
- "$dst = asrrnd($src1, #$src2)">;
-
-def C4_fastcorner9 : T_LOGICAL_2OP<"fastcorner9", 0b000, 0, 0>,
- Requires<[HasV5T]> {
- let Inst{13,7,4} = 0b111;
-}
-
-def C4_fastcorner9_not : T_LOGICAL_2OP<"!fastcorner9", 0b000, 0, 0>,
- Requires<[HasV5T]> {
- let Inst{20,13,7,4} = 0b1111;
-}
-
-let hasNewValue = 1, validSubTargets = HasV5SubT in
-def S5_popcountp : ALU64_rr<(outs IntRegs:$Rd), (ins DoubleRegs:$Rss),
- "$Rd = popcount($Rss)", [], "", S_2op_tc_2_SLOT23>,
- Requires<[HasV5T]> {
- bits<5> Rd;
- bits<5> Rss;
-
- let IClass = 0b1000;
-
- let Inst{27-21} = 0b1000011;
- let Inst{7-5} = 0b011;
- let Inst{4-0} = Rd;
- let Inst{20-16} = Rss;
- }
-
-let isFP = 1, hasNewValue = 1, opNewValue = 0 in
-class T_MInstFloat <string mnemonic, bits<3> MajOp, bits<3> MinOp>
- : MInst<(outs IntRegs:$Rd),
- (ins IntRegs:$Rs, IntRegs:$Rt),
- "$Rd = "#mnemonic#"($Rs, $Rt)", [],
- "" , M_tc_3or4x_SLOT23 > ,
- Requires<[HasV5T]> {
- bits<5> Rd;
- bits<5> Rs;
- bits<5> Rt;
-
- let IClass = 0b1110;
-
- let Inst{27-24} = 0b1011;
- let Inst{23-21} = MajOp;
- let Inst{20-16} = Rs;
- let Inst{13} = 0b0;
- let Inst{12-8} = Rt;
- let Inst{7-5} = MinOp;
- let Inst{4-0} = Rd;
- }
-
-let isCommutable = 1 in {
- def F2_sfadd : T_MInstFloat < "sfadd", 0b000, 0b000>;
- def F2_sfmpy : T_MInstFloat < "sfmpy", 0b010, 0b000>;
-}
-
-def F2_sfsub : T_MInstFloat < "sfsub", 0b000, 0b001>;
-
-let Itinerary = M_tc_3x_SLOT23 in {
- def F2_sfmax : T_MInstFloat < "sfmax", 0b100, 0b000>;
- def F2_sfmin : T_MInstFloat < "sfmin", 0b100, 0b001>;
-}
-
-let Itinerary = M_tc_3or4x_SLOT23 in {
-def F2_sffixupn : T_MInstFloat < "sffixupn", 0b110, 0b000>;
-def F2_sffixupd : T_MInstFloat < "sffixupd", 0b110, 0b001>;
-}
-
-// F2_sfrecipa: Reciprocal approximation for division.
-let Uses = [USR], isPredicateLate = 1, isFP = 1,
- hasSideEffects = 0, hasNewValue = 1, Itinerary = M_tc_3or4x_SLOT23 in
-def F2_sfrecipa: MInst <
- (outs IntRegs:$Rd, PredRegs:$Pe),
- (ins IntRegs:$Rs, IntRegs:$Rt),
- "$Rd, $Pe = sfrecipa($Rs, $Rt)">,
- Requires<[HasV5T]> {
- bits<5> Rd;
- bits<2> Pe;
- bits<5> Rs;
- bits<5> Rt;
-
- let IClass = 0b1110;
- let Inst{27-21} = 0b1011111;
- let Inst{20-16} = Rs;
- let Inst{13} = 0b0;
- let Inst{12-8} = Rt;
- let Inst{7} = 0b1;
- let Inst{6-5} = Pe;
- let Inst{4-0} = Rd;
- }
-
-// F2_dfcmpeq: Floating point compare for equal.
-let Uses = [USR], isCompare = 1, isFP = 1 in
-class T_fcmp <string mnemonic, RegisterClass RC, bits<3> MinOp,
- list<dag> pattern = [] >
- : ALU64Inst <(outs PredRegs:$dst), (ins RC:$src1, RC:$src2),
- "$dst = "#mnemonic#"($src1, $src2)", pattern,
- "" , ALU64_tc_2early_SLOT23 > ,
- Requires<[HasV5T]> {
- bits<2> dst;
- bits<5> src1;
- bits<5> src2;
-
- let IClass = 0b1101;
-
- let Inst{27-21} = 0b0010111;
- let Inst{20-16} = src1;
- let Inst{12-8} = src2;
- let Inst{7-5} = MinOp;
- let Inst{1-0} = dst;
- }
-
-class T_fcmp64 <string mnemonic, PatFrag OpNode, bits<3> MinOp>
- : T_fcmp <mnemonic, DoubleRegs, MinOp, []> {
- let IClass = 0b1101;
- let Inst{27-21} = 0b0010111;
-}
-
-class T_fcmp32 <string mnemonic, PatFrag OpNode, bits<3> MinOp>
- : T_fcmp <mnemonic, IntRegs, MinOp, []> {
- let IClass = 0b1100;
- let Inst{27-21} = 0b0111111;
-}
-
-def F2_dfcmpeq : T_fcmp64<"dfcmp.eq", setoeq, 0b000>;
-def F2_dfcmpgt : T_fcmp64<"dfcmp.gt", setogt, 0b001>;
-def F2_dfcmpge : T_fcmp64<"dfcmp.ge", setoge, 0b010>;
-def F2_dfcmpuo : T_fcmp64<"dfcmp.uo", setuo, 0b011>;
-
-def F2_sfcmpge : T_fcmp32<"sfcmp.ge", setoge, 0b000>;
-def F2_sfcmpuo : T_fcmp32<"sfcmp.uo", setuo, 0b001>;
-def F2_sfcmpeq : T_fcmp32<"sfcmp.eq", setoeq, 0b011>;
-def F2_sfcmpgt : T_fcmp32<"sfcmp.gt", setogt, 0b100>;
-
-// F2 convert template classes:
-let Uses = [USR], isFP = 1 in
-class F2_RDD_RSS_CONVERT<string mnemonic, bits<3> MinOp,
- string chop ="">
- : SInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss),
- "$Rdd = "#mnemonic#"($Rss)"#chop, [], "",
- S_2op_tc_3or4x_SLOT23> {
- bits<5> Rdd;
- bits<5> Rss;
-
- let IClass = 0b1000;
-
- let Inst{27-21} = 0b0000111;
- let Inst{20-16} = Rss;
- let Inst{7-5} = MinOp;
- let Inst{4-0} = Rdd;
- }
-
-let Uses = [USR], isFP = 1 in
-class F2_RDD_RS_CONVERT<string mnemonic, bits<3> MinOp,
- string chop ="">
- : SInst <(outs DoubleRegs:$Rdd), (ins IntRegs:$Rs),
- "$Rdd = "#mnemonic#"($Rs)"#chop, [], "",
- S_2op_tc_3or4x_SLOT23> {
- bits<5> Rdd;
- bits<5> Rs;
-
- let IClass = 0b1000;
-
- let Inst{27-21} = 0b0100100;
- let Inst{20-16} = Rs;
- let Inst{7-5} = MinOp;
- let Inst{4-0} = Rdd;
- }
-
-let Uses = [USR], isFP = 1, hasNewValue = 1 in
-class F2_RD_RSS_CONVERT<string mnemonic, bits<3> MinOp,
- string chop ="">
- : SInst <(outs IntRegs:$Rd), (ins DoubleRegs:$Rss),
- "$Rd = "#mnemonic#"($Rss)"#chop, [], "",
- S_2op_tc_3or4x_SLOT23> {
- bits<5> Rd;
- bits<5> Rss;
-
- let IClass = 0b1000;
-
- let Inst{27-24} = 0b1000;
- let Inst{23-21} = MinOp;
- let Inst{20-16} = Rss;
- let Inst{7-5} = 0b001;
- let Inst{4-0} = Rd;
- }
-
-let Uses = [USR], isFP = 1, hasNewValue = 1 in
-class F2_RD_RS_CONVERT<string mnemonic, bits<3> MajOp, bits<3> MinOp,
- string chop ="">
- : SInst <(outs IntRegs:$Rd), (ins IntRegs:$Rs),
- "$Rd = "#mnemonic#"($Rs)"#chop, [], "",
- S_2op_tc_3or4x_SLOT23> {
- bits<5> Rd;
- bits<5> Rs;
-
- let IClass = 0b1000;
-
- let Inst{27-24} = 0b1011;
- let Inst{23-21} = MajOp;
- let Inst{20-16} = Rs;
- let Inst{7-5} = MinOp;
- let Inst{4-0} = Rd;
- }
-
-// Convert single precision to double precision and vice-versa.
-def F2_conv_sf2df : F2_RDD_RS_CONVERT <"convert_sf2df", 0b000>;
-def F2_conv_df2sf : F2_RD_RSS_CONVERT <"convert_df2sf", 0b000>;
-
-// Convert Integer to Floating Point.
-def F2_conv_d2sf : F2_RD_RSS_CONVERT <"convert_d2sf", 0b010>;
-def F2_conv_ud2sf : F2_RD_RSS_CONVERT <"convert_ud2sf", 0b001>;
-def F2_conv_uw2sf : F2_RD_RS_CONVERT <"convert_uw2sf", 0b001, 0b000>;
-def F2_conv_w2sf : F2_RD_RS_CONVERT <"convert_w2sf", 0b010, 0b000>;
-def F2_conv_d2df : F2_RDD_RSS_CONVERT <"convert_d2df", 0b011>;
-def F2_conv_ud2df : F2_RDD_RSS_CONVERT <"convert_ud2df", 0b010>;
-def F2_conv_uw2df : F2_RDD_RS_CONVERT <"convert_uw2df", 0b001>;
-def F2_conv_w2df : F2_RDD_RS_CONVERT <"convert_w2df", 0b010>;
-
-// Convert Floating Point to Integer.
-def F2_conv_df2uw_chop : F2_RD_RSS_CONVERT <"convert_df2uw", 0b101, ":chop">;
-def F2_conv_df2w_chop : F2_RD_RSS_CONVERT <"convert_df2w", 0b111, ":chop">;
-def F2_conv_sf2uw_chop : F2_RD_RS_CONVERT <"convert_sf2uw", 0b011, 0b001,
- ":chop">;
-def F2_conv_sf2w_chop : F2_RD_RS_CONVERT <"convert_sf2w", 0b100, 0b001,
- ":chop">;
-def F2_conv_df2d_chop : F2_RDD_RSS_CONVERT <"convert_df2d", 0b110, ":chop">;
-def F2_conv_df2ud_chop : F2_RDD_RSS_CONVERT <"convert_df2ud", 0b111, ":chop">;
-def F2_conv_sf2d_chop : F2_RDD_RS_CONVERT <"convert_sf2d", 0b110, ":chop">;
-def F2_conv_sf2ud_chop : F2_RDD_RS_CONVERT <"convert_sf2ud", 0b101, ":chop">;
-
-// Convert Floating Point to Integer: non-chopped.
-let AddedComplexity = 20, Predicates = [HasV5T] in {
- def F2_conv_df2d : F2_RDD_RSS_CONVERT <"convert_df2d", 0b000>;
- def F2_conv_df2ud : F2_RDD_RSS_CONVERT <"convert_df2ud", 0b001>;
- def F2_conv_sf2ud : F2_RDD_RS_CONVERT <"convert_sf2ud", 0b011>;
- def F2_conv_sf2d : F2_RDD_RS_CONVERT <"convert_sf2d", 0b100>;
- def F2_conv_df2uw : F2_RD_RSS_CONVERT <"convert_df2uw", 0b011>;
- def F2_conv_df2w : F2_RD_RSS_CONVERT <"convert_df2w", 0b100>;
- def F2_conv_sf2uw : F2_RD_RS_CONVERT <"convert_sf2uw", 0b011, 0b000>;
- def F2_conv_sf2w : F2_RD_RS_CONVERT <"convert_sf2w", 0b100, 0b000>;
-}
-
-// Fix up radicand.
-let Uses = [USR], isFP = 1, hasNewValue = 1 in
-def F2_sffixupr: SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs),
- "$Rd = sffixupr($Rs)",
- [], "" , S_2op_tc_3or4x_SLOT23>, Requires<[HasV5T]> {
- bits<5> Rd;
- bits<5> Rs;
-
- let IClass = 0b1000;
-
- let Inst{27-21} = 0b1011101;
- let Inst{20-16} = Rs;
- let Inst{7-5} = 0b000;
- let Inst{4-0} = Rd;
- }
-
-// F2_sffma: Floating-point fused multiply add.
-let Uses = [USR], isFP = 1, hasNewValue = 1 in
-class T_sfmpy_acc <bit isSub, bit isLib>
- : MInst<(outs IntRegs:$Rx),
- (ins IntRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt),
- "$Rx "#!if(isSub, "-=","+=")#" sfmpy($Rs, $Rt)"#!if(isLib, ":lib",""),
- [], "$dst2 = $Rx" , M_tc_3or4x_SLOT23 > ,
- Requires<[HasV5T]> {
- bits<5> Rx;
- bits<5> Rs;
- bits<5> Rt;
-
- let IClass = 0b1110;
-
- let Inst{27-21} = 0b1111000;
- let Inst{20-16} = Rs;
- let Inst{13} = 0b0;
- let Inst{12-8} = Rt;
- let Inst{7} = 0b1;
- let Inst{6} = isLib;
- let Inst{5} = isSub;
- let Inst{4-0} = Rx;
- }
-
-def F2_sffma: T_sfmpy_acc <0, 0>;
-def F2_sffms: T_sfmpy_acc <1, 0>;
-def F2_sffma_lib: T_sfmpy_acc <0, 1>;
-def F2_sffms_lib: T_sfmpy_acc <1, 1>;
-
-// Floating-point fused multiply add w/ additional scaling (2**pu).
-let Uses = [USR], isFP = 1, hasNewValue = 1 in
-def F2_sffma_sc: MInst <
- (outs IntRegs:$Rx),
- (ins IntRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt, PredRegs:$Pu),
- "$Rx += sfmpy($Rs, $Rt, $Pu):scale" ,
- [], "$dst2 = $Rx" , M_tc_3or4x_SLOT23 > ,
- Requires<[HasV5T]> {
- bits<5> Rx;
- bits<5> Rs;
- bits<5> Rt;
- bits<2> Pu;
-
- let IClass = 0b1110;
-
- let Inst{27-21} = 0b1111011;
- let Inst{20-16} = Rs;
- let Inst{13} = 0b0;
- let Inst{12-8} = Rt;
- let Inst{7} = 0b1;
- let Inst{6-5} = Pu;
- let Inst{4-0} = Rx;
- }
-
-//===----------------------------------------------------------------------===//
-// :natural forms of vasrh and vasrhub insns
-//===----------------------------------------------------------------------===//
-// S5_asrhub_rnd_sat: Vector arithmetic shift right by immediate with round,
-// saturate, and pack.
-let Defs = [USR_OVF], hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
-class T_ASRHUB<bit isSat>
- : SInst <(outs IntRegs:$Rd),
- (ins DoubleRegs:$Rss, u4_0Imm:$u4),
- "$Rd = vasrhub($Rss, #$u4):"#!if(isSat, "sat", "raw"),
- [], "", S_2op_tc_2_SLOT23>,
- Requires<[HasV5T]> {
- bits<5> Rd;
- bits<5> Rss;
- bits<4> u4;
-
- let IClass = 0b1000;
-
- let Inst{27-21} = 0b1000011;
- let Inst{20-16} = Rss;
- let Inst{13-12} = 0b00;
- let Inst{11-8} = u4;
- let Inst{7-6} = 0b10;
- let Inst{5} = isSat;
- let Inst{4-0} = Rd;
- }
-
-def S5_asrhub_rnd_sat : T_ASRHUB <0>;
-def S5_asrhub_sat : T_ASRHUB <1>;
-
-let isAsmParserOnly = 1 in
-def S5_asrhub_rnd_sat_goodsyntax
- : SInst <(outs IntRegs:$Rd), (ins DoubleRegs:$Rss, u4_0Imm:$u4),
- "$Rd = vasrhub($Rss, #$u4):rnd:sat">, Requires<[HasV5T]>;
-
-// S5_vasrhrnd: Vector arithmetic shift right by immediate with round.
-let hasSideEffects = 0 in
-def S5_vasrhrnd : SInst <(outs DoubleRegs:$Rdd),
- (ins DoubleRegs:$Rss, u4_0Imm:$u4),
- "$Rdd = vasrh($Rss, #$u4):raw">,
- Requires<[HasV5T]> {
- bits<5> Rdd;
- bits<5> Rss;
- bits<4> u4;
-
- let IClass = 0b1000;
-
- let Inst{27-21} = 0b0000001;
- let Inst{20-16} = Rss;
- let Inst{13-12} = 0b00;
- let Inst{11-8} = u4;
- let Inst{7-5} = 0b000;
- let Inst{4-0} = Rdd;
- }
-
-let isAsmParserOnly = 1 in
-def S5_vasrhrnd_goodsyntax
- : SInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss, u4_0Imm:$u4),
- "$Rdd = vasrh($Rss,#$u4):rnd">, Requires<[HasV5T]>;
-
-// Floating point reciprocal square root approximation
-let Uses = [USR], isPredicateLate = 1, isFP = 1,
- hasSideEffects = 0, hasNewValue = 1, opNewValue = 0,
- validSubTargets = HasV5SubT in
-def F2_sfinvsqrta: SInst <
- (outs IntRegs:$Rd, PredRegs:$Pe),
- (ins IntRegs:$Rs),
- "$Rd, $Pe = sfinvsqrta($Rs)" > ,
- Requires<[HasV5T]> {
- bits<5> Rd;
- bits<2> Pe;
- bits<5> Rs;
-
- let IClass = 0b1000;
-
- let Inst{27-21} = 0b1011111;
- let Inst{20-16} = Rs;
- let Inst{7} = 0b0;
- let Inst{6-5} = Pe;
- let Inst{4-0} = Rd;
- }
-
-// Complex multiply 32x16
-let Defs = [USR_OVF], Itinerary = S_3op_tc_3x_SLOT23 in {
- def M4_cmpyi_whc : T_S3op_8<"cmpyiwh", 0b101, 1, 1, 1, 1>;
- def M4_cmpyr_whc : T_S3op_8<"cmpyrwh", 0b111, 1, 1, 1, 1>;
-}
-
-// Classify floating-point value
-let Uses = [USR], isFP = 1 in
-def F2_sfclass : T_TEST_BIT_IMM<"sfclass", 0b111>, Requires<[HasV5T]>;
-
-let Uses = [USR], isFP = 1 in
-def F2_dfclass: ALU64Inst<(outs PredRegs:$Pd), (ins DoubleRegs:$Rss, u5_0Imm:$u5),
- "$Pd = dfclass($Rss, #$u5)",
- [], "" , ALU64_tc_2early_SLOT23 > , Requires<[HasV5T]> {
- bits<2> Pd;
- bits<5> Rss;
- bits<5> u5;
-
- let IClass = 0b1101;
- let Inst{27-21} = 0b1100100;
- let Inst{20-16} = Rss;
- let Inst{12-10} = 0b000;
- let Inst{9-5} = u5;
- let Inst{4-3} = 0b10;
- let Inst{1-0} = Pd;
- }
-
-// Instructions to create floating point constant
-class T_fimm <string mnemonic, RegisterClass RC, bits<4> RegType, bit isNeg>
- : ALU64Inst<(outs RC:$dst), (ins u10_0Imm:$src),
- "$dst = "#mnemonic#"(#$src)"#!if(isNeg, ":neg", ":pos"),
- [], "", ALU64_tc_2_SLOT23>, Requires<[HasV5T]> {
- bits<5> dst;
- bits<10> src;
-
- let IClass = 0b1101;
- let Inst{27-24} = RegType;
- let Inst{23} = 0b0;
- let Inst{22} = isNeg;
- let Inst{21} = src{9};
- let Inst{13-5} = src{8-0};
- let Inst{4-0} = dst;
- }
-
-let hasNewValue = 1, opNewValue = 0 in {
- def F2_sfimm_p : T_fimm <"sfmake", IntRegs, 0b0110, 0>;
- def F2_sfimm_n : T_fimm <"sfmake", IntRegs, 0b0110, 1>;
-}
-
-def F2_dfimm_p : T_fimm <"dfmake", DoubleRegs, 0b1001, 0>;
-def F2_dfimm_n : T_fimm <"dfmake", DoubleRegs, 0b1001, 1>;
Removed: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV60.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV60.td?rev=294752&view=auto
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV60.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV60.td (removed)
@@ -1,2068 +0,0 @@
-//=- HexagonInstrInfoV60.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file describes the Hexagon V60 instructions in TableGen format.
-//
-//===----------------------------------------------------------------------===//
-// Vector load
-let Predicates = [HasV60T, UseHVX] in
-let mayLoad = 1, validSubTargets = HasV60SubT, hasSideEffects = 0 in
- class V6_LDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
- string cstr = "", InstrItinClass itin = CVI_VM_LD,
- IType type = TypeCVI_VM_LD>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, type>;
-
-// Vector store
-let Predicates = [HasV60T, UseHVX] in
-let mayStore = 1, validSubTargets = HasV60SubT, hasSideEffects = 0 in
-class V6_STInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
- string cstr = "", InstrItinClass itin = CVI_VM_ST,
- IType type = TypeCVI_VM_ST>
-: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, type>;
-
-//===----------------------------------------------------------------------===//
-// Vector loads with base + immediate offset
-//===----------------------------------------------------------------------===//
-let addrMode = BaseImmOffset, accessSize = Vector64Access in
-class T_vload_ai<string asmStr>
- : V6_LDInst <(outs VectorRegs:$dst), (ins IntRegs:$src1, s4_6Imm:$src2),
- asmStr>;
-
-let isCodeGenOnly = 1, addrMode = BaseImmOffset, accessSize = Vector128Access in
-class T_vload_ai_128B<string asmStr>
- : V6_LDInst <(outs VectorRegs128B:$dst), (ins IntRegs:$src1, s4_7Imm:$src2),
- asmStr>;
-
-let isCVLoadable = 1, hasNewValue = 1 in {
- def V6_vL32b_ai : T_vload_ai <"$dst = vmem($src1+#$src2)">,
- V6_vL32b_ai_enc;
- def V6_vL32b_nt_ai : T_vload_ai <"$dst = vmem($src1+#$src2):nt">,
- V6_vL32b_nt_ai_enc;
- // 128B
- def V6_vL32b_ai_128B : T_vload_ai_128B <"$dst = vmem($src1+#$src2)">,
- V6_vL32b_ai_128B_enc;
- def V6_vL32b_nt_ai_128B : T_vload_ai_128B <"$dst = vmem($src1+#$src2):nt">,
- V6_vL32b_nt_ai_128B_enc;
-}
-
-let Itinerary = CVI_VM_VP_LDU, Type = TypeCVI_VM_VP_LDU, hasNewValue = 1 in {
- def V6_vL32Ub_ai : T_vload_ai <"$dst = vmemu($src1+#$src2)">,
- V6_vL32Ub_ai_enc;
- def V6_vL32Ub_ai_128B : T_vload_ai_128B <"$dst = vmemu($src1+#$src2)">,
- V6_vL32Ub_ai_128B_enc;
-}
-
-let Itinerary = CVI_VM_LD, Type = TypeCVI_VM_LD, isCVLoad = 1,
- hasNewValue = 1 in {
- def V6_vL32b_cur_ai : T_vload_ai <"$dst.cur = vmem($src1+#$src2)">,
- V6_vL32b_cur_ai_enc;
- def V6_vL32b_nt_cur_ai : T_vload_ai <"$dst.cur = vmem($src1+#$src2):nt">,
- V6_vL32b_nt_cur_ai_enc;
- // 128B
- def V6_vL32b_cur_ai_128B : T_vload_ai_128B
- <"$dst.cur = vmem($src1+#$src2)">,
- V6_vL32b_cur_ai_128B_enc;
- def V6_vL32b_nt_cur_ai_128B : T_vload_ai_128B
- <"$dst.cur = vmem($src1+#$src2):nt">,
- V6_vL32b_nt_cur_ai_128B_enc;
-}
-
-
-let Itinerary = CVI_VM_TMP_LD, Type = TypeCVI_VM_TMP_LD, hasNewValue = 1 in {
- def V6_vL32b_tmp_ai : T_vload_ai <"$dst.tmp = vmem($src1+#$src2)">,
- V6_vL32b_tmp_ai_enc;
- def V6_vL32b_nt_tmp_ai : T_vload_ai <"$dst.tmp = vmem($src1+#$src2):nt">,
- V6_vL32b_nt_tmp_ai_enc;
- // 128B
- def V6_vL32b_tmp_ai_128B : T_vload_ai_128B
- <"$dst.tmp = vmem($src1+#$src2)">,
- V6_vL32b_tmp_ai_128B_enc;
- def V6_vL32b_nt_tmp_ai_128B : T_vload_ai_128B
- <"$dst.tmp = vmem($src1+#$src2)">,
- V6_vL32b_nt_tmp_ai_128B_enc;
-}
-
-//===----------------------------------------------------------------------===//
-// Vector stores with base + immediate offset - unconditional
-//===----------------------------------------------------------------------===//
-let addrMode = BaseImmOffset, accessSize = Vector64Access, isPredicable = 1 in
-class T_vstore_ai <string mnemonic, string baseOp, Operand ImmOp,
- RegisterClass RC, bit isNT>
- : V6_STInst <(outs), (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
- mnemonic#"($src1+#$src2)"#!if(isNT, ":nt", "")#" = $src3">, NewValueRel {
- let BaseOpcode = baseOp;
-}
-
-let accessSize = Vector64Access in
-class T_vstore_ai_64B <string mnemonic, string baseOp, bit isNT = 0>
- : T_vstore_ai <mnemonic, baseOp, s4_6Imm, VectorRegs, isNT>;
-
-let isCodeGenOnly = 1, accessSize = Vector128Access in
-class T_vstore_ai_128B <string mnemonic, string baseOp, bit isNT = 0>
- : T_vstore_ai <mnemonic, baseOp#"128B", s4_7Imm, VectorRegs128B, isNT>;
-
-let isNVStorable = 1 in {
- def V6_vS32b_ai : T_vstore_ai_64B <"vmem", "vS32b_ai">,
- V6_vS32b_ai_enc;
- def V6_vS32b_ai_128B : T_vstore_ai_128B <"vmem", "vS32b_ai">,
- V6_vS32b_ai_128B_enc;
-}
-
-let isNVStorable = 1, isNonTemporal = 1 in {
- def V6_vS32b_nt_ai : T_vstore_ai_64B <"vmem", "vS32b_ai", 1>,
- V6_vS32b_nt_ai_enc;
- def V6_vS32b_nt_ai_128B : T_vstore_ai_128B <"vmem", "vS32b_ai", 1>,
- V6_vS32b_nt_ai_128B_enc;
-}
-
-let Itinerary = CVI_VM_STU, Type = TypeCVI_VM_STU in {
- def V6_vS32Ub_ai : T_vstore_ai_64B <"vmemu", "vS32Ub_ai">,
- V6_vS32Ub_ai_enc;
- def V6_vS32Ub_ai_128B : T_vstore_ai_128B <"vmemu", "vS32Ub_ai">,
- V6_vS32Ub_ai_128B_enc;
-}
-//===----------------------------------------------------------------------===//
-// Vector stores with base + immediate offset - unconditional new
-//===----------------------------------------------------------------------===//
-let addrMode = BaseImmOffset, isNewValue = 1, opNewValue = 2, isNVStore = 1,
- isPredicable = 1, Itinerary = CVI_VM_NEW_ST, Type = TypeCVI_VM_NEW_ST in
-class T_vstore_new_ai <string baseOp, Operand ImmOp, RegisterClass RC, bit isNT>
- : V6_STInst <(outs ), (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
- "vmem($src1+#$src2)"#!if(isNT, ":nt", "")#" = $src3.new">, NewValueRel {
- let BaseOpcode = baseOp;
-}
-
-let accessSize = Vector64Access in
-class T_vstore_new_ai_64B <string baseOp, bit isNT = 0>
- : T_vstore_new_ai <baseOp, s4_6Imm, VectorRegs, isNT>;
-
-let isCodeGenOnly = 1, accessSize = Vector128Access in
-class T_vstore_new_ai_128B <string baseOp, bit isNT = 0>
- : T_vstore_new_ai <baseOp#"128B", s4_7Imm, VectorRegs128B, isNT>;
-
-def V6_vS32b_new_ai : T_vstore_new_ai_64B <"vS32b_ai">, V6_vS32b_new_ai_enc;
-def V6_vS32b_new_ai_128B : T_vstore_new_ai_128B <"vS32b_ai">,
- V6_vS32b_new_ai_128B_enc;
-
-let isNonTemporal = 1 in {
- def V6_vS32b_nt_new_ai : T_vstore_new_ai_64B<"vS32b_ai", 1>,
- V6_vS32b_nt_new_ai_enc;
- def V6_vS32b_nt_new_ai_128B : T_vstore_new_ai_128B<"vS32b_ai", 1>,
- V6_vS32b_nt_new_ai_128B_enc;
-}
-
-//===----------------------------------------------------------------------===//
-// Vector stores with base + immediate offset - conditional
-//===----------------------------------------------------------------------===//
-let addrMode = BaseImmOffset, isPredicated = 1 in
-class T_vstore_pred_ai <string mnemonic, string baseOp, Operand ImmOp,
- RegisterClass RC, bit isPredNot = 0, bit isNT = 0>
- : V6_STInst <(outs),
- (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4),
- "if ("#!if(isPredNot, "!", "")#"$src1) "
- #mnemonic#"($src2+#$src3)"#!if(isNT, ":nt", "")#" = $src4">, NewValueRel {
- let isPredicatedFalse = isPredNot;
- let BaseOpcode = baseOp;
-}
-
-let accessSize = Vector64Access in
-class T_vstore_pred_ai_64B <string mnemonic, string baseOp,
- bit isPredNot = 0, bit isNT = 0>
- : T_vstore_pred_ai <mnemonic, baseOp, s4_6Imm, VectorRegs, isPredNot, isNT>;
-
-let isCodeGenOnly = 1, accessSize = Vector128Access in
-class T_vstore_pred_ai_128B <string mnemonic, string baseOp,
- bit isPredNot = 0, bit isNT = 0>
- : T_vstore_pred_ai <mnemonic, baseOp#"128B", s4_7Imm, VectorRegs128B,
- isPredNot, isNT>;
-
-let isNVStorable = 1 in {
- def V6_vS32b_pred_ai : T_vstore_pred_ai_64B <"vmem", "vS32b_ai">,
- V6_vS32b_pred_ai_enc;
- def V6_vS32b_npred_ai : T_vstore_pred_ai_64B <"vmem", "vS32b_ai", 1>,
- V6_vS32b_npred_ai_enc;
- // 128B
- def V6_vS32b_pred_ai_128B : T_vstore_pred_ai_128B <"vmem", "vS32b_ai">,
- V6_vS32b_pred_ai_128B_enc;
- def V6_vS32b_npred_ai_128B : T_vstore_pred_ai_128B <"vmem", "vS32b_ai", 1>,
- V6_vS32b_npred_ai_128B_enc;
-}
-
-
-let isNVStorable = 1, isNonTemporal = 1 in {
- def V6_vS32b_nt_pred_ai : T_vstore_pred_ai_64B <"vmem", "vS32b_ai", 0, 1>,
- V6_vS32b_nt_pred_ai_enc;
- def V6_vS32b_nt_npred_ai : T_vstore_pred_ai_64B <"vmem", "vS32b_ai", 1, 1>,
- V6_vS32b_nt_npred_ai_enc;
- // 128B
- def V6_vS32b_nt_pred_ai_128B : T_vstore_pred_ai_128B
- <"vmem", "vS32b_ai", 0, 1>,
- V6_vS32b_nt_pred_ai_128B_enc;
- def V6_vS32b_nt_npred_ai_128B : T_vstore_pred_ai_128B
- <"vmem", "vS32b_ai", 1, 1>,
- V6_vS32b_nt_npred_ai_128B_enc;
-}
-
-let Itinerary = CVI_VM_STU, Type = TypeCVI_VM_STU in {
- def V6_vS32Ub_pred_ai : T_vstore_pred_ai_64B <"vmemu", "vS32Ub_ai">,
- V6_vS32Ub_pred_ai_enc;
- def V6_vS32Ub_npred_ai : T_vstore_pred_ai_64B <"vmemu", "vS32Ub_ai", 1>,
- V6_vS32Ub_npred_ai_enc;
- // 128B
- def V6_vS32Ub_pred_ai_128B :T_vstore_pred_ai_128B <"vmemu", "vS32Ub_ai">,
- V6_vS32Ub_pred_ai_128B_enc;
- def V6_vS32Ub_npred_ai_128B :T_vstore_pred_ai_128B <"vmemu", "vS32Ub_ai", 1>,
- V6_vS32Ub_npred_ai_128B_enc;
-}
-
-//===----------------------------------------------------------------------===//
-// Vector stores with base + immediate offset - byte-enabled aligned
-//===----------------------------------------------------------------------===//
-let addrMode = BaseImmOffset in
-class T_vstore_qpred_ai <Operand ImmOp, RegisterClass RC,
- bit isPredNot = 0, bit isNT = 0>
- : V6_STInst <(outs),
- (ins VecPredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4),
- "if ("#!if(isPredNot, "!", "")#"$src1) vmem($src2+#$src3)"
- #!if(isNT, ":nt", "")#" = $src4"> {
- let isPredicatedFalse = isPredNot;
-}
-
-let accessSize = Vector64Access in
-class T_vstore_qpred_ai_64B <bit isPredNot = 0, bit isNT = 0>
- : T_vstore_qpred_ai <s4_6Imm, VectorRegs, isPredNot, isNT>;
-
-let isCodeGenOnly = 1, accessSize = Vector128Access in
-class T_vstore_qpred_ai_128B <bit isPredNot = 0, bit isNT = 0>
- : T_vstore_qpred_ai <s4_7Imm, VectorRegs128B, isPredNot, isNT>;
-
-def V6_vS32b_qpred_ai : T_vstore_qpred_ai_64B, V6_vS32b_qpred_ai_enc;
-def V6_vS32b_nqpred_ai : T_vstore_qpred_ai_64B <1>,
- V6_vS32b_nqpred_ai_enc;
-def V6_vS32b_nt_qpred_ai : T_vstore_qpred_ai_64B <0, 1>,
- V6_vS32b_nt_qpred_ai_enc;
-def V6_vS32b_nt_nqpred_ai : T_vstore_qpred_ai_64B <1, 1>,
- V6_vS32b_nt_nqpred_ai_enc;
-// 128B
-def V6_vS32b_qpred_ai_128B : T_vstore_qpred_ai_128B, V6_vS32b_qpred_ai_128B_enc;
-def V6_vS32b_nqpred_ai_128B : T_vstore_qpred_ai_128B<1>,
- V6_vS32b_nqpred_ai_128B_enc;
-def V6_vS32b_nt_qpred_ai_128B : T_vstore_qpred_ai_128B<0, 1>,
- V6_vS32b_nt_qpred_ai_128B_enc;
-def V6_vS32b_nt_nqpred_ai_128B : T_vstore_qpred_ai_128B<1, 1>,
- V6_vS32b_nt_nqpred_ai_128B_enc;
-
-
-//===----------------------------------------------------------------------===//
-// Vector stores with base + immediate offset - conditional new
-//===----------------------------------------------------------------------===//
-let addrMode = BaseImmOffset, isPredicated = 1, isNewValue = 1, opNewValue = 3,
- isNVStore = 1, Type = TypeCVI_VM_NEW_ST, Itinerary = CVI_VM_NEW_ST in
-class T_vstore_new_pred_ai <string baseOp, Operand ImmOp, RegisterClass RC,
- bit isPredNot, bit isNT>
- : V6_STInst <(outs),
- (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4),
- "if("#!if(isPredNot, "!", "")#"$src1) vmem($src2+#$src3)"
- #!if(isNT, ":nt", "")#" = $src4.new">, NewValueRel {
- let isPredicatedFalse = isPredNot;
- let BaseOpcode = baseOp;
-}
-
-let accessSize = Vector64Access in
-class T_vstore_new_pred_ai_64B <string baseOp, bit isPredNot = 0, bit isNT = 0>
- : T_vstore_new_pred_ai <baseOp, s4_6Imm, VectorRegs, isPredNot, isNT>;
-
-let isCodeGenOnly = 1, accessSize = Vector128Access in
-class T_vstore_new_pred_ai_128B <string baseOp, bit isPredNot = 0, bit isNT = 0>
- : T_vstore_new_pred_ai <baseOp#"128B", s4_7Imm, VectorRegs128B,
- isPredNot, isNT>;
-
-
-def V6_vS32b_new_pred_ai : T_vstore_new_pred_ai_64B <"vS32b_ai">,
- V6_vS32b_new_pred_ai_enc;
-def V6_vS32b_new_npred_ai : T_vstore_new_pred_ai_64B <"vS32b_ai", 1>,
- V6_vS32b_new_npred_ai_enc;
-// 128B
-def V6_vS32b_new_pred_ai_128B : T_vstore_new_pred_ai_128B <"vS32b_ai">,
- V6_vS32b_new_pred_ai_128B_enc;
-def V6_vS32b_new_npred_ai_128B : T_vstore_new_pred_ai_128B <"vS32b_ai", 1>,
- V6_vS32b_new_npred_ai_128B_enc;
-let isNonTemporal = 1 in {
- def V6_vS32b_nt_new_pred_ai : T_vstore_new_pred_ai_64B <"vS32b_ai", 0, 1>,
- V6_vS32b_nt_new_pred_ai_enc;
- def V6_vS32b_nt_new_npred_ai : T_vstore_new_pred_ai_64B <"vS32b_ai", 1, 1>,
- V6_vS32b_nt_new_npred_ai_enc;
- // 128B
- def V6_vS32b_nt_new_pred_ai_128B : T_vstore_new_pred_ai_128B
- <"vS32b_ai", 0, 1>,
- V6_vS32b_nt_new_pred_ai_128B_enc;
- def V6_vS32b_nt_new_npred_ai_128B : T_vstore_new_pred_ai_128B
- <"vS32b_ai", 1, 1>,
- V6_vS32b_nt_new_npred_ai_128B_enc;
-}
-
-//===----------------------------------------------------------------------===//
-// Post increment vector loads with immediate offset.
-//===----------------------------------------------------------------------===//
-let addrMode = PostInc, hasNewValue = 1 in
-class T_vload_pi<string asmStr, Operand ImmOp, RegisterClass RC>
- : V6_LDInst <(outs RC:$dst, IntRegs:$_dst_),
- (ins IntRegs:$src1, ImmOp:$src2), asmStr, [],
- "$src1 = $_dst_">;
-
-let accessSize = Vector64Access in
-class T_vload_pi_64B <string asmStr>
- : T_vload_pi <asmStr, s3_6Imm, VectorRegs>;
-
-let isCodeGenOnly = 1, accessSize = Vector128Access in
-class T_vload_pi_128B <string asmStr>
- : T_vload_pi <asmStr, s3_7Imm, VectorRegs128B>;
-
-let isCVLoadable = 1 in {
- def V6_vL32b_pi : T_vload_pi_64B <"$dst = vmem($src1++#$src2)">,
- V6_vL32b_pi_enc;
- def V6_vL32b_nt_pi : T_vload_pi_64B <"$dst = vmem($src1++#$src2):nt">,
- V6_vL32b_nt_pi_enc;
- // 128B
- def V6_vL32b_pi_128B : T_vload_pi_128B <"$dst = vmem($src1++#$src2)">,
- V6_vL32b_pi_128B_enc;
- def V6_vL32b_nt_pi_128B : T_vload_pi_128B <"$dst = vmem($src1++#$src2):nt">,
- V6_vL32b_nt_pi_128B_enc;
-}
-
-let Itinerary = CVI_VM_VP_LDU, Type = TypeCVI_VM_VP_LDU in {
- def V6_vL32Ub_pi : T_vload_pi_64B <"$dst = vmemu($src1++#$src2)">,
- V6_vL32Ub_pi_enc;
- // 128B
- def V6_vL32Ub_pi_128B : T_vload_pi_128B <"$dst = vmemu($src1++#$src2)">,
- V6_vL32Ub_pi_128B_enc;
-}
-
-let isCVLoad = 1, Itinerary = CVI_VM_LD, Type = TypeCVI_VM_LD in {
- def V6_vL32b_cur_pi : T_vload_pi_64B <"$dst.cur = vmem($src1++#$src2)">,
- V6_vL32b_cur_pi_enc;
- def V6_vL32b_nt_cur_pi : T_vload_pi_64B <"$dst.cur = vmem($src1++#$src2):nt">,
- V6_vL32b_nt_cur_pi_enc;
- // 128B
- def V6_vL32b_cur_pi_128B : T_vload_pi_128B
- <"$dst.cur = vmem($src1++#$src2)">,
- V6_vL32b_cur_pi_128B_enc;
- def V6_vL32b_nt_cur_pi_128B : T_vload_pi_128B
- <"$dst.cur = vmem($src1++#$src2):nt">,
- V6_vL32b_nt_cur_pi_128B_enc;
-}
-
-let Itinerary = CVI_VM_TMP_LD, Type = TypeCVI_VM_TMP_LD in {
- def V6_vL32b_tmp_pi : T_vload_pi_64B <"$dst.tmp = vmem($src1++#$src2)">,
- V6_vL32b_tmp_pi_enc;
- def V6_vL32b_nt_tmp_pi : T_vload_pi_64B <"$dst.tmp = vmem($src1++#$src2):nt">,
- V6_vL32b_nt_tmp_pi_enc;
- //128B
- def V6_vL32b_tmp_pi_128B : T_vload_pi_128B
- <"$dst.tmp = vmem($src1++#$src2)">,
- V6_vL32b_tmp_pi_128B_enc;
- def V6_vL32b_nt_tmp_pi_128B : T_vload_pi_128B
- <"$dst.tmp = vmem($src1++#$src2):nt">,
- V6_vL32b_nt_tmp_pi_128B_enc;
-}
-
-//===----------------------------------------------------------------------===//
-// Post increment vector stores with immediate offset.
-//===----------------------------------------------------------------------===//
-let addrMode = PostInc, isPredicable = 1 in
-class T_vstore_pi <string mnemonic, string baseOp, Operand ImmOp,
- RegisterClass RC, bit isNT>
- : V6_STInst <(outs IntRegs:$_dst_),
- (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
- mnemonic#"($src1++#$src2)"#!if(isNT, ":nt", "")#" = $src3", [],
- "$src1 = $_dst_">, NewValueRel {
- let BaseOpcode = baseOp;
-}
-
-let accessSize = Vector64Access in
-class T_vstore_pi_64B <string mnemonic, string baseOp, bit isNT = 0>
- : T_vstore_pi <mnemonic, baseOp, s3_6Imm, VectorRegs, isNT>;
-
-let isCodeGenOnly = 1, accessSize = Vector128Access in
-class T_vstore_pi_128B <string mnemonic, string baseOp, bit isNT = 0>
- : T_vstore_pi <mnemonic, baseOp#"128B", s3_7Imm, VectorRegs128B, isNT>;
-
-let isNVStorable = 1 in {
- def V6_vS32b_pi : T_vstore_pi_64B <"vmem", "vS32b_pi">, V6_vS32b_pi_enc;
- def V6_vS32b_pi_128B : T_vstore_pi_128B <"vmem", "vS32b_pi">,
- V6_vS32b_pi_128B_enc;
-}
-
-let isNVStorable = 1 , isNonTemporal = 1 in {
- def V6_vS32b_nt_pi : T_vstore_pi_64B <"vmem", "vS32b_pi", 1>,
- V6_vS32b_nt_pi_enc;
- def V6_vS32b_nt_pi_128B : T_vstore_pi_128B <"vmem", "vS32b_pi", 1>,
- V6_vS32b_nt_pi_128B_enc;
-}
-
-
-let Itinerary = CVI_VM_STU, Type = TypeCVI_VM_STU in {
- def V6_vS32Ub_pi : T_vstore_pi_64B <"vmemu", "vS32Ub_pi">,
- V6_vS32Ub_pi_enc;
- def V6_vS32Ub_pi_128B : T_vstore_pi_128B <"vmemu", "vS32Ub_pi">,
- V6_vS32Ub_pi_128B_enc;
-}
-
-//===----------------------------------------------------------------------===//
-// Post increment unconditional .new vector stores with immediate offset.
-//===----------------------------------------------------------------------===//
-let addrMode = PostInc, isNVStore = 1 in
-let Itinerary = CVI_VM_NEW_ST, Type = TypeCVI_VM_NEW_ST, isNewValue = 1,
- isPredicable = 1, opNewValue = 3, isNVStore = 1 in
-class T_vstore_new_pi <string baseOp, Operand ImmOp, RegisterClass RC, bit isNT>
- : V6_STInst <(outs IntRegs:$_dst_),
- (ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
- "vmem($src1++#$src2)"#!if(isNT, ":nt", "")#" = $src3.new", [],
- "$src1 = $_dst_">, NewValueRel {
- let BaseOpcode = baseOp;
-}
-
-let accessSize = Vector64Access in
-class T_vstore_new_pi_64B <string baseOp, bit isNT = 0>
- : T_vstore_new_pi <baseOp, s3_6Imm, VectorRegs, isNT>;
-
-let isCodeGenOnly = 1, accessSize = Vector128Access in
-class T_vstore_new_pi_128B <string baseOp, bit isNT = 0>
- : T_vstore_new_pi <baseOp#"128B", s3_7Imm, VectorRegs128B, isNT>;
-
-
-def V6_vS32b_new_pi : T_vstore_new_pi_64B <"vS32b_pi">,
- V6_vS32b_new_pi_enc;
-def V6_vS32b_new_pi_128B : T_vstore_new_pi_128B <"vS32b_pi">,
- V6_vS32b_new_pi_128B_enc;
-
-let isNonTemporal = 1 in {
- def V6_vS32b_nt_new_pi : T_vstore_new_pi_64B <"vS32b_pi", 1>,
- V6_vS32b_nt_new_pi_enc;
- def V6_vS32b_nt_new_pi_128B : T_vstore_new_pi_128B <"vS32b_pi", 1>,
- V6_vS32b_nt_new_pi_128B_enc;
-}
-
-//===----------------------------------------------------------------------===//
-// Post increment conditional vector stores with immediate offset
-//===----------------------------------------------------------------------===//
-let isPredicated = 1, addrMode = PostInc in
-class T_vstore_pred_pi <string mnemonic, string baseOp, Operand ImmOp,
- RegisterClass RC, bit isPredNot, bit isNT>
- : V6_STInst<(outs IntRegs:$_dst_),
- (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4),
- "if ("#!if(isPredNot, "!", "")#"$src1) "#mnemonic#"($src2++#$src3)"
- #!if(isNT, ":nt", "")#" = $src4", [],
- "$src2 = $_dst_">, NewValueRel {
- let isPredicatedFalse = isPredNot;
- let BaseOpcode = baseOp;
-}
-
-let accessSize = Vector64Access in
-class T_vstore_pred_pi_64B <string mnemonic, string baseOp,
- bit isPredNot = 0, bit isNT = 0>
- : T_vstore_pred_pi <mnemonic, baseOp, s3_6Imm, VectorRegs, isPredNot, isNT>;
-
-let isCodeGenOnly = 1, accessSize = Vector128Access in
-class T_vstore_pred_pi_128B <string mnemonic, string baseOp,
- bit isPredNot = 0, bit isNT = 0>
- : T_vstore_pred_pi <mnemonic, baseOp#"128B", s3_7Imm, VectorRegs128B,
- isPredNot, isNT>;
-
-let isNVStorable = 1 in {
- def V6_vS32b_pred_pi : T_vstore_pred_pi_64B <"vmem", "vS32b_pi">,
- V6_vS32b_pred_pi_enc;
- def V6_vS32b_npred_pi : T_vstore_pred_pi_64B <"vmem", "vS32b_pi", 1>,
- V6_vS32b_npred_pi_enc;
- // 128B
- def V6_vS32b_pred_pi_128B : T_vstore_pred_pi_128B <"vmem", "vS32b_pi">,
- V6_vS32b_pred_pi_128B_enc;
- def V6_vS32b_npred_pi_128B : T_vstore_pred_pi_128B <"vmem", "vS32b_pi", 1>,
- V6_vS32b_npred_pi_128B_enc;
-}
-let isNVStorable = 1, isNonTemporal = 1 in {
- def V6_vS32b_nt_pred_pi : T_vstore_pred_pi_64B <"vmem", "vS32b_pi", 0, 1>,
- V6_vS32b_nt_pred_pi_enc;
- def V6_vS32b_nt_npred_pi : T_vstore_pred_pi_64B <"vmem", "vS32b_pi", 1, 1>,
- V6_vS32b_nt_npred_pi_enc;
- // 128B
- def V6_vS32b_nt_pred_pi_128B : T_vstore_pred_pi_128B
- <"vmem", "vS32b_pi", 0, 1>,
- V6_vS32b_nt_pred_pi_128B_enc;
- def V6_vS32b_nt_npred_pi_128B : T_vstore_pred_pi_128B
- <"vmem", "vS32b_pi", 1, 1>,
- V6_vS32b_nt_npred_pi_128B_enc;
-}
-
-let Itinerary = CVI_VM_STU, Type = TypeCVI_VM_STU in {
- def V6_vS32Ub_pred_pi : T_vstore_pred_pi_64B <"vmemu", "vS32Ub_pi">,
- V6_vS32Ub_pred_pi_enc;
- def V6_vS32Ub_npred_pi : T_vstore_pred_pi_64B <"vmemu", "vS32Ub_pi", 1>,
- V6_vS32Ub_npred_pi_enc;
- // 128B
- def V6_vS32Ub_pred_pi_128B : T_vstore_pred_pi_128B <"vmemu", "vS32Ub_pi">,
- V6_vS32Ub_pred_pi_128B_enc;
- def V6_vS32Ub_npred_pi_128B : T_vstore_pred_pi_128B <"vmemu", "vS32Ub_pi", 1>,
- V6_vS32Ub_npred_pi_128B_enc;
-}
-
-//===----------------------------------------------------------------------===//
-// Post increment vector stores with immediate offset - byte-enabled aligned
-//===----------------------------------------------------------------------===//
-let addrMode = PostInc in
-class T_vstore_qpred_pi <Operand ImmOp, RegisterClass RC, bit isPredNot = 0,
- bit isNT = 0>
- : V6_STInst <(outs IntRegs:$_dst_),
- (ins VecPredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4),
- "if ("#!if(isPredNot, "!", "")#"$src1) vmem($src2++#$src3)"
- #!if(isNT, ":nt", "")#" = $src4", [],
- "$src2 = $_dst_">;
-
-let accessSize = Vector64Access in
-class T_vstore_qpred_pi_64B <bit isPredNot = 0, bit isNT = 0>
- : T_vstore_qpred_pi <s3_6Imm, VectorRegs, isPredNot, isNT>;
-
-let isCodeGenOnly = 1, accessSize = Vector128Access in
-class T_vstore_qpred_pi_128B <bit isPredNot = 0, bit isNT = 0>
- : T_vstore_qpred_pi <s3_7Imm, VectorRegs128B, isPredNot, isNT>;
-
-def V6_vS32b_qpred_pi : T_vstore_qpred_pi_64B, V6_vS32b_qpred_pi_enc;
-def V6_vS32b_nqpred_pi : T_vstore_qpred_pi_64B <1>, V6_vS32b_nqpred_pi_enc;
-// 128B
-def V6_vS32b_qpred_pi_128B : T_vstore_qpred_pi_128B,
- V6_vS32b_qpred_pi_128B_enc;
-def V6_vS32b_nqpred_pi_128B : T_vstore_qpred_pi_128B<1>,
- V6_vS32b_nqpred_pi_128B_enc;
-
-let isNonTemporal = 1 in {
- def V6_vS32b_nt_qpred_pi : T_vstore_qpred_pi_64B <0, 1>,
- V6_vS32b_nt_qpred_pi_enc;
- def V6_vS32b_nt_nqpred_pi : T_vstore_qpred_pi_64B <1, 1>,
- V6_vS32b_nt_nqpred_pi_enc;
- // 128B
- def V6_vS32b_nt_qpred_pi_128B : T_vstore_qpred_pi_128B<0, 1>,
- V6_vS32b_nt_qpred_pi_128B_enc;
- def V6_vS32b_nt_nqpred_pi_128B : T_vstore_qpred_pi_128B<1, 1>,
- V6_vS32b_nt_nqpred_pi_128B_enc;
-}
-
-//===----------------------------------------------------------------------===//
-// Post increment conditional .new vector stores with immediate offset
-//===----------------------------------------------------------------------===//
-let Itinerary = CVI_VM_NEW_ST, Type = TypeCVI_VM_NEW_ST, isPredicated = 1,
- isNewValue = 1, opNewValue = 4, addrMode = PostInc, isNVStore = 1 in
-class T_vstore_new_pred_pi <string baseOp, Operand ImmOp, RegisterClass RC,
- bit isPredNot, bit isNT>
- : V6_STInst <(outs IntRegs:$_dst_),
- (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4),
- "if("#!if(isPredNot, "!", "")#"$src1) vmem($src2++#$src3)"
- #!if(isNT, ":nt", "")#" = $src4.new", [],
- "$src2 = $_dst_"> , NewValueRel {
- let isPredicatedFalse = isPredNot;
- let BaseOpcode = baseOp;
-}
-
-let accessSize = Vector64Access in
-class T_vstore_new_pred_pi_64B <string baseOp, bit isPredNot = 0, bit isNT = 0>
- : T_vstore_new_pred_pi <baseOp, s3_6Imm, VectorRegs, isPredNot, isNT>;
-
-let isCodeGenOnly = 1, accessSize = Vector128Access in
-class T_vstore_new_pred_pi_128B <string baseOp, bit isPredNot = 0, bit isNT = 0>
- : T_vstore_new_pred_pi <baseOp#"128B", s3_7Imm, VectorRegs128B,
- isPredNot, isNT>;
-
-def V6_vS32b_new_pred_pi : T_vstore_new_pred_pi_64B <"vS32b_pi">,
- V6_vS32b_new_pred_pi_enc;
-def V6_vS32b_new_npred_pi : T_vstore_new_pred_pi_64B <"vS32b_pi", 1>,
- V6_vS32b_new_npred_pi_enc;
-// 128B
-def V6_vS32b_new_pred_pi_128B : T_vstore_new_pred_pi_128B <"vS32b_pi">,
- V6_vS32b_new_pred_pi_128B_enc;
-def V6_vS32b_new_npred_pi_128B : T_vstore_new_pred_pi_128B <"vS32b_pi", 1>,
- V6_vS32b_new_npred_pi_128B_enc;
-let isNonTemporal = 1 in {
- def V6_vS32b_nt_new_pred_pi : T_vstore_new_pred_pi_64B <"vS32b_pi", 0, 1>,
- V6_vS32b_nt_new_pred_pi_enc;
- def V6_vS32b_nt_new_npred_pi : T_vstore_new_pred_pi_64B <"vS32b_pi", 1, 1>,
- V6_vS32b_nt_new_npred_pi_enc;
- // 128B
- def V6_vS32b_nt_new_pred_pi_128B : T_vstore_new_pred_pi_128B
- <"vS32b_pi", 0, 1>,
- V6_vS32b_nt_new_pred_pi_128B_enc;
- def V6_vS32b_nt_new_npred_pi_128B : T_vstore_new_pred_pi_128B
- <"vS32b_pi", 1, 1>,
- V6_vS32b_nt_new_npred_pi_128B_enc;
-}
-
-//===----------------------------------------------------------------------===//
-// Post increment vector loads with register offset
-//===----------------------------------------------------------------------===//
-let hasNewValue = 1 in
-class T_vload_ppu<string asmStr>
- : V6_LDInst <(outs VectorRegs:$dst, IntRegs:$_dst_),
- (ins IntRegs:$src1, ModRegs:$src2), asmStr, [],
- "$src1 = $_dst_">, NewValueRel;
-
-let isCVLoadable = 1 in {
- def V6_vL32b_ppu : T_vload_ppu <"$dst = vmem($src1++$src2)">,
- V6_vL32b_ppu_enc;
- def V6_vL32b_nt_ppu : T_vload_ppu <"$dst = vmem($src1++$src2):nt">,
- V6_vL32b_nt_ppu_enc;
-}
-
-let Itinerary = CVI_VM_VP_LDU, Type = TypeCVI_VM_VP_LDU in
-def V6_vL32Ub_ppu : T_vload_ppu <"$dst = vmemu($src1++$src2)">,
- V6_vL32Ub_ppu_enc;
-
-let isCVLoad = 1, Itinerary = CVI_VM_CUR_LD, Type = TypeCVI_VM_CUR_LD in {
- def V6_vL32b_cur_ppu : T_vload_ppu <"$dst.cur = vmem($src1++$src2)">,
- V6_vL32b_cur_ppu_enc;
- def V6_vL32b_nt_cur_ppu : T_vload_ppu <"$dst.cur = vmem($src1++$src2):nt">,
- V6_vL32b_nt_cur_ppu_enc;
-}
-
-let Itinerary = CVI_VM_TMP_LD, Type = TypeCVI_VM_TMP_LD in {
- def V6_vL32b_tmp_ppu : T_vload_ppu <"$dst.tmp = vmem($src1++$src2)">,
- V6_vL32b_tmp_ppu_enc;
- def V6_vL32b_nt_tmp_ppu : T_vload_ppu <"$dst.tmp = vmem($src1++$src2):nt">,
- V6_vL32b_nt_tmp_ppu_enc;
-}
-
-//===----------------------------------------------------------------------===//
-// Post increment vector stores with register offset
-//===----------------------------------------------------------------------===//
-let isPredicable = 1 in
-class T_vstore_ppu <string mnemonic, bit isNT = 0>
- : V6_STInst <(outs IntRegs:$_dst_),
- (ins IntRegs:$src1, ModRegs:$src2, VectorRegs:$src3),
- mnemonic#"($src1++$src2)"#!if(isNT, ":nt", "")#" = $src3", [],
- "$src1 = $_dst_">, NewValueRel;
-
-let isNVStorable = 1, BaseOpcode = "vS32b_ppu" in {
- def V6_vS32b_ppu : T_vstore_ppu <"vmem">,
- V6_vS32b_ppu_enc;
- let isNonTemporal = 1, BaseOpcode = "vS32b_ppu" in
- def V6_vS32b_nt_ppu : T_vstore_ppu <"vmem", 1>,
- V6_vS32b_nt_ppu_enc;
-}
-
-let BaseOpcode = "vS32Ub_ppu", Itinerary = CVI_VM_STU, Type = TypeCVI_VM_STU in
-def V6_vS32Ub_ppu : T_vstore_ppu <"vmemu">, V6_vS32Ub_ppu_enc;
-
-//===----------------------------------------------------------------------===//
-// Post increment .new vector stores with register offset
-//===----------------------------------------------------------------------===//
-let Itinerary = CVI_VM_NEW_ST, Type = TypeCVI_VM_NEW_ST, isNewValue = 1,
- isPredicable = 1, opNewValue = 3, isNVStore = 1 in
-class T_vstore_new_ppu <bit isNT = 0>
- : V6_STInst <(outs IntRegs:$_dst_),
- (ins IntRegs:$src1, ModRegs:$src2, VectorRegs:$src3),
- "vmem($src1++$src2)"#!if(isNT, ":nt", "")#" = $src3.new", [],
- "$src1 = $_dst_">, NewValueRel;
-
-let BaseOpcode = "vS32b_ppu" in
-def V6_vS32b_new_ppu : T_vstore_new_ppu, V6_vS32b_new_ppu_enc;
-
-let BaseOpcode = "vS32b_ppu", isNonTemporal = 1 in
-def V6_vS32b_nt_new_ppu : T_vstore_new_ppu<1>, V6_vS32b_nt_new_ppu_enc;
-
-//===----------------------------------------------------------------------===//
-// Post increment conditional .new vector stores with register offset
-//===----------------------------------------------------------------------===//
-let isPredicated = 1 in
-class T_vstore_pred_ppu <string mnemonic, bit isPredNot = 0, bit isNT = 0>
- : V6_STInst<(outs IntRegs:$_dst_),
- (ins PredRegs:$src1, IntRegs:$src2, ModRegs:$src3, VectorRegs:$src4),
- "if ("#!if(isPredNot, "!", "")#"$src1) "#mnemonic#"($src2++$src3)"
- #!if(isNT, ":nt", "")#" = $src4", [],
- "$src2 = $_dst_">, NewValueRel {
- let isPredicatedFalse = isPredNot;
-}
-
-let isNVStorable = 1, BaseOpcode = "vS32b_ppu" in {
- def V6_vS32b_pred_ppu : T_vstore_pred_ppu<"vmem">, V6_vS32b_pred_ppu_enc;
- def V6_vS32b_npred_ppu: T_vstore_pred_ppu<"vmem", 1>, V6_vS32b_npred_ppu_enc;
-}
-
-let isNVStorable = 1, BaseOpcode = "vS32b_ppu", isNonTemporal = 1 in {
- def V6_vS32b_nt_pred_ppu : T_vstore_pred_ppu <"vmem", 0, 1>,
- V6_vS32b_nt_pred_ppu_enc;
- def V6_vS32b_nt_npred_ppu : T_vstore_pred_ppu <"vmem", 1, 1>,
- V6_vS32b_nt_npred_ppu_enc;
-}
-
-let BaseOpcode = "vS32Ub_ppu", Itinerary = CVI_VM_STU,
- Type = TypeCVI_VM_STU in {
- def V6_vS32Ub_pred_ppu : T_vstore_pred_ppu <"vmemu">,
- V6_vS32Ub_pred_ppu_enc;
- def V6_vS32Ub_npred_ppu : T_vstore_pred_ppu <"vmemu", 1>,
- V6_vS32Ub_npred_ppu_enc;
-}
-
-//===----------------------------------------------------------------------===//
-// Post increment vector stores with register offset - byte-enabled aligned
-//===----------------------------------------------------------------------===//
-class T_vstore_qpred_ppu <bit isPredNot = 0, bit isNT = 0>
- : V6_STInst <(outs IntRegs:$_dst_),
- (ins VecPredRegs:$src1, IntRegs:$src2, ModRegs:$src3, VectorRegs:$src4),
- "if ("#!if(isPredNot, "!", "")#"$src1) vmem($src2++$src3)"
- #!if(isNT, ":nt", "")#" = $src4", [],
- "$src2 = $_dst_">, NewValueRel;
-
-def V6_vS32b_qpred_ppu : T_vstore_qpred_ppu, V6_vS32b_qpred_ppu_enc;
-def V6_vS32b_nqpred_ppu : T_vstore_qpred_ppu<1>, V6_vS32b_nqpred_ppu_enc;
-def V6_vS32b_nt_qpred_ppu : T_vstore_qpred_ppu<0, 1>,
- V6_vS32b_nt_qpred_ppu_enc;
-def V6_vS32b_nt_nqpred_ppu : T_vstore_qpred_ppu<1, 1>,
- V6_vS32b_nt_nqpred_ppu_enc;
-
-//===----------------------------------------------------------------------===//
-// Post increment conditional .new vector stores with register offset
-//===----------------------------------------------------------------------===//
-let Itinerary = CVI_VM_NEW_ST, Type = TypeCVI_VM_NEW_ST, isPredicated = 1,
- isNewValue = 1, opNewValue = 4, isNVStore = 1 in
-class T_vstore_new_pred_ppu <bit isPredNot = 0, bit isNT = 0>
- : V6_STInst <(outs IntRegs:$_dst_),
- (ins PredRegs:$src1, IntRegs:$src2, ModRegs:$src3, VectorRegs:$src4),
- "if("#!if(isPredNot, "!", "")#"$src1) vmem($src2++$src3)"
- #!if(isNT, ":nt", "")#" = $src4.new", [],
- "$src2 = $_dst_">, NewValueRel {
- let isPredicatedFalse = isPredNot;
-}
-
-let BaseOpcode = "vS32b_ppu" in {
- def V6_vS32b_new_pred_ppu : T_vstore_new_pred_ppu,
- V6_vS32b_new_pred_ppu_enc;
- def V6_vS32b_new_npred_ppu : T_vstore_new_pred_ppu<1>,
- V6_vS32b_new_npred_ppu_enc;
-}
-
-let BaseOpcode = "vS32b_ppu", isNonTemporal = 1 in {
-def V6_vS32b_nt_new_pred_ppu : T_vstore_new_pred_ppu<0, 1>,
- V6_vS32b_nt_new_pred_ppu_enc;
-def V6_vS32b_nt_new_npred_ppu : T_vstore_new_pred_ppu<1, 1>,
- V6_vS32b_nt_new_npred_ppu_enc;
-}
-
-
-// Vector load/store pseudos
-
-let isPseudo = 1, isCodeGenOnly = 1, validSubTargets = HasV60SubT in
-class STrivv_template<RegisterClass RC>
- : V6_STInst<(outs), (ins IntRegs:$addr, s32_0Imm:$off, RC:$src), "", []>;
-
-def PS_vstorerw_ai: STrivv_template<VecDblRegs>,
- Requires<[HasV60T,UseHVXSgl]>;
-def PS_vstorerwu_ai: STrivv_template<VecDblRegs>,
- Requires<[HasV60T,UseHVXSgl]>;
-def PS_vstorerw_ai_128B: STrivv_template<VecDblRegs128B>,
- Requires<[HasV60T,UseHVXDbl]>;
-def PS_vstorerwu_ai_128B: STrivv_template<VecDblRegs128B>,
- Requires<[HasV60T,UseHVXDbl]>;
-
-
-let isPseudo = 1, isCodeGenOnly = 1, validSubTargets = HasV60SubT in
-class LDrivv_template<RegisterClass RC>
- : V6_LDInst<(outs RC:$dst), (ins IntRegs:$addr, s32_0Imm:$off), "", []>;
-
-def PS_vloadrw_ai: LDrivv_template<VecDblRegs>,
- Requires<[HasV60T,UseHVXSgl]>;
-def PS_vloadrwu_ai: LDrivv_template<VecDblRegs>,
- Requires<[HasV60T,UseHVXSgl]>;
-def PS_vloadrw_ai_128B: LDrivv_template<VecDblRegs128B>,
- Requires<[HasV60T,UseHVXDbl]>;
-def PS_vloadrwu_ai_128B: LDrivv_template<VecDblRegs128B>,
- Requires<[HasV60T,UseHVXDbl]>;
-
-// Store vector predicate pseudo.
-let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 13,
- isCodeGenOnly = 1, isPseudo = 1, mayStore = 1, hasSideEffects = 0 in {
- def PS_vstorerq_ai : STInst<(outs),
- (ins IntRegs:$base, s32_0Imm:$offset, VecPredRegs:$src1),
- ".error \"should not emit\"", []>,
- Requires<[HasV60T,UseHVXSgl]>;
- def PS_vstorerq_ai_128B : STInst<(outs),
- (ins IntRegs:$base, s32_0Imm:$offset, VecPredRegs128B:$src1),
- ".error \"should not emit\"", []>,
- Requires<[HasV60T,UseHVXDbl]>;
-}
-
-// Load vector predicate pseudo.
-let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 13,
- opExtentAlign = 2, isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in {
- def PS_vloadrq_ai : LDInst<(outs VecPredRegs:$dst),
- (ins IntRegs:$base, s32_0Imm:$offset),
- ".error \"should not emit\"", []>,
- Requires<[HasV60T,UseHVXSgl]>;
- def PS_vloadrq_ai_128B : LDInst<(outs VecPredRegs128B:$dst),
- (ins IntRegs:$base, s32_0Imm:$offset),
- ".error \"should not emit\"", []>,
- Requires<[HasV60T,UseHVXDbl]>;
-}
-
-class VSELInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
- string cstr = "", InstrItinClass itin = CVI_VA_DV,
- IType type = TypeCVI_VA_DV>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, type>;
-
-let isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in {
- def PS_vselect: VSELInst<(outs VectorRegs:$dst),
- (ins PredRegs:$src1, VectorRegs:$src2, VectorRegs:$src3), "", []>,
- Requires<[HasV60T,UseHVXSgl]>;
- def PS_vselect_128B: VSELInst<(outs VectorRegs128B:$dst),
- (ins PredRegs:$src1, VectorRegs128B:$src2, VectorRegs128B:$src3),
- "", []>, Requires<[HasV60T,UseHVXDbl]>;
- def PS_wselect: VSELInst<(outs VecDblRegs:$dst),
- (ins PredRegs:$src1, VecDblRegs:$src2, VecDblRegs:$src3), "", []>,
- Requires<[HasV60T,UseHVXSgl]>;
- def PS_wselect_128B: VSELInst<(outs VecDblRegs128B:$dst),
- (ins PredRegs:$src1, VecDblRegs128B:$src2, VecDblRegs128B:$src3),
- "", []>, Requires<[HasV60T,UseHVXDbl]>;
-}
-
-let hasNewValue = 1 in
-class T_vmpy <string asmString, RegisterClass RCout, RegisterClass RCin>
- : CVI_VX_DV_Resource1<(outs RCout:$dst), (ins RCin:$src1, IntRegs:$src2),
- asmString >;
-
-multiclass T_vmpy <string asmString, RegisterClass RCout,
- RegisterClass RCin> {
- def NAME : T_vmpy <asmString, RCout, RCin>;
- let isCodeGenOnly = 1 in
- def NAME#_128B : T_vmpy <asmString, !cast<RegisterClass>(RCout#"128B"),
- !cast<RegisterClass>(RCin#"128B")>;
-}
-
-multiclass T_vmpy_VV <string asmString>:
- T_vmpy <asmString, VectorRegs, VectorRegs>;
-
-multiclass T_vmpy_WW <string asmString>:
- T_vmpy <asmString, VecDblRegs, VecDblRegs>;
-
-multiclass T_vmpy_VW <string asmString>:
- T_vmpy <asmString, VectorRegs, VecDblRegs>;
-
-multiclass T_vmpy_WV <string asmString>:
- T_vmpy <asmString, VecDblRegs, VectorRegs>;
-
-defm V6_vtmpyb :T_vmpy_WW<"$dst.h = vtmpy($src1.b,$src2.b)">, V6_vtmpyb_enc;
-defm V6_vtmpybus :T_vmpy_WW<"$dst.h = vtmpy($src1.ub,$src2.b)">, V6_vtmpybus_enc;
-defm V6_vdsaduh :T_vmpy_WW<"$dst.uw = vdsad($src1.uh,$src2.uh)">, V6_vdsaduh_enc;
-defm V6_vmpybus :T_vmpy_WV<"$dst.h = vmpy($src1.ub,$src2.b)">, V6_vmpybus_enc;
-defm V6_vmpabus :T_vmpy_WW<"$dst.h = vmpa($src1.ub,$src2.b)">, V6_vmpabus_enc;
-defm V6_vmpahb :T_vmpy_WW<"$dst.w = vmpa($src1.h,$src2.b)">, V6_vmpahb_enc;
-defm V6_vmpyh :T_vmpy_WV<"$dst.w = vmpy($src1.h,$src2.h)">, V6_vmpyh_enc;
-defm V6_vmpyuh :T_vmpy_WV<"$dst.uw = vmpy($src1.uh,$src2.uh)">, V6_vmpyuh_enc;
-defm V6_vmpyiwh :T_vmpy_VV<"$dst.w = vmpyi($src1.w,$src2.h)">, V6_vmpyiwh_enc;
-defm V6_vtmpyhb :T_vmpy_WW<"$dst.w = vtmpy($src1.h,$src2.b)">, V6_vtmpyhb_enc;
-defm V6_vmpyub :T_vmpy_WV<"$dst.uh = vmpy($src1.ub,$src2.ub)">, V6_vmpyub_enc;
-
-let Itinerary = CVI_VX_LONG, Type = TypeCVI_VX in
-defm V6_vmpyihb :T_vmpy_VV<"$dst.h = vmpyi($src1.h,$src2.b)">, V6_vmpyihb_enc;
-
-defm V6_vdmpybus_dv :
- T_vmpy_WW <"$dst.h = vdmpy($src1.ub,$src2.b)">, V6_vdmpybus_dv_enc;
-defm V6_vdmpyhsusat :
- T_vmpy_VV <"$dst.w = vdmpy($src1.h,$src2.uh):sat">, V6_vdmpyhsusat_enc;
-defm V6_vdmpyhsuisat :
- T_vmpy_VW <"$dst.w = vdmpy($src1.h,$src2.uh,#1):sat">, V6_vdmpyhsuisat_enc;
-defm V6_vdmpyhsat :
- T_vmpy_VV <"$dst.w = vdmpy($src1.h,$src2.h):sat">, V6_vdmpyhsat_enc;
-defm V6_vdmpyhisat :
- T_vmpy_VW <"$dst.w = vdmpy($src1.h,$src2.h):sat">, V6_vdmpyhisat_enc;
-defm V6_vdmpyhb_dv :
- T_vmpy_WW <"$dst.w = vdmpy($src1.h,$src2.b)">, V6_vdmpyhb_dv_enc;
-defm V6_vmpyhss :
- T_vmpy_VV <"$dst.h = vmpy($src1.h,$src2.h):<<1:sat">, V6_vmpyhss_enc;
-defm V6_vmpyhsrs :
- T_vmpy_VV <"$dst.h = vmpy($src1.h,$src2.h):<<1:rnd:sat">, V6_vmpyhsrs_enc;
-
-let Itinerary = CVI_VP, Type = TypeCVI_VP in
-defm V6_vror : T_vmpy_VV <"$dst = vror($src1,$src2)">, V6_vror_enc;
-
-let Itinerary = CVI_VX, Type = TypeCVI_VX in {
-defm V6_vdmpyhb : T_vmpy_VV<"$dst.w = vdmpy($src1.h,$src2.b)">, V6_vdmpyhb_enc;
-defm V6_vrmpybus : T_vmpy_VV<"$dst.w = vrmpy($src1.ub,$src2.b)">, V6_vrmpybus_enc;
-defm V6_vdmpybus : T_vmpy_VV<"$dst.h = vdmpy($src1.ub,$src2.b)">, V6_vdmpybus_enc;
-defm V6_vmpyiwb : T_vmpy_VV<"$dst.w = vmpyi($src1.w,$src2.b)">, V6_vmpyiwb_enc;
-defm V6_vrmpyub : T_vmpy_VV<"$dst.uw = vrmpy($src1.ub,$src2.ub)">, V6_vrmpyub_enc;
-}
-
-let Itinerary = CVI_VS, Type = TypeCVI_VS in {
-defm V6_vasrw : T_vmpy_VV <"$dst.w = vasr($src1.w,$src2)">, V6_vasrw_enc;
-defm V6_vasrh : T_vmpy_VV <"$dst.h = vasr($src1.h,$src2)">, V6_vasrh_enc;
-defm V6_vaslw : T_vmpy_VV <"$dst.w = vasl($src1.w,$src2)">, V6_vaslw_enc;
-defm V6_vaslh : T_vmpy_VV <"$dst.h = vasl($src1.h,$src2)">, V6_vaslh_enc;
-defm V6_vlsrw : T_vmpy_VV <"$dst.uw = vlsr($src1.uw,$src2)">, V6_vlsrw_enc;
-defm V6_vlsrh : T_vmpy_VV <"$dst.uh = vlsr($src1.uh,$src2)">, V6_vlsrh_enc;
-}
-
-let hasNewValue = 1 in
-class T_HVX_alu <string asmString, InstrItinClass itin,
- RegisterClass RCout, RegisterClass RCin>
- : CVI_VA_Resource1 <(outs RCout:$dst), (ins RCin:$src1, RCin:$src2),
- asmString >{
- let Itinerary = itin;
- let Type = !cast<IType>("Type"#itin);
-}
-
-multiclass T_HVX_alu <string asmString, RegisterClass RCout,
- RegisterClass RCin, InstrItinClass itin> {
- def NAME : T_HVX_alu <asmString, itin, RCout, RCin>;
- let isCodeGenOnly = 1 in
- def NAME#_128B : T_HVX_alu <asmString, itin,
- !cast<RegisterClass>(RCout#"128B"),
- !cast<RegisterClass>(RCin#"128B")>;
-}
-
-multiclass T_HVX_alu_VV <string asmString>:
- T_HVX_alu <asmString, VectorRegs, VectorRegs, CVI_VA>;
-
-multiclass T_HVX_alu_WW <string asmString>:
- T_HVX_alu <asmString, VecDblRegs, VecDblRegs, CVI_VA_DV>;
-
-multiclass T_HVX_alu_WV <string asmString>:
- T_HVX_alu <asmString, VecDblRegs, VectorRegs, CVI_VX_DV>;
-
-
-let Itinerary = CVI_VX, Type = TypeCVI_VX in {
-defm V6_vrmpyubv :
- T_HVX_alu_VV <"$dst.uw = vrmpy($src1.ub,$src2.ub)">, V6_vrmpyubv_enc;
-defm V6_vrmpybv :
- T_HVX_alu_VV <"$dst.w = vrmpy($src1.b,$src2.b)">, V6_vrmpybv_enc;
-defm V6_vrmpybusv :
- T_HVX_alu_VV <"$dst.w = vrmpy($src1.ub,$src2.b)">, V6_vrmpybusv_enc;
-defm V6_vabsdiffub :
- T_HVX_alu_VV <"$dst.ub = vabsdiff($src1.ub,$src2.ub)">, V6_vabsdiffub_enc;
-defm V6_vabsdiffh :
- T_HVX_alu_VV <"$dst.uh = vabsdiff($src1.h,$src2.h)">, V6_vabsdiffh_enc;
-defm V6_vabsdiffuh :
- T_HVX_alu_VV <"$dst.uh = vabsdiff($src1.uh,$src2.uh)">, V6_vabsdiffuh_enc;
-defm V6_vabsdiffw :
- T_HVX_alu_VV <"$dst.uw = vabsdiff($src1.w,$src2.w)">, V6_vabsdiffw_enc;
-}
-
-let Itinerary = CVI_VX_DV, Type = TypeCVI_VX_DV in {
-defm V6_vdmpyhvsat :
- T_HVX_alu_VV <"$dst.w = vdmpy($src1.h,$src2.h):sat">, V6_vdmpyhvsat_enc;
-defm V6_vmpyhvsrs :
- T_HVX_alu_VV<"$dst.h = vmpy($src1.h,$src2.h):<<1:rnd:sat">, V6_vmpyhvsrs_enc;
-defm V6_vmpyih :
- T_HVX_alu_VV <"$dst.h = vmpyi($src1.h,$src2.h)">, V6_vmpyih_enc;
-}
-
-defm V6_vand :
- T_HVX_alu_VV <"$dst = vand($src1,$src2)">, V6_vand_enc;
-defm V6_vor :
- T_HVX_alu_VV <"$dst = vor($src1,$src2)">, V6_vor_enc;
-defm V6_vxor :
- T_HVX_alu_VV <"$dst = vxor($src1,$src2)">, V6_vxor_enc;
-defm V6_vaddw :
- T_HVX_alu_VV <"$dst.w = vadd($src1.w,$src2.w)">, V6_vaddw_enc;
-defm V6_vaddubsat :
- T_HVX_alu_VV <"$dst.ub = vadd($src1.ub,$src2.ub):sat">, V6_vaddubsat_enc;
-defm V6_vadduhsat :
- T_HVX_alu_VV <"$dst.uh = vadd($src1.uh,$src2.uh):sat">, V6_vadduhsat_enc;
-defm V6_vaddhsat :
- T_HVX_alu_VV <"$dst.h = vadd($src1.h,$src2.h):sat">, V6_vaddhsat_enc;
-defm V6_vaddwsat :
- T_HVX_alu_VV <"$dst.w = vadd($src1.w,$src2.w):sat">, V6_vaddwsat_enc;
-defm V6_vsubb :
- T_HVX_alu_VV <"$dst.b = vsub($src1.b,$src2.b)">, V6_vsubb_enc;
-defm V6_vsubh :
- T_HVX_alu_VV <"$dst.h = vsub($src1.h,$src2.h)">, V6_vsubh_enc;
-defm V6_vsubw :
- T_HVX_alu_VV <"$dst.w = vsub($src1.w,$src2.w)">, V6_vsubw_enc;
-defm V6_vsububsat :
- T_HVX_alu_VV <"$dst.ub = vsub($src1.ub,$src2.ub):sat">, V6_vsububsat_enc;
-defm V6_vsubuhsat :
- T_HVX_alu_VV <"$dst.uh = vsub($src1.uh,$src2.uh):sat">, V6_vsubuhsat_enc;
-defm V6_vsubhsat :
- T_HVX_alu_VV <"$dst.h = vsub($src1.h,$src2.h):sat">, V6_vsubhsat_enc;
-defm V6_vsubwsat :
- T_HVX_alu_VV <"$dst.w = vsub($src1.w,$src2.w):sat">, V6_vsubwsat_enc;
-defm V6_vavgub :
- T_HVX_alu_VV <"$dst.ub = vavg($src1.ub,$src2.ub)">, V6_vavgub_enc;
-defm V6_vavguh :
- T_HVX_alu_VV <"$dst.uh = vavg($src1.uh,$src2.uh)">, V6_vavguh_enc;
-defm V6_vavgh :
- T_HVX_alu_VV <"$dst.h = vavg($src1.h,$src2.h)">, V6_vavgh_enc;
-defm V6_vavgw :
- T_HVX_alu_VV <"$dst.w = vavg($src1.w,$src2.w)">, V6_vavgw_enc;
-defm V6_vnavgub :
- T_HVX_alu_VV <"$dst.b = vnavg($src1.ub,$src2.ub)">, V6_vnavgub_enc;
-defm V6_vnavgh :
- T_HVX_alu_VV <"$dst.h = vnavg($src1.h,$src2.h)">, V6_vnavgh_enc;
-defm V6_vnavgw :
- T_HVX_alu_VV <"$dst.w = vnavg($src1.w,$src2.w)">, V6_vnavgw_enc;
-defm V6_vavgubrnd :
- T_HVX_alu_VV <"$dst.ub = vavg($src1.ub,$src2.ub):rnd">, V6_vavgubrnd_enc;
-defm V6_vavguhrnd :
- T_HVX_alu_VV <"$dst.uh = vavg($src1.uh,$src2.uh):rnd">, V6_vavguhrnd_enc;
-defm V6_vavghrnd :
- T_HVX_alu_VV <"$dst.h = vavg($src1.h,$src2.h):rnd">, V6_vavghrnd_enc;
-defm V6_vavgwrnd :
- T_HVX_alu_VV <"$dst.w = vavg($src1.w,$src2.w):rnd">, V6_vavgwrnd_enc;
-
-defm V6_vmpybv :
- T_HVX_alu_WV <"$dst.h = vmpy($src1.b,$src2.b)">, V6_vmpybv_enc;
-defm V6_vmpyubv :
- T_HVX_alu_WV <"$dst.uh = vmpy($src1.ub,$src2.ub)">, V6_vmpyubv_enc;
-defm V6_vmpybusv :
- T_HVX_alu_WV <"$dst.h = vmpy($src1.ub,$src2.b)">, V6_vmpybusv_enc;
-defm V6_vmpyhv :
- T_HVX_alu_WV <"$dst.w = vmpy($src1.h,$src2.h)">, V6_vmpyhv_enc;
-defm V6_vmpyuhv :
- T_HVX_alu_WV <"$dst.uw = vmpy($src1.uh,$src2.uh)">, V6_vmpyuhv_enc;
-defm V6_vmpyhus :
- T_HVX_alu_WV <"$dst.w = vmpy($src1.h,$src2.uh)">, V6_vmpyhus_enc;
-defm V6_vaddubh :
- T_HVX_alu_WV <"$dst.h = vadd($src1.ub,$src2.ub)">, V6_vaddubh_enc;
-defm V6_vadduhw :
- T_HVX_alu_WV <"$dst.w = vadd($src1.uh,$src2.uh)">, V6_vadduhw_enc;
-defm V6_vaddhw :
- T_HVX_alu_WV <"$dst.w = vadd($src1.h,$src2.h)">, V6_vaddhw_enc;
-defm V6_vsububh :
- T_HVX_alu_WV <"$dst.h = vsub($src1.ub,$src2.ub)">, V6_vsububh_enc;
-defm V6_vsubuhw :
- T_HVX_alu_WV <"$dst.w = vsub($src1.uh,$src2.uh)">, V6_vsubuhw_enc;
-defm V6_vsubhw :
- T_HVX_alu_WV <"$dst.w = vsub($src1.h,$src2.h)">, V6_vsubhw_enc;
-
-defm V6_vaddb_dv :
- T_HVX_alu_WW <"$dst.b = vadd($src1.b,$src2.b)">, V6_vaddb_dv_enc;
-defm V6_vaddh_dv :
- T_HVX_alu_WW <"$dst.h = vadd($src1.h,$src2.h)">, V6_vaddh_dv_enc;
-defm V6_vaddw_dv :
- T_HVX_alu_WW <"$dst.w = vadd($src1.w,$src2.w)">, V6_vaddw_dv_enc;
-defm V6_vaddubsat_dv :
- T_HVX_alu_WW <"$dst.ub = vadd($src1.ub,$src2.ub):sat">, V6_vaddubsat_dv_enc;
-defm V6_vadduhsat_dv :
- T_HVX_alu_WW <"$dst.uh = vadd($src1.uh,$src2.uh):sat">, V6_vadduhsat_dv_enc;
-defm V6_vaddhsat_dv :
- T_HVX_alu_WW <"$dst.h = vadd($src1.h,$src2.h):sat">, V6_vaddhsat_dv_enc;
-defm V6_vaddwsat_dv :
- T_HVX_alu_WW <"$dst.w = vadd($src1.w,$src2.w):sat">, V6_vaddwsat_dv_enc;
-defm V6_vsubb_dv :
- T_HVX_alu_WW <"$dst.b = vsub($src1.b,$src2.b)">, V6_vsubb_dv_enc;
-defm V6_vsubh_dv :
- T_HVX_alu_WW <"$dst.h = vsub($src1.h,$src2.h)">, V6_vsubh_dv_enc;
-defm V6_vsubw_dv :
- T_HVX_alu_WW <"$dst.w = vsub($src1.w,$src2.w)">, V6_vsubw_dv_enc;
-defm V6_vsububsat_dv :
- T_HVX_alu_WW <"$dst.ub = vsub($src1.ub,$src2.ub):sat">, V6_vsububsat_dv_enc;
-defm V6_vsubuhsat_dv :
- T_HVX_alu_WW <"$dst.uh = vsub($src1.uh,$src2.uh):sat">, V6_vsubuhsat_dv_enc;
-defm V6_vsubhsat_dv :
- T_HVX_alu_WW <"$dst.h = vsub($src1.h,$src2.h):sat">, V6_vsubhsat_dv_enc;
-defm V6_vsubwsat_dv :
- T_HVX_alu_WW <"$dst.w = vsub($src1.w,$src2.w):sat">, V6_vsubwsat_dv_enc;
-
-let Itinerary = CVI_VX_DV_LONG, Type = TypeCVI_VX_DV in {
-defm V6_vmpabusv :
- T_HVX_alu_WW <"$dst.h = vmpa($src1.ub,$src2.b)">, V6_vmpabusv_enc;
-defm V6_vmpabuuv :
- T_HVX_alu_WW <"$dst.h = vmpa($src1.ub,$src2.ub)">, V6_vmpabuuv_enc;
-}
-
-let isAccumulator = 1, hasNewValue = 1 in
-class T_HVX_vmpyacc <string asmString, InstrItinClass itin, RegisterClass RCout,
- RegisterClass RCin1, RegisterClass RCin2>
- : CVI_VA_Resource1 <(outs RCout:$dst),
- (ins RCout:$_src_, RCin1:$src1, RCin2:$src2), asmString,
- [], "$dst = $_src_" > {
- let Itinerary = itin;
- let Type = !cast<IType>("Type"#itin);
-}
-
-multiclass T_HVX_vmpyacc_both <string asmString, RegisterClass RCout,
- RegisterClass RCin1, RegisterClass RCin2, InstrItinClass itin > {
- def NAME : T_HVX_vmpyacc <asmString, itin, RCout, RCin1, RCin2>;
- let isCodeGenOnly = 1 in
- def NAME#_128B : T_HVX_vmpyacc <asmString, itin,
- !cast<RegisterClass>(RCout#"128B"),
- !cast<RegisterClass>(RCin1#"128B"),
- !cast<RegisterClass>(RCin2#
- !if(!eq (!cast<string>(RCin2), "IntRegs"), "", "128B"))>;
-}
-
-multiclass T_HVX_vmpyacc_VVR <string asmString>:
- T_HVX_vmpyacc_both <asmString, VectorRegs, VectorRegs, IntRegs, CVI_VX>;
-
-multiclass T_HVX_vmpyacc_VWR <string asmString>:
- T_HVX_vmpyacc_both <asmString, VectorRegs, VecDblRegs, IntRegs, CVI_VX_DV>;
-
-multiclass T_HVX_vmpyacc_WVR <string asmString>:
- T_HVX_vmpyacc_both <asmString, VecDblRegs, VectorRegs, IntRegs, CVI_VX_DV>;
-
-multiclass T_HVX_vmpyacc_WWR <string asmString>:
- T_HVX_vmpyacc_both <asmString, VecDblRegs, VecDblRegs, IntRegs, CVI_VX_DV>;
-
-multiclass T_HVX_vmpyacc_VVV <string asmString>:
- T_HVX_vmpyacc_both <asmString, VectorRegs, VectorRegs, VectorRegs, CVI_VX_DV>;
-
-multiclass T_HVX_vmpyacc_WVV <string asmString>:
- T_HVX_vmpyacc_both <asmString, VecDblRegs, VectorRegs, VectorRegs, CVI_VX_DV>;
-
-
-defm V6_vtmpyb_acc :
- T_HVX_vmpyacc_WWR <"$dst.h += vtmpy($src1.b,$src2.b)">,
- V6_vtmpyb_acc_enc;
-defm V6_vtmpybus_acc :
- T_HVX_vmpyacc_WWR <"$dst.h += vtmpy($src1.ub,$src2.b)">,
- V6_vtmpybus_acc_enc;
-defm V6_vtmpyhb_acc :
- T_HVX_vmpyacc_WWR <"$dst.w += vtmpy($src1.h,$src2.b)">,
- V6_vtmpyhb_acc_enc;
-defm V6_vdmpyhb_acc :
- T_HVX_vmpyacc_VVR <"$dst.w += vdmpy($src1.h,$src2.b)">,
- V6_vdmpyhb_acc_enc;
-defm V6_vrmpyub_acc :
- T_HVX_vmpyacc_VVR <"$dst.uw += vrmpy($src1.ub,$src2.ub)">,
- V6_vrmpyub_acc_enc;
-defm V6_vrmpybus_acc :
- T_HVX_vmpyacc_VVR <"$dst.w += vrmpy($src1.ub,$src2.b)">,
- V6_vrmpybus_acc_enc;
-defm V6_vdmpybus_acc :
- T_HVX_vmpyacc_VVR <"$dst.h += vdmpy($src1.ub,$src2.b)">,
- V6_vdmpybus_acc_enc;
-defm V6_vdmpybus_dv_acc :
- T_HVX_vmpyacc_WWR <"$dst.h += vdmpy($src1.ub,$src2.b)">,
- V6_vdmpybus_dv_acc_enc;
-defm V6_vdmpyhsuisat_acc :
- T_HVX_vmpyacc_VWR <"$dst.w += vdmpy($src1.h,$src2.uh,#1):sat">,
- V6_vdmpyhsuisat_acc_enc;
-defm V6_vdmpyhisat_acc :
- T_HVX_vmpyacc_VWR <"$dst.w += vdmpy($src1.h,$src2.h):sat">,
- V6_vdmpyhisat_acc_enc;
-defm V6_vdmpyhb_dv_acc :
- T_HVX_vmpyacc_WWR <"$dst.w += vdmpy($src1.h,$src2.b)">,
- V6_vdmpyhb_dv_acc_enc;
-defm V6_vmpybus_acc :
- T_HVX_vmpyacc_WVR <"$dst.h += vmpy($src1.ub,$src2.b)">,
- V6_vmpybus_acc_enc;
-defm V6_vmpabus_acc :
- T_HVX_vmpyacc_WWR <"$dst.h += vmpa($src1.ub,$src2.b)">,
- V6_vmpabus_acc_enc;
-defm V6_vmpahb_acc :
- T_HVX_vmpyacc_WWR <"$dst.w += vmpa($src1.h,$src2.b)">,
- V6_vmpahb_acc_enc;
-defm V6_vmpyhsat_acc :
- T_HVX_vmpyacc_WVR <"$dst.w += vmpy($src1.h,$src2.h):sat">,
- V6_vmpyhsat_acc_enc;
-defm V6_vmpyuh_acc :
- T_HVX_vmpyacc_WVR <"$dst.uw += vmpy($src1.uh,$src2.uh)">,
- V6_vmpyuh_acc_enc;
-defm V6_vmpyiwb_acc :
- T_HVX_vmpyacc_VVR <"$dst.w += vmpyi($src1.w,$src2.b)">,
- V6_vmpyiwb_acc_enc;
-defm V6_vdsaduh_acc :
- T_HVX_vmpyacc_WWR <"$dst.uw += vdsad($src1.uh,$src2.uh)">,
- V6_vdsaduh_acc_enc;
-defm V6_vmpyihb_acc :
- T_HVX_vmpyacc_VVR <"$dst.h += vmpyi($src1.h,$src2.b)">,
- V6_vmpyihb_acc_enc;
-defm V6_vmpyub_acc :
- T_HVX_vmpyacc_WVR <"$dst.uh += vmpy($src1.ub,$src2.ub)">,
- V6_vmpyub_acc_enc;
-
-let Itinerary = CVI_VX_DV, Type = TypeCVI_VX_DV in {
-defm V6_vdmpyhsusat_acc :
- T_HVX_vmpyacc_VVR <"$dst.w += vdmpy($src1.h,$src2.uh):sat">,
- V6_vdmpyhsusat_acc_enc;
-defm V6_vdmpyhsat_acc :
- T_HVX_vmpyacc_VVR <"$dst.w += vdmpy($src1.h,$src2.h):sat">,
- V6_vdmpyhsat_acc_enc;
-defm V6_vmpyiwh_acc : T_HVX_vmpyacc_VVR
- <"$dst.w += vmpyi($src1.w,$src2.h)">, V6_vmpyiwh_acc_enc;
-}
-
-let Itinerary = CVI_VS, Type = TypeCVI_VS in {
-defm V6_vaslw_acc :
- T_HVX_vmpyacc_VVR <"$dst.w += vasl($src1.w,$src2)">, V6_vaslw_acc_enc;
-defm V6_vasrw_acc :
- T_HVX_vmpyacc_VVR <"$dst.w += vasr($src1.w,$src2)">, V6_vasrw_acc_enc;
-}
-
-defm V6_vdmpyhvsat_acc :
- T_HVX_vmpyacc_VVV <"$dst.w += vdmpy($src1.h,$src2.h):sat">,
- V6_vdmpyhvsat_acc_enc;
-defm V6_vmpybusv_acc :
- T_HVX_vmpyacc_WVV <"$dst.h += vmpy($src1.ub,$src2.b)">,
- V6_vmpybusv_acc_enc;
-defm V6_vmpybv_acc :
- T_HVX_vmpyacc_WVV <"$dst.h += vmpy($src1.b,$src2.b)">, V6_vmpybv_acc_enc;
-defm V6_vmpyhus_acc :
- T_HVX_vmpyacc_WVV <"$dst.w += vmpy($src1.h,$src2.uh)">, V6_vmpyhus_acc_enc;
-defm V6_vmpyhv_acc :
- T_HVX_vmpyacc_WVV <"$dst.w += vmpy($src1.h,$src2.h)">, V6_vmpyhv_acc_enc;
-defm V6_vmpyiewh_acc :
- T_HVX_vmpyacc_VVV <"$dst.w += vmpyie($src1.w,$src2.h)">,
- V6_vmpyiewh_acc_enc;
-defm V6_vmpyiewuh_acc :
- T_HVX_vmpyacc_VVV <"$dst.w += vmpyie($src1.w,$src2.uh)">,
- V6_vmpyiewuh_acc_enc;
-defm V6_vmpyih_acc :
- T_HVX_vmpyacc_VVV <"$dst.h += vmpyi($src1.h,$src2.h)">, V6_vmpyih_acc_enc;
-defm V6_vmpyowh_rnd_sacc :
- T_HVX_vmpyacc_VVV <"$dst.w += vmpyo($src1.w,$src2.h):<<1:rnd:sat:shift">,
- V6_vmpyowh_rnd_sacc_enc;
-defm V6_vmpyowh_sacc :
- T_HVX_vmpyacc_VVV <"$dst.w += vmpyo($src1.w,$src2.h):<<1:sat:shift">,
- V6_vmpyowh_sacc_enc;
-defm V6_vmpyubv_acc :
- T_HVX_vmpyacc_WVV <"$dst.uh += vmpy($src1.ub,$src2.ub)">,
- V6_vmpyubv_acc_enc;
-defm V6_vmpyuhv_acc :
- T_HVX_vmpyacc_WVV <"$dst.uw += vmpy($src1.uh,$src2.uh)">,
- V6_vmpyuhv_acc_enc;
-defm V6_vrmpybusv_acc :
- T_HVX_vmpyacc_VVV <"$dst.w += vrmpy($src1.ub,$src2.b)">,
- V6_vrmpybusv_acc_enc;
-defm V6_vrmpybv_acc :
- T_HVX_vmpyacc_VVV <"$dst.w += vrmpy($src1.b,$src2.b)">, V6_vrmpybv_acc_enc;
-defm V6_vrmpyubv_acc :
- T_HVX_vmpyacc_VVV <"$dst.uw += vrmpy($src1.ub,$src2.ub)">,
- V6_vrmpyubv_acc_enc;
-
-
-class T_HVX_vcmp <string asmString, RegisterClass RCout, RegisterClass RCin>
- : CVI_VA_Resource1 <(outs RCout:$dst),
- (ins RCout:$_src_, RCin:$src1, RCin:$src2), asmString,
- [], "$dst = $_src_" > {
- let Itinerary = CVI_VA;
- let Type = TypeCVI_VA;
-}
-
-multiclass T_HVX_vcmp <string asmString> {
- def NAME : T_HVX_vcmp <asmString, VecPredRegs, VectorRegs>;
- let isCodeGenOnly = 1 in
- def NAME#_128B : T_HVX_vcmp <asmString, VecPredRegs128B, VectorRegs128B>;
-}
-
-defm V6_veqb_and :
- T_HVX_vcmp <"$dst &= vcmp.eq($src1.b,$src2.b)">, V6_veqb_and_enc;
-defm V6_veqh_and :
- T_HVX_vcmp <"$dst &= vcmp.eq($src1.h,$src2.h)">, V6_veqh_and_enc;
-defm V6_veqw_and :
- T_HVX_vcmp <"$dst &= vcmp.eq($src1.w,$src2.w)">, V6_veqw_and_enc;
-defm V6_vgtb_and :
- T_HVX_vcmp <"$dst &= vcmp.gt($src1.b,$src2.b)">, V6_vgtb_and_enc;
-defm V6_vgth_and :
- T_HVX_vcmp <"$dst &= vcmp.gt($src1.h,$src2.h)">, V6_vgth_and_enc;
-defm V6_vgtw_and :
- T_HVX_vcmp <"$dst &= vcmp.gt($src1.w,$src2.w)">, V6_vgtw_and_enc;
-defm V6_vgtub_and :
- T_HVX_vcmp <"$dst &= vcmp.gt($src1.ub,$src2.ub)">, V6_vgtub_and_enc;
-defm V6_vgtuh_and :
- T_HVX_vcmp <"$dst &= vcmp.gt($src1.uh,$src2.uh)">, V6_vgtuh_and_enc;
-defm V6_vgtuw_and :
- T_HVX_vcmp <"$dst &= vcmp.gt($src1.uw,$src2.uw)">, V6_vgtuw_and_enc;
-defm V6_veqb_or :
- T_HVX_vcmp <"$dst |= vcmp.eq($src1.b,$src2.b)">, V6_veqb_or_enc;
-defm V6_veqh_or :
- T_HVX_vcmp <"$dst |= vcmp.eq($src1.h,$src2.h)">, V6_veqh_or_enc;
-defm V6_veqw_or :
- T_HVX_vcmp <"$dst |= vcmp.eq($src1.w,$src2.w)">, V6_veqw_or_enc;
-defm V6_vgtb_or :
- T_HVX_vcmp <"$dst |= vcmp.gt($src1.b,$src2.b)">, V6_vgtb_or_enc;
-defm V6_vgth_or :
- T_HVX_vcmp <"$dst |= vcmp.gt($src1.h,$src2.h)">, V6_vgth_or_enc;
-defm V6_vgtw_or :
- T_HVX_vcmp <"$dst |= vcmp.gt($src1.w,$src2.w)">, V6_vgtw_or_enc;
-defm V6_vgtub_or :
- T_HVX_vcmp <"$dst |= vcmp.gt($src1.ub,$src2.ub)">, V6_vgtub_or_enc;
-defm V6_vgtuh_or :
- T_HVX_vcmp <"$dst |= vcmp.gt($src1.uh,$src2.uh)">, V6_vgtuh_or_enc;
-defm V6_vgtuw_or :
- T_HVX_vcmp <"$dst |= vcmp.gt($src1.uw,$src2.uw)">, V6_vgtuw_or_enc;
-defm V6_veqb_xor :
- T_HVX_vcmp <"$dst ^= vcmp.eq($src1.b,$src2.b)">, V6_veqb_xor_enc;
-defm V6_veqh_xor :
- T_HVX_vcmp <"$dst ^= vcmp.eq($src1.h,$src2.h)">, V6_veqh_xor_enc;
-defm V6_veqw_xor :
- T_HVX_vcmp <"$dst ^= vcmp.eq($src1.w,$src2.w)">, V6_veqw_xor_enc;
-defm V6_vgtb_xor :
- T_HVX_vcmp <"$dst ^= vcmp.gt($src1.b,$src2.b)">, V6_vgtb_xor_enc;
-defm V6_vgth_xor :
- T_HVX_vcmp <"$dst ^= vcmp.gt($src1.h,$src2.h)">, V6_vgth_xor_enc;
-defm V6_vgtw_xor :
- T_HVX_vcmp <"$dst ^= vcmp.gt($src1.w,$src2.w)">, V6_vgtw_xor_enc;
-defm V6_vgtub_xor :
- T_HVX_vcmp <"$dst ^= vcmp.gt($src1.ub,$src2.ub)">, V6_vgtub_xor_enc;
-defm V6_vgtuh_xor :
- T_HVX_vcmp <"$dst ^= vcmp.gt($src1.uh,$src2.uh)">, V6_vgtuh_xor_enc;
-defm V6_vgtuw_xor :
- T_HVX_vcmp <"$dst ^= vcmp.gt($src1.uw,$src2.uw)">, V6_vgtuw_xor_enc;
-
-defm V6_vminub :
- T_HVX_alu_VV <"$dst.ub = vmin($src1.ub,$src2.ub)">, V6_vminub_enc;
-defm V6_vminuh :
- T_HVX_alu_VV <"$dst.uh = vmin($src1.uh,$src2.uh)">, V6_vminuh_enc;
-defm V6_vminh :
- T_HVX_alu_VV <"$dst.h = vmin($src1.h,$src2.h)">, V6_vminh_enc;
-defm V6_vminw :
- T_HVX_alu_VV <"$dst.w = vmin($src1.w,$src2.w)">, V6_vminw_enc;
-defm V6_vmaxub :
- T_HVX_alu_VV <"$dst.ub = vmax($src1.ub,$src2.ub)">, V6_vmaxub_enc;
-defm V6_vmaxuh :
- T_HVX_alu_VV <"$dst.uh = vmax($src1.uh,$src2.uh)">, V6_vmaxuh_enc;
-defm V6_vmaxh :
- T_HVX_alu_VV <"$dst.h = vmax($src1.h,$src2.h)">, V6_vmaxh_enc;
-defm V6_vmaxw :
- T_HVX_alu_VV <"$dst.w = vmax($src1.w,$src2.w)">, V6_vmaxw_enc;
-defm V6_vshuffeb :
- T_HVX_alu_VV <"$dst.b = vshuffe($src1.b,$src2.b)">, V6_vshuffeb_enc;
-defm V6_vshuffob :
- T_HVX_alu_VV <"$dst.b = vshuffo($src1.b,$src2.b)">, V6_vshuffob_enc;
-defm V6_vshufeh :
- T_HVX_alu_VV <"$dst.h = vshuffe($src1.h,$src2.h)">, V6_vshufeh_enc;
-defm V6_vshufoh :
- T_HVX_alu_VV <"$dst.h = vshuffo($src1.h,$src2.h)">, V6_vshufoh_enc;
-
-let Itinerary = CVI_VX_DV, Type = TypeCVI_VX_DV in {
-defm V6_vmpyowh_rnd :
- T_HVX_alu_VV <"$dst.w = vmpyo($src1.w,$src2.h):<<1:rnd:sat">,
- V6_vmpyowh_rnd_enc;
-defm V6_vmpyiewuh :
- T_HVX_alu_VV <"$dst.w = vmpyie($src1.w,$src2.uh)">, V6_vmpyiewuh_enc;
-defm V6_vmpyewuh :
- T_HVX_alu_VV <"$dst.w = vmpye($src1.w,$src2.uh)">, V6_vmpyewuh_enc;
-defm V6_vmpyowh :
- T_HVX_alu_VV <"$dst.w = vmpyo($src1.w,$src2.h):<<1:sat">, V6_vmpyowh_enc;
-defm V6_vmpyiowh :
- T_HVX_alu_VV <"$dst.w = vmpyio($src1.w,$src2.h)">, V6_vmpyiowh_enc;
-}
-let Itinerary = CVI_VX, Type = TypeCVI_VX in
-defm V6_vmpyieoh :
- T_HVX_alu_VV <"$dst.w = vmpyieo($src1.h,$src2.h)">, V6_vmpyieoh_enc;
-
-let Itinerary = CVI_VA_DV, Type = TypeCVI_VA_DV in {
-defm V6_vshufoeh :
- T_HVX_alu_WV <"$dst.h = vshuffoe($src1.h,$src2.h)">, V6_vshufoeh_enc;
-defm V6_vshufoeb :
- T_HVX_alu_WV <"$dst.b = vshuffoe($src1.b,$src2.b)">, V6_vshufoeb_enc;
-}
-
-let isRegSequence = 1, Itinerary = CVI_VA_DV, Type = TypeCVI_VA_DV in
-defm V6_vcombine :
- T_HVX_alu_WV <"$dst = vcombine($src1,$src2)">, V6_vcombine_enc;
-
-let Itinerary = CVI_VINLANESAT, Type = TypeCVI_VINLANESAT in {
-defm V6_vsathub :
- T_HVX_alu_VV <"$dst.ub = vsat($src1.h,$src2.h)">, V6_vsathub_enc;
-defm V6_vsatwh :
- T_HVX_alu_VV <"$dst.h = vsat($src1.w,$src2.w)">, V6_vsatwh_enc;
-}
-
-let Itinerary = CVI_VS, Type = TypeCVI_VS in {
-defm V6_vroundwh :
- T_HVX_alu_VV <"$dst.h = vround($src1.w,$src2.w):sat">, V6_vroundwh_enc;
-defm V6_vroundwuh :
- T_HVX_alu_VV <"$dst.uh = vround($src1.w,$src2.w):sat">, V6_vroundwuh_enc;
-defm V6_vroundhb :
- T_HVX_alu_VV <"$dst.b = vround($src1.h,$src2.h):sat">, V6_vroundhb_enc;
-defm V6_vroundhub :
- T_HVX_alu_VV <"$dst.ub = vround($src1.h,$src2.h):sat">, V6_vroundhub_enc;
-defm V6_vasrwv :
- T_HVX_alu_VV <"$dst.w = vasr($src1.w,$src2.w)">, V6_vasrwv_enc;
-defm V6_vlsrwv :
- T_HVX_alu_VV <"$dst.w = vlsr($src1.w,$src2.w)">, V6_vlsrwv_enc;
-defm V6_vlsrhv :
- T_HVX_alu_VV <"$dst.h = vlsr($src1.h,$src2.h)">, V6_vlsrhv_enc;
-defm V6_vasrhv :
- T_HVX_alu_VV <"$dst.h = vasr($src1.h,$src2.h)">, V6_vasrhv_enc;
-defm V6_vaslwv :
- T_HVX_alu_VV <"$dst.w = vasl($src1.w,$src2.w)">, V6_vaslwv_enc;
-defm V6_vaslhv :
- T_HVX_alu_VV <"$dst.h = vasl($src1.h,$src2.h)">, V6_vaslhv_enc;
-}
-
-defm V6_vaddb :
- T_HVX_alu_VV <"$dst.b = vadd($src1.b,$src2.b)">, V6_vaddb_enc;
-defm V6_vaddh :
- T_HVX_alu_VV <"$dst.h = vadd($src1.h,$src2.h)">, V6_vaddh_enc;
-
-let Itinerary = CVI_VP, Type = TypeCVI_VP in {
-defm V6_vdelta :
- T_HVX_alu_VV <"$dst = vdelta($src1,$src2)">, V6_vdelta_enc;
-defm V6_vrdelta :
- T_HVX_alu_VV <"$dst = vrdelta($src1,$src2)">, V6_vrdelta_enc;
-defm V6_vdealb4w :
- T_HVX_alu_VV <"$dst.b = vdeale($src1.b,$src2.b)">, V6_vdealb4w_enc;
-defm V6_vpackeb :
- T_HVX_alu_VV <"$dst.b = vpacke($src1.h,$src2.h)">, V6_vpackeb_enc;
-defm V6_vpackeh :
- T_HVX_alu_VV <"$dst.h = vpacke($src1.w,$src2.w)">, V6_vpackeh_enc;
-defm V6_vpackhub_sat :
- T_HVX_alu_VV <"$dst.ub = vpack($src1.h,$src2.h):sat">, V6_vpackhub_sat_enc;
-defm V6_vpackhb_sat :
- T_HVX_alu_VV <"$dst.b = vpack($src1.h,$src2.h):sat">, V6_vpackhb_sat_enc;
-defm V6_vpackwuh_sat :
- T_HVX_alu_VV <"$dst.uh = vpack($src1.w,$src2.w):sat">, V6_vpackwuh_sat_enc;
-defm V6_vpackwh_sat :
- T_HVX_alu_VV <"$dst.h = vpack($src1.w,$src2.w):sat">, V6_vpackwh_sat_enc;
-defm V6_vpackob :
- T_HVX_alu_VV <"$dst.b = vpacko($src1.h,$src2.h)">, V6_vpackob_enc;
-defm V6_vpackoh :
- T_HVX_alu_VV <"$dst.h = vpacko($src1.w,$src2.w)">, V6_vpackoh_enc;
-}
-
-let hasNewValue = 1, hasSideEffects = 0 in
-class T_HVX_condALU <string asmString, RegisterClass RC1, RegisterClass RC2>
- : CVI_VA_Resource1 <(outs RC2:$dst),
- (ins RC1:$src1, RC2:$_src_, RC2:$src2), asmString,
- [], "$dst = $_src_" > {
- let Itinerary = CVI_VA;
- let Type = TypeCVI_VA;
-}
-
-multiclass T_HVX_condALU <string asmString> {
- def NAME : T_HVX_condALU <asmString, VecPredRegs, VectorRegs>;
- let isCodeGenOnly = 1 in
- def NAME#_128B : T_HVX_condALU <asmString, VecPredRegs128B, VectorRegs128B>;
-}
-
-defm V6_vaddbq : T_HVX_condALU <"if ($src1) $dst.b += $src2.b">,
- V6_vaddbq_enc;
-defm V6_vaddhq : T_HVX_condALU <"if ($src1) $dst.h += $src2.h">,
- V6_vaddhq_enc;
-defm V6_vaddwq : T_HVX_condALU <"if ($src1) $dst.w += $src2.w">,
- V6_vaddwq_enc;
-defm V6_vsubbq : T_HVX_condALU <"if ($src1) $dst.b -= $src2.b">,
- V6_vsubbq_enc;
-defm V6_vsubhq : T_HVX_condALU <"if ($src1) $dst.h -= $src2.h">,
- V6_vsubhq_enc;
-defm V6_vsubwq : T_HVX_condALU <"if ($src1) $dst.w -= $src2.w">,
- V6_vsubwq_enc;
-defm V6_vaddbnq : T_HVX_condALU <"if (!$src1) $dst.b += $src2.b">,
- V6_vaddbnq_enc;
-defm V6_vaddhnq : T_HVX_condALU <"if (!$src1) $dst.h += $src2.h">,
- V6_vaddhnq_enc;
-defm V6_vaddwnq : T_HVX_condALU <"if (!$src1) $dst.w += $src2.w">,
- V6_vaddwnq_enc;
-defm V6_vsubbnq : T_HVX_condALU <"if (!$src1) $dst.b -= $src2.b">,
- V6_vsubbnq_enc;
-defm V6_vsubhnq : T_HVX_condALU <"if (!$src1) $dst.h -= $src2.h">,
- V6_vsubhnq_enc;
-defm V6_vsubwnq : T_HVX_condALU <"if (!$src1) $dst.w -= $src2.w">,
- V6_vsubwnq_enc;
-
-let hasNewValue = 1 in
-class T_HVX_alu_2op <string asmString, InstrItinClass itin,
- RegisterClass RCout, RegisterClass RCin>
- : CVI_VA_Resource1 <(outs RCout:$dst), (ins RCin:$src1),
- asmString >{
- let Itinerary = itin;
- let Type = !cast<IType>("Type"#itin);
-}
-
-multiclass T_HVX_alu_2op <string asmString, RegisterClass RCout,
- RegisterClass RCin, InstrItinClass itin> {
- def NAME : T_HVX_alu_2op <asmString, itin, RCout, RCin>;
- let isCodeGenOnly = 1 in
- def NAME#_128B : T_HVX_alu_2op <asmString, itin,
- !cast<RegisterClass>(RCout#"128B"),
- !cast<RegisterClass>(RCin#"128B")>;
-}
-
-let hasNewValue = 1 in
-multiclass T_HVX_alu_2op_VV <string asmString>:
- T_HVX_alu_2op <asmString, VectorRegs, VectorRegs, CVI_VA>;
-
-multiclass T_HVX_alu_2op_WV <string asmString>:
- T_HVX_alu_2op <asmString, VecDblRegs, VectorRegs, CVI_VA_DV>;
-
-
-defm V6_vabsh : T_HVX_alu_2op_VV <"$dst.h = vabs($src1.h)">,
- V6_vabsh_enc;
-defm V6_vabsw : T_HVX_alu_2op_VV <"$dst.w = vabs($src1.w)">,
- V6_vabsw_enc;
-defm V6_vabsh_sat : T_HVX_alu_2op_VV <"$dst.h = vabs($src1.h):sat">,
- V6_vabsh_sat_enc;
-defm V6_vabsw_sat : T_HVX_alu_2op_VV <"$dst.w = vabs($src1.w):sat">,
- V6_vabsw_sat_enc;
-defm V6_vnot : T_HVX_alu_2op_VV <"$dst = vnot($src1)">,
- V6_vnot_enc;
-defm V6_vassign : T_HVX_alu_2op_VV <"$dst = $src1">,
- V6_vassign_enc;
-
-defm V6_vzb : T_HVX_alu_2op_WV <"$dst.uh = vzxt($src1.ub)">,
- V6_vzb_enc;
-defm V6_vzh : T_HVX_alu_2op_WV <"$dst.uw = vzxt($src1.uh)">,
- V6_vzh_enc;
-defm V6_vsb : T_HVX_alu_2op_WV <"$dst.h = vsxt($src1.b)">,
- V6_vsb_enc;
-defm V6_vsh : T_HVX_alu_2op_WV <"$dst.w = vsxt($src1.h)">,
- V6_vsh_enc;
-
-let Itinerary = CVI_VP, Type = TypeCVI_VP in {
-defm V6_vdealh : T_HVX_alu_2op_VV <"$dst.h = vdeal($src1.h)">,
- V6_vdealh_enc;
-defm V6_vdealb : T_HVX_alu_2op_VV <"$dst.b = vdeal($src1.b)">,
- V6_vdealb_enc;
-defm V6_vshuffh : T_HVX_alu_2op_VV <"$dst.h = vshuff($src1.h)">,
- V6_vshuffh_enc;
-defm V6_vshuffb : T_HVX_alu_2op_VV <"$dst.b = vshuff($src1.b)">,
- V6_vshuffb_enc;
-}
-
-let Itinerary = CVI_VP_VS, Type = TypeCVI_VP_VS in {
-defm V6_vunpackub : T_HVX_alu_2op_WV <"$dst.uh = vunpack($src1.ub)">,
- V6_vunpackub_enc;
-defm V6_vunpackuh : T_HVX_alu_2op_WV <"$dst.uw = vunpack($src1.uh)">,
- V6_vunpackuh_enc;
-defm V6_vunpackb : T_HVX_alu_2op_WV <"$dst.h = vunpack($src1.b)">,
- V6_vunpackb_enc;
-defm V6_vunpackh : T_HVX_alu_2op_WV <"$dst.w = vunpack($src1.h)">,
- V6_vunpackh_enc;
-}
-
-let Itinerary = CVI_VS, Type = TypeCVI_VS in {
-defm V6_vcl0w : T_HVX_alu_2op_VV <"$dst.uw = vcl0($src1.uw)">,
- V6_vcl0w_enc;
-defm V6_vcl0h : T_HVX_alu_2op_VV <"$dst.uh = vcl0($src1.uh)">,
- V6_vcl0h_enc;
-defm V6_vnormamtw : T_HVX_alu_2op_VV <"$dst.w = vnormamt($src1.w)">,
- V6_vnormamtw_enc;
-defm V6_vnormamth : T_HVX_alu_2op_VV <"$dst.h = vnormamt($src1.h)">,
- V6_vnormamth_enc;
-defm V6_vpopcounth : T_HVX_alu_2op_VV <"$dst.h = vpopcount($src1.h)">,
- V6_vpopcounth_enc;
-}
-
-let isAccumulator = 1, hasNewValue = 1, Itinerary = CVI_VX_DV_LONG,
- Type = TypeCVI_VX_DV in
-class T_HVX_vmpyacc2 <string asmString, RegisterClass RC>
- : CVI_VA_Resource1 <(outs RC:$dst),
- (ins RC:$_src_, RC:$src1, IntRegs:$src2, u1_0Imm:$src3),
- asmString, [], "$dst = $_src_" > ;
-
-
-multiclass T_HVX_vmpyacc2 <string asmString> {
- def NAME : T_HVX_vmpyacc2 <asmString, VecDblRegs>;
-
- let isCodeGenOnly = 1 in
- def NAME#_128B : T_HVX_vmpyacc2 <asmString, VecDblRegs128B>;
-}
-
-defm V6_vrmpybusi_acc :
- T_HVX_vmpyacc2<"$dst.w += vrmpy($src1.ub,$src2.b,#$src3)">,
- V6_vrmpybusi_acc_enc;
-defm V6_vrsadubi_acc :
- T_HVX_vmpyacc2<"$dst.uw += vrsad($src1.ub,$src2.ub,#$src3)">,
- V6_vrsadubi_acc_enc;
-defm V6_vrmpyubi_acc :
- T_HVX_vmpyacc2<"$dst.uw += vrmpy($src1.ub,$src2.ub,#$src3)">,
- V6_vrmpyubi_acc_enc;
-
-
-let Itinerary = CVI_VX_DV_LONG, Type = TypeCVI_VX_DV, hasNewValue = 1 in
-class T_HVX_vmpy2 <string asmString, RegisterClass RC>
- : CVI_VA_Resource1<(outs RC:$dst), (ins RC:$src1, IntRegs:$src2, u1_0Imm:$src3),
- asmString>;
-
-
-multiclass T_HVX_vmpy2 <string asmString> {
- def NAME : T_HVX_vmpy2 <asmString, VecDblRegs>;
-
- let isCodeGenOnly = 1 in
- def NAME#_128B : T_HVX_vmpy2 <asmString, VecDblRegs128B>;
-}
-
-defm V6_vrmpybusi :
- T_HVX_vmpy2 <"$dst.w = vrmpy($src1.ub,$src2.b,#$src3)">, V6_vrmpybusi_enc;
-defm V6_vrsadubi :
- T_HVX_vmpy2 <"$dst.uw = vrsad($src1.ub,$src2.ub,#$src3)">, V6_vrsadubi_enc;
-defm V6_vrmpyubi :
- T_HVX_vmpy2 <"$dst.uw = vrmpy($src1.ub,$src2.ub,#$src3)">, V6_vrmpyubi_enc;
-
-
-let Itinerary = CVI_VP_VS_LONG_EARLY, Type = TypeCVI_VP_VS,
- hasSideEffects = 0, hasNewValue2 = 1, opNewValue2 = 1 in
-class T_HVX_perm <string asmString, RegisterClass RC>
- : CVI_VA_Resource1 <(outs RC:$_dst1_, RC:$_dst2_),
- (ins RC:$src1, RC:$src2, IntRegs:$src3),
- asmString, [], "$_dst1_ = $src1, $_dst2_ = $src2" >;
-
-multiclass T_HVX_perm <string asmString> {
- def NAME : T_HVX_perm <asmString, VectorRegs>;
-
- let isCodeGenOnly = 1 in
- def NAME#_128B : T_HVX_perm <asmString, VectorRegs128B>;
-}
-
-let hasNewValue = 1, opNewValue = 0, hasNewValue2 = 1, opNewValue2 = 1 in {
- defm V6_vshuff : T_HVX_perm <"vshuff($src1,$src2,$src3)">, V6_vshuff_enc;
- defm V6_vdeal : T_HVX_perm <"vdeal($src1,$src2,$src3)">, V6_vdeal_enc;
-}
-
-// Conditional vector move.
-let isPredicated = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
-class T_HVX_cmov <bit isPredNot, RegisterClass RC>
- : CVI_VA_Resource1 <(outs RC:$dst), (ins PredRegs:$src1, RC:$src2),
- "if ("#!if(isPredNot, "!", "")#"$src1) $dst = $src2"> {
- let isPredicatedFalse = isPredNot;
-}
-
-multiclass T_HVX_cmov <bit isPredNot = 0> {
- def NAME : T_HVX_cmov <isPredNot, VectorRegs>;
-
- let isCodeGenOnly = 1 in
- def NAME#_128B : T_HVX_cmov <isPredNot, VectorRegs128B>;
-}
-
-defm V6_vcmov : T_HVX_cmov, V6_vcmov_enc;
-defm V6_vncmov : T_HVX_cmov<1>, V6_vncmov_enc;
-
-// Conditional vector combine.
-let Itinerary = CVI_VA_DV, Type = TypeCVI_VA_DV, isPredicated = 1,
- hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
-class T_HVX_ccombine <bit isPredNot, RegisterClass RCout, RegisterClass RCin>
- : CVI_VA_Resource1 < (outs RCout:$dst),
- (ins PredRegs:$src1, RCin:$src2, RCin:$src3),
- "if ("#!if(isPredNot, "!", "")#"$src1) $dst = vcombine($src2,$src3)"> {
- let isPredicatedFalse = isPredNot;
-}
-
-multiclass T_HVX_ccombine <bit isPredNot = 0> {
- def NAME : T_HVX_ccombine <isPredNot, VecDblRegs, VectorRegs>;
-
- let isCodeGenOnly = 1 in
- def NAME#_128B : T_HVX_ccombine <isPredNot, VecDblRegs128B, VectorRegs128B>;
-}
-
-defm V6_vccombine : T_HVX_ccombine, V6_vccombine_enc;
-defm V6_vnccombine : T_HVX_ccombine<1>, V6_vnccombine_enc;
-
-let hasNewValue = 1 in
-class T_HVX_shift <string asmString, RegisterClass RCout, RegisterClass RCin>
- : CVI_VX_DV_Resource1<(outs RCout:$dst),
- (ins RCin:$src1, RCin:$src2, IntRegsLow8:$src3),
- asmString >;
-
-multiclass T_HVX_shift <string asmString, RegisterClass RCout,
- RegisterClass RCin> {
- def NAME : T_HVX_shift <asmString, RCout, RCin>;
- let isCodeGenOnly = 1 in
- def NAME#_128B : T_HVX_shift <asmString, !cast<RegisterClass>(RCout#"128B"),
- !cast<RegisterClass>(RCin#"128B")>;
-}
-
-multiclass T_HVX_shift_VV <string asmString>:
- T_HVX_shift <asmString, VectorRegs, VectorRegs>;
-
-multiclass T_HVX_shift_WV <string asmString>:
- T_HVX_shift <asmString, VecDblRegs, VectorRegs>;
-
-let Itinerary = CVI_VP_LONG, Type = TypeCVI_VP in {
-defm V6_valignb :
- T_HVX_shift_VV <"$dst = valign($src1,$src2,$src3)">, V6_valignb_enc;
-defm V6_vlalignb :
- T_HVX_shift_VV <"$dst = vlalign($src1,$src2,$src3)">, V6_vlalignb_enc;
-}
-
-let Itinerary = CVI_VS, Type = TypeCVI_VS in {
-defm V6_vasrwh :
- T_HVX_shift_VV <"$dst.h = vasr($src1.w,$src2.w,$src3)">, V6_vasrwh_enc;
-defm V6_vasrwhsat :
- T_HVX_shift_VV <"$dst.h = vasr($src1.w,$src2.w,$src3):sat">,
- V6_vasrwhsat_enc;
-defm V6_vasrwhrndsat :
- T_HVX_shift_VV <"$dst.h = vasr($src1.w,$src2.w,$src3):rnd:sat">,
- V6_vasrwhrndsat_enc;
-defm V6_vasrwuhsat :
- T_HVX_shift_VV <"$dst.uh = vasr($src1.w,$src2.w,$src3):sat">,
- V6_vasrwuhsat_enc;
-defm V6_vasrhubsat :
- T_HVX_shift_VV <"$dst.ub = vasr($src1.h,$src2.h,$src3):sat">,
- V6_vasrhubsat_enc;
-defm V6_vasrhubrndsat :
- T_HVX_shift_VV <"$dst.ub = vasr($src1.h,$src2.h,$src3):rnd:sat">,
- V6_vasrhubrndsat_enc;
-defm V6_vasrhbrndsat :
- T_HVX_shift_VV <"$dst.b = vasr($src1.h,$src2.h,$src3):rnd:sat">,
- V6_vasrhbrndsat_enc;
-}
-
-// Assembler mapped -- alias?
-//defm V6_vtran2x2vdd : T_HVX_shift_VV <"">, V6_vtran2x2vdd_enc;
-let Itinerary = CVI_VP_VS_LONG, Type = TypeCVI_VP_VS in {
-defm V6_vshuffvdd :
- T_HVX_shift_WV <"$dst = vshuff($src1,$src2,$src3)">, V6_vshuffvdd_enc;
-defm V6_vdealvdd :
- T_HVX_shift_WV <"$dst = vdeal($src1,$src2,$src3)">, V6_vdealvdd_enc;
-}
-
-let hasNewValue = 1, Itinerary = CVI_VP_VS_LONG, Type = TypeCVI_VP_VS in
-class T_HVX_unpack <string asmString, RegisterClass RCout, RegisterClass RCin>
- : CVI_VX_DV_Resource1<(outs RCout:$dst), (ins RCout:$_src_, RCin:$src1),
- asmString, [], "$dst = $_src_">;
-
-multiclass T_HVX_unpack <string asmString> {
- def NAME : T_HVX_unpack <asmString, VecDblRegs, VectorRegs>;
- let isCodeGenOnly = 1 in
- def NAME#_128B : T_HVX_unpack <asmString, VecDblRegs128B, VectorRegs128B>;
-}
-
-defm V6_vunpackob : T_HVX_unpack <"$dst.h |= vunpacko($src1.b)">, V6_vunpackob_enc;
-defm V6_vunpackoh : T_HVX_unpack <"$dst.w |= vunpacko($src1.h)">, V6_vunpackoh_enc;
-
-let Itinerary = CVI_VP_LONG, Type = TypeCVI_VP, hasNewValue = 1,
- hasSideEffects = 0 in
-class T_HVX_valign <string asmString, RegisterClass RC>
- : CVI_VA_Resource1<(outs RC:$dst), (ins RC:$src1, RC:$src2, u3_0Imm:$src3),
- asmString>;
-
-multiclass T_HVX_valign <string asmString> {
- def NAME : T_HVX_valign <asmString, VectorRegs>;
-
- let isCodeGenOnly = 1 in
- def NAME#_128B : T_HVX_valign <asmString, VectorRegs128B>;
-}
-
-defm V6_valignbi :
- T_HVX_valign <"$dst = valign($src1,$src2,#$src3)">, V6_valignbi_enc;
-defm V6_vlalignbi :
- T_HVX_valign <"$dst = vlalign($src1,$src2,#$src3)">, V6_vlalignbi_enc;
-
-let Itinerary = CVI_VA_DV, Type = TypeCVI_VA_DV in
-class T_HVX_predAlu <string asmString, RegisterClass RC>
- : CVI_VA_Resource1<(outs RC:$dst), (ins RC:$src1, RC:$src2),
- asmString>;
-
-multiclass T_HVX_predAlu <string asmString> {
- def NAME : T_HVX_predAlu <asmString, VecPredRegs>;
-
- let isCodeGenOnly = 1 in
- def NAME#_128B : T_HVX_predAlu <asmString, VecPredRegs128B>;
-}
-
-defm V6_pred_and : T_HVX_predAlu <"$dst = and($src1,$src2)">, V6_pred_and_enc;
-defm V6_pred_or : T_HVX_predAlu <"$dst = or($src1,$src2)">, V6_pred_or_enc;
-defm V6_pred_xor : T_HVX_predAlu <"$dst = xor($src1,$src2)">, V6_pred_xor_enc;
-defm V6_pred_or_n : T_HVX_predAlu <"$dst = or($src1,!$src2)">, V6_pred_or_n_enc;
-defm V6_pred_and_n :
- T_HVX_predAlu <"$dst = and($src1,!$src2)">, V6_pred_and_n_enc;
-
-let Itinerary = CVI_VA, Type = TypeCVI_VA in
-class T_HVX_prednot <RegisterClass RC>
- : CVI_VA_Resource1<(outs RC:$dst), (ins RC:$src1),
- "$dst = not($src1)">, V6_pred_not_enc;
-
-def V6_pred_not : T_HVX_prednot <VecPredRegs>;
-let isCodeGenOnly = 1 in
-def V6_pred_not_128B : T_HVX_prednot <VecPredRegs128B>;
-
-let Itinerary = CVI_VA, Type = TypeCVI_VA in
-class T_HVX_vcmp2 <string asmString, RegisterClass RCout, RegisterClass RCin>
- : CVI_VA_Resource1 <(outs RCout:$dst), (ins RCin:$src1, RCin:$src2),
- asmString >;
-
-multiclass T_HVX_vcmp2 <string asmString> {
- def NAME : T_HVX_vcmp2 <asmString, VecPredRegs, VectorRegs>;
- let isCodeGenOnly = 1 in
- def NAME#_128B : T_HVX_vcmp2 <asmString, VecPredRegs128B, VectorRegs128B>;
-}
-
-defm V6_veqb : T_HVX_vcmp2 <"$dst = vcmp.eq($src1.b,$src2.b)">, V6_veqb_enc;
-defm V6_veqh : T_HVX_vcmp2 <"$dst = vcmp.eq($src1.h,$src2.h)">, V6_veqh_enc;
-defm V6_veqw : T_HVX_vcmp2 <"$dst = vcmp.eq($src1.w,$src2.w)">, V6_veqw_enc;
-defm V6_vgtb : T_HVX_vcmp2 <"$dst = vcmp.gt($src1.b,$src2.b)">, V6_vgtb_enc;
-defm V6_vgth : T_HVX_vcmp2 <"$dst = vcmp.gt($src1.h,$src2.h)">, V6_vgth_enc;
-defm V6_vgtw : T_HVX_vcmp2 <"$dst = vcmp.gt($src1.w,$src2.w)">, V6_vgtw_enc;
-defm V6_vgtub : T_HVX_vcmp2 <"$dst = vcmp.gt($src1.ub,$src2.ub)">, V6_vgtub_enc;
-defm V6_vgtuh : T_HVX_vcmp2 <"$dst = vcmp.gt($src1.uh,$src2.uh)">, V6_vgtuh_enc;
-defm V6_vgtuw : T_HVX_vcmp2 <"$dst = vcmp.gt($src1.uw,$src2.uw)">, V6_vgtuw_enc;
-
-let isAccumulator = 1, hasNewValue = 1, hasSideEffects = 0 in
-class T_V6_vandqrt_acc <RegisterClass RCout, RegisterClass RCin>
- : CVI_VX_Resource_late<(outs RCout:$dst),
- (ins RCout:$_src_, RCin:$src1, IntRegs:$src2),
- "$dst |= vand($src1,$src2)", [], "$dst = $_src_">, V6_vandqrt_acc_enc;
-
-def V6_vandqrt_acc : T_V6_vandqrt_acc <VectorRegs, VecPredRegs>;
-let isCodeGenOnly = 1 in
-def V6_vandqrt_acc_128B : T_V6_vandqrt_acc <VectorRegs128B, VecPredRegs128B>;
-
-let isAccumulator = 1 in
-class T_V6_vandvrt_acc <RegisterClass RCout, RegisterClass RCin>
- : CVI_VX_Resource_late<(outs RCout:$dst),
- (ins RCout:$_src_, RCin:$src1, IntRegs:$src2),
- "$dst |= vand($src1,$src2)", [], "$dst = $_src_">, V6_vandvrt_acc_enc;
-
-def V6_vandvrt_acc : T_V6_vandvrt_acc <VecPredRegs, VectorRegs>;
-let isCodeGenOnly = 1 in
-def V6_vandvrt_acc_128B : T_V6_vandvrt_acc <VecPredRegs128B, VectorRegs128B>;
-
-let hasNewValue = 1, hasSideEffects = 0 in
-class T_V6_vandqrt <RegisterClass RCout, RegisterClass RCin>
- : CVI_VX_Resource_late<(outs RCout:$dst),
- (ins RCin:$src1, IntRegs:$src2),
- "$dst = vand($src1,$src2)" >, V6_vandqrt_enc;
-
-def V6_vandqrt : T_V6_vandqrt <VectorRegs, VecPredRegs>;
-let isCodeGenOnly = 1 in
-def V6_vandqrt_128B : T_V6_vandqrt <VectorRegs128B, VecPredRegs128B>;
-
-let hasNewValue = 1, hasSideEffects = 0 in
-class T_V6_lvsplatw <RegisterClass RC>
- : CVI_VX_Resource_late<(outs RC:$dst), (ins IntRegs:$src1),
- "$dst = vsplat($src1)" >, V6_lvsplatw_enc;
-
-def V6_lvsplatw : T_V6_lvsplatw <VectorRegs>;
-let isCodeGenOnly = 1 in
-def V6_lvsplatw_128B : T_V6_lvsplatw <VectorRegs128B>;
-
-
-let hasNewValue = 1 in
-class T_V6_vinsertwr <RegisterClass RC>
- : CVI_VX_Resource_late<(outs RC:$dst), (ins RC:$_src_, IntRegs:$src1),
- "$dst.w = vinsert($src1)", [], "$dst = $_src_">,
- V6_vinsertwr_enc;
-
-def V6_vinsertwr : T_V6_vinsertwr <VectorRegs>;
-let isCodeGenOnly = 1 in
-def V6_vinsertwr_128B : T_V6_vinsertwr <VectorRegs128B>;
-
-
-let Itinerary = CVI_VP_LONG, Type = TypeCVI_VP in
-class T_V6_pred_scalar2 <RegisterClass RC>
- : CVI_VA_Resource1<(outs RC:$dst), (ins IntRegs:$src1),
- "$dst = vsetq($src1)">, V6_pred_scalar2_enc;
-
-def V6_pred_scalar2 : T_V6_pred_scalar2 <VecPredRegs>;
-let isCodeGenOnly = 1 in
-def V6_pred_scalar2_128B : T_V6_pred_scalar2 <VecPredRegs128B>;
-
-class T_V6_vandvrt <RegisterClass RCout, RegisterClass RCin>
- : CVI_VX_Resource_late<(outs RCout:$dst), (ins RCin:$src1, IntRegs:$src2),
- "$dst = vand($src1,$src2)">, V6_vandvrt_enc;
-
-def V6_vandvrt : T_V6_vandvrt <VecPredRegs, VectorRegs>;
-let isCodeGenOnly = 1 in
-def V6_vandvrt_128B : T_V6_vandvrt <VecPredRegs128B, VectorRegs128B>;
-
-let validSubTargets = HasV60SubT in
-class T_HVX_rol <string asmString, RegisterClass RC, Operand ImmOp >
- : SInst2 <(outs RC:$dst), (ins RC:$src1, ImmOp:$src2), asmString>;
-
-class T_HVX_rol_R <string asmString>
- : T_HVX_rol <asmString, IntRegs, u5_0Imm>;
-class T_HVX_rol_P <string asmString>
- : T_HVX_rol <asmString, DoubleRegs, u6_0Imm>;
-
-def S6_rol_i_p : T_HVX_rol_P <"$dst = rol($src1,#$src2)">, S6_rol_i_p_enc;
-let hasNewValue = 1, opNewValue = 0 in
-def S6_rol_i_r : T_HVX_rol_R <"$dst = rol($src1,#$src2)">, S6_rol_i_r_enc;
-
-let validSubTargets = HasV60SubT in
-class T_HVX_rol_acc <string asmString, RegisterClass RC, Operand ImmOp>
- : SInst2 <(outs RC:$dst), (ins RC:$_src_, RC:$src1, ImmOp:$src2),
- asmString, [], "$dst = $_src_" >;
-
-class T_HVX_rol_acc_P <string asmString>
- : T_HVX_rol_acc <asmString, DoubleRegs, u6_0Imm>;
-
-class T_HVX_rol_acc_R <string asmString>
- : T_HVX_rol_acc <asmString, IntRegs, u5_0Imm>;
-
-def S6_rol_i_p_nac :
- T_HVX_rol_acc_P <"$dst -= rol($src1,#$src2)">, S6_rol_i_p_nac_enc;
-def S6_rol_i_p_acc :
- T_HVX_rol_acc_P <"$dst += rol($src1,#$src2)">, S6_rol_i_p_acc_enc;
-def S6_rol_i_p_and :
- T_HVX_rol_acc_P <"$dst &= rol($src1,#$src2)">, S6_rol_i_p_and_enc;
-def S6_rol_i_p_or :
- T_HVX_rol_acc_P <"$dst |= rol($src1,#$src2)">, S6_rol_i_p_or_enc;
-def S6_rol_i_p_xacc :
- T_HVX_rol_acc_P<"$dst ^= rol($src1,#$src2)">, S6_rol_i_p_xacc_enc;
-
-let hasNewValue = 1, opNewValue = 0 in {
-def S6_rol_i_r_nac :
- T_HVX_rol_acc_R <"$dst -= rol($src1,#$src2)">, S6_rol_i_r_nac_enc;
-def S6_rol_i_r_acc :
- T_HVX_rol_acc_R <"$dst += rol($src1,#$src2)">, S6_rol_i_r_acc_enc;
-def S6_rol_i_r_and :
- T_HVX_rol_acc_R <"$dst &= rol($src1,#$src2)">, S6_rol_i_r_and_enc;
-def S6_rol_i_r_or :
- T_HVX_rol_acc_R <"$dst |= rol($src1,#$src2)">, S6_rol_i_r_or_enc;
-def S6_rol_i_r_xacc :
- T_HVX_rol_acc_R <"$dst ^= rol($src1,#$src2)">, S6_rol_i_r_xacc_enc;
-}
-
-let isSolo = 1, Itinerary = LD_tc_ld_SLOT0, Type = TypeLD in
-class T_V6_extractw <RegisterClass RC>
- : LD1Inst <(outs IntRegs:$dst), (ins RC:$src1, IntRegs:$src2),
- "$dst = vextract($src1,$src2)">, V6_extractw_enc;
-
-def V6_extractw : T_V6_extractw <VectorRegs>;
-let isCodeGenOnly = 1 in
-def V6_extractw_128B : T_V6_extractw <VectorRegs128B>;
-
-let Itinerary = ST_tc_st_SLOT0, validSubTargets = HasV55SubT in
-class T_sys0op <string asmString>
- : ST1Inst <(outs), (ins), asmString>;
-
-let isSolo = 1, validSubTargets = HasV55SubT in {
-def Y5_l2gunlock : T_sys0op <"l2gunlock">, Y5_l2gunlock_enc;
-def Y5_l2gclean : T_sys0op <"l2gclean">, Y5_l2gclean_enc;
-def Y5_l2gcleaninv : T_sys0op <"l2gcleaninv">, Y5_l2gcleaninv_enc;
-}
-
-class T_sys1op <string asmString, RegisterClass RC>
- : ST1Inst <(outs), (ins RC:$src1), asmString>;
-
-class T_sys1op_R <string asmString> : T_sys1op <asmString, IntRegs>;
-class T_sys1op_P <string asmString> : T_sys1op <asmString, DoubleRegs>;
-
-let isSoloAX = 1, validSubTargets = HasV55SubT in
-def Y5_l2unlocka : T_sys1op_R <"l2unlocka($src1)">, Y5_l2unlocka_enc;
-
-let isSolo = 1, validSubTargets = HasV60SubT in {
-def Y6_l2gcleanpa : T_sys1op_P <"l2gclean($src1)">, Y6_l2gcleanpa_enc;
-def Y6_l2gcleaninvpa : T_sys1op_P <"l2gcleaninv($src1)">, Y6_l2gcleaninvpa_enc;
-}
-
-let Itinerary = ST_tc_3stall_SLOT0, isPredicateLate = 1, isSoloAX = 1,
- validSubTargets = HasV55SubT in
-def Y5_l2locka : ST1Inst <(outs PredRegs:$dst), (ins IntRegs:$src1),
- "$dst = l2locka($src1)">, Y5_l2locka_enc;
-
-// not defined on etc side. why?
-// defm S2_cabacencbin : _VV <"Rdd=encbin(Rss,$src2,Pu)">, S2_cabacencbin_enc;
-
-let Defs = [USR_OVF], Itinerary = M_tc_3stall_SLOT23, isPredicateLate = 1,
- hasSideEffects = 0,
-validSubTargets = HasV55SubT in
-def A5_ACS : MInst2 <(outs DoubleRegs:$dst1, PredRegs:$dst2),
- (ins DoubleRegs:$_src_, DoubleRegs:$src1, DoubleRegs:$src2),
- "$dst1,$dst2 = vacsh($src1,$src2)", [],
- "$dst1 = $_src_" >, Requires<[HasV55T]>, A5_ACS_enc;
-
-let Itinerary = CVI_VA_DV, Type = TypeCVI_VA_DV, hasNewValue = 1,
- hasSideEffects = 0 in
-class T_HVX_alu2 <string asmString, RegisterClass RCout, RegisterClass RCin1,
- RegisterClass RCin2>
- : CVI_VA_Resource1<(outs RCout:$dst),
- (ins RCin1:$src1, RCin2:$src2, RCin2:$src3), asmString>;
-
-multiclass T_HVX_alu2 <string asmString, RegisterClass RC > {
- def NAME : T_HVX_alu2 <asmString, RC, VecPredRegs, VectorRegs>;
- let isCodeGenOnly = 1 in
- def NAME#_128B : T_HVX_alu2 <asmString, !cast<RegisterClass>(RC#"128B"),
- VecPredRegs128B, VectorRegs128B>;
-}
-
-multiclass T_HVX_alu2_V <string asmString> :
- T_HVX_alu2 <asmString, VectorRegs>;
-
-multiclass T_HVX_alu2_W <string asmString> :
- T_HVX_alu2 <asmString, VecDblRegs>;
-
-defm V6_vswap : T_HVX_alu2_W <"$dst = vswap($src1,$src2,$src3)">, V6_vswap_enc;
-
-let Itinerary = CVI_VA, Type = TypeCVI_VA, hasNewValue = 1,
- hasSideEffects = 0 in
-defm V6_vmux : T_HVX_alu2_V <"$dst = vmux($src1,$src2,$src3)">, V6_vmux_enc;
-
-class T_HVX_vlutb <string asmString, RegisterClass RCout, RegisterClass RCin>
- : CVI_VA_Resource1<(outs RCout:$dst),
- (ins RCin:$src1, RCin:$src2, IntRegsLow8:$src3), asmString>;
-
-multiclass T_HVX_vlutb <string asmString, RegisterClass RCout,
- RegisterClass RCin> {
- def NAME : T_HVX_vlutb <asmString, RCout, RCin>;
- let isCodeGenOnly = 1 in
- def NAME#_128B : T_HVX_vlutb <asmString, !cast<RegisterClass>(RCout#"128B"),
- !cast<RegisterClass>(RCin#"128B")>;
-}
-
-multiclass T_HVX_vlutb_V <string asmString> :
- T_HVX_vlutb <asmString, VectorRegs, VectorRegs>;
-
-multiclass T_HVX_vlutb_W <string asmString> :
- T_HVX_vlutb <asmString, VecDblRegs, VectorRegs>;
-
-let Itinerary = CVI_VP_VS_LONG, Type = TypeCVI_VP_VS, isAccumulator = 1 in
-class T_HVX_vlutb_acc <string asmString, RegisterClass RCout,
- RegisterClass RCin>
- : CVI_VA_Resource1<(outs RCout:$dst),
- (ins RCout:$_src_, RCin:$src1, RCin:$src2, IntRegsLow8:$src3),
- asmString, [], "$dst = $_src_">;
-
-multiclass T_HVX_vlutb_acc <string asmString, RegisterClass RCout,
- RegisterClass RCin> {
- def NAME : T_HVX_vlutb_acc <asmString, RCout, RCin>;
- let isCodeGenOnly = 1 in
- def NAME#_128B : T_HVX_vlutb_acc<asmString,
- !cast<RegisterClass>(RCout#"128B"),
- !cast<RegisterClass>(RCin#"128B")>;
-}
-
-multiclass T_HVX_vlutb_acc_V <string asmString> :
- T_HVX_vlutb_acc <asmString, VectorRegs, VectorRegs>;
-
-multiclass T_HVX_vlutb_acc_W <string asmString> :
- T_HVX_vlutb_acc <asmString, VecDblRegs, VectorRegs>;
-
-
-let Itinerary = CVI_VP_LONG, Type = TypeCVI_VP, hasNewValue = 1 in
-defm V6_vlutvvb:
- T_HVX_vlutb_V <"$dst.b = vlut32($src1.b,$src2.b,$src3)">, V6_vlutvvb_enc;
-
-let Itinerary = CVI_VP_VS_LONG, Type = TypeCVI_VP_VS, hasNewValue = 1 in
-defm V6_vlutvwh:
- T_HVX_vlutb_W <"$dst.h = vlut16($src1.b,$src2.h,$src3)">, V6_vlutvwh_enc;
-
-let hasNewValue = 1 in {
- defm V6_vlutvvb_oracc:
- T_HVX_vlutb_acc_V <"$dst.b |= vlut32($src1.b,$src2.b,$src3)">,
- V6_vlutvvb_oracc_enc;
- defm V6_vlutvwh_oracc:
- T_HVX_vlutb_acc_W <"$dst.h |= vlut16($src1.b,$src2.h,$src3)">,
- V6_vlutvwh_oracc_enc;
-}
-
-// It's a fake instruction and should not be defined?
-def S2_cabacencbin
- : SInst2<(outs DoubleRegs:$dst),
- (ins DoubleRegs:$src1, DoubleRegs:$src2, PredRegs:$src3),
- "$dst = encbin($src1,$src2,$src3)">, S2_cabacencbin_enc;
-
-// Vhist instructions
-def V6_vhistq
- : CVI_HIST_Resource1 <(outs), (ins VecPredRegs:$src1),
- "vhist($src1)">, V6_vhistq_enc;
-
-def V6_vhist
- : CVI_HIST_Resource1 <(outs), (ins),
- "vhist" >, V6_vhist_enc;
-
-
-let isPseudo = 1, isCodeGenOnly = 1, hasSideEffects = 0 in {
- def V6_vd0: CVI_VA_Resource<(outs VectorRegs:$dst), (ins), "$dst = #0", []>;
- def V6_vd0_128B: CVI_VA_Resource<(outs VectorRegs128B:$dst), (ins),
- "$dst = #0", []>;
-
- def V6_vassignp: CVI_VA_Resource<(outs VecDblRegs:$dst),
- (ins VecDblRegs:$src), "", []>;
- def V6_vassignp_128B : CVI_VA_Resource<(outs VecDblRegs128B:$dst),
- (ins VecDblRegs128B:$src), "", []>;
-
- def V6_lo: CVI_VA_Resource<(outs VectorRegs:$dst), (ins VecDblRegs:$src1),
- "", []>;
- def V6_lo_128B: CVI_VA_Resource<(outs VectorRegs128B:$dst),
- (ins VecDblRegs128B:$src1), "", []>;
-
- def V6_hi: CVI_VA_Resource<(outs VectorRegs:$dst), (ins VecDblRegs:$src1),
- "", []>;
- def V6_hi_128B: CVI_VA_Resource<(outs VectorRegs128B:$dst),
- (ins VecDblRegs128B:$src1), "", []>;
-}
Removed: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoVector.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoVector.td?rev=294752&view=auto
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoVector.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoVector.td (removed)
@@ -1,69 +0,0 @@
-//===- HexagonInstrInfoVector.td - Hexagon Vector Patterns -*- tablegen -*-===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file describes the Hexagon Vector instructions in TableGen format.
-//
-//===----------------------------------------------------------------------===//
-
-// Vector shift support. Vector shifting in Hexagon is rather different
-// from internal representation of LLVM.
-// LLVM assumes all shifts (in vector case) will have the form
-// <VT> = SHL/SRA/SRL <VT> by <VT>
-// while Hexagon has the following format:
-// <VT> = SHL/SRA/SRL <VT> by <IT/i32>
-// As a result, special care is needed to guarantee correctness and
-// performance.
-class vshift_v4i16<SDNode Op, string Str, bits<3>MajOp, bits<3>MinOp>
- : S_2OpInstImm<Str, MajOp, MinOp, u4_0Imm, []> {
- bits<4> src2;
- let Inst{11-8} = src2;
-}
-
-class vshift_v2i32<SDNode Op, string Str, bits<3>MajOp, bits<3>MinOp>
- : S_2OpInstImm<Str, MajOp, MinOp, u5_0Imm, []> {
- bits<5> src2;
- let Inst{12-8} = src2;
-}
-
-def S2_asr_i_vw : vshift_v2i32<sra, "vasrw", 0b010, 0b000>;
-def S2_lsr_i_vw : vshift_v2i32<srl, "vlsrw", 0b010, 0b001>;
-def S2_asl_i_vw : vshift_v2i32<shl, "vaslw", 0b010, 0b010>;
-
-def S2_asr_i_vh : vshift_v4i16<sra, "vasrh", 0b100, 0b000>;
-def S2_lsr_i_vh : vshift_v4i16<srl, "vlsrh", 0b100, 0b001>;
-def S2_asl_i_vh : vshift_v4i16<shl, "vaslh", 0b100, 0b010>;
-
-// Vector shift words by register
-def S2_asr_r_vw : T_S3op_shiftVect < "vasrw", 0b00, 0b00>;
-def S2_lsr_r_vw : T_S3op_shiftVect < "vlsrw", 0b00, 0b01>;
-def S2_asl_r_vw : T_S3op_shiftVect < "vaslw", 0b00, 0b10>;
-def S2_lsl_r_vw : T_S3op_shiftVect < "vlslw", 0b00, 0b11>;
-
-// Vector shift halfwords by register
-def S2_asr_r_vh : T_S3op_shiftVect < "vasrh", 0b01, 0b00>;
-def S2_lsr_r_vh : T_S3op_shiftVect < "vlsrh", 0b01, 0b01>;
-def S2_asl_r_vh : T_S3op_shiftVect < "vaslh", 0b01, 0b10>;
-def S2_lsl_r_vh : T_S3op_shiftVect < "vlslh", 0b01, 0b11>;
-
-
-// Hexagon doesn't have a vector multiply with C semantics.
-// Instead, generate a pseudo instruction that gets expaneded into two
-// scalar MPYI instructions.
-// This is expanded by ExpandPostRAPseudos.
-let isPseudo = 1 in
-def PS_vmulw : PseudoM<(outs DoubleRegs:$Rd),
- (ins DoubleRegs:$Rs, DoubleRegs:$Rt), "", []>;
-
-let isPseudo = 1 in
-def PS_vmulw_acc : PseudoM<(outs DoubleRegs:$Rd),
- (ins DoubleRegs:$Rx, DoubleRegs:$Rs, DoubleRegs:$Rt), "", [],
- "$Rd = $Rx">;
-
-
-
Modified: llvm/trunk/lib/Target/Hexagon/HexagonIntrinsicsV60.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonIntrinsicsV60.td?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonIntrinsicsV60.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonIntrinsicsV60.td Fri Feb 10 09:33:13 2017
@@ -790,7 +790,7 @@ def : T_RRI_pat <S6_rol_i_r_xacc, int_he
defm : T_VR_pat <V6_extractw, int_hexagon_V6_extractw>;
defm : T_VR_pat <V6_vinsertwr, int_hexagon_V6_vinsertwr>;
-def : T_PPQ_pat <S2_cabacencbin, int_hexagon_S2_cabacencbin>;
+//def : T_PPQ_pat <S2_cabacencbin, int_hexagon_S2_cabacencbin>;
def: Pat<(v64i16 (trunc v64i32:$Vdd)),
(v64i16 (V6_vpackwh_sat_128B
Modified: llvm/trunk/lib/Target/Hexagon/HexagonOperands.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonOperands.td?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonOperands.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonOperands.td Fri Feb 10 09:33:13 2017
@@ -1,298 +1,33 @@
-//===- HexagonImmediates.td - Hexagon immediate processing -*- tablegen -*-===//
+//===--- HexagonOperands.td -----------------------------------------------===//
//
// The LLVM Compiler Infrastructure
//
-// This file is distributed under the University of Illnois Open Source
+// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
-def s32_0ImmOperand : AsmOperandClass { let Name = "s32_0Imm"; }
-def s23_2ImmOperand : AsmOperandClass { let Name = "s23_2Imm"; }
-def s8_0ImmOperand : AsmOperandClass { let Name = "s8_0Imm"; }
-def s8_0Imm64Operand : AsmOperandClass { let Name = "s8_0Imm64"; }
-def s6_0ImmOperand : AsmOperandClass { let Name = "s6_0Imm"; }
-def s4_0ImmOperand : AsmOperandClass { let Name = "s4_0Imm"; }
-def s4_1ImmOperand : AsmOperandClass { let Name = "s4_1Imm"; }
-def s4_2ImmOperand : AsmOperandClass { let Name = "s4_2Imm"; }
-def s4_3ImmOperand : AsmOperandClass { let Name = "s4_3Imm"; }
-def s4_6ImmOperand : AsmOperandClass { let Name = "s4_6Imm"; }
-def s3_6ImmOperand : AsmOperandClass { let Name = "s3_6Imm"; }
-def u64_0ImmOperand : AsmOperandClass { let Name = "u64_0Imm"; }
-def u32_0ImmOperand : AsmOperandClass { let Name = "u32_0Imm"; }
-def u26_6ImmOperand : AsmOperandClass { let Name = "u26_6Imm"; }
-def u16_0ImmOperand : AsmOperandClass { let Name = "u16_0Imm"; }
-def u16_1ImmOperand : AsmOperandClass { let Name = "u16_1Imm"; }
-def u16_2ImmOperand : AsmOperandClass { let Name = "u16_2Imm"; }
-def u16_3ImmOperand : AsmOperandClass { let Name = "u16_3Imm"; }
-def u11_3ImmOperand : AsmOperandClass { let Name = "u11_3Imm"; }
-def u10_0ImmOperand : AsmOperandClass { let Name = "u10_0Imm"; }
-def u9_0ImmOperand : AsmOperandClass { let Name = "u9_0Imm"; }
-def u8_0ImmOperand : AsmOperandClass { let Name = "u8_0Imm"; }
-def u7_0ImmOperand : AsmOperandClass { let Name = "u7_0Imm"; }
-def u6_0ImmOperand : AsmOperandClass { let Name = "u6_0Imm"; }
-def u6_1ImmOperand : AsmOperandClass { let Name = "u6_1Imm"; }
-def u6_2ImmOperand : AsmOperandClass { let Name = "u6_2Imm"; }
-def u6_3ImmOperand : AsmOperandClass { let Name = "u6_3Imm"; }
-def u5_0ImmOperand : AsmOperandClass { let Name = "u5_0Imm"; }
-def u4_0ImmOperand : AsmOperandClass { let Name = "u4_0Imm"; }
-def u3_0ImmOperand : AsmOperandClass { let Name = "u3_0Imm"; }
-def u2_0ImmOperand : AsmOperandClass { let Name = "u2_0Imm"; }
-def u1_0ImmOperand : AsmOperandClass { let Name = "u1_0Imm"; }
-def n8_0ImmOperand : AsmOperandClass { let Name = "n8_0Imm"; }
-// Immediate operands.
-
-let OperandType = "OPERAND_IMMEDIATE",
- DecoderMethod = "unsignedImmDecoder" in {
- def s32_0Imm : Operand<i32> { let ParserMatchClass = s32_0ImmOperand;
- let DecoderMethod = "s32_0ImmDecoder"; }
- def s23_2Imm : Operand<i32> { let ParserMatchClass = s23_2ImmOperand; }
- def s8_0Imm : Operand<i32> { let ParserMatchClass = s8_0ImmOperand;
- let DecoderMethod = "s8_0ImmDecoder"; }
- def s8_0Imm64 : Operand<i64> { let ParserMatchClass = s8_0Imm64Operand;
- let DecoderMethod = "s8_0ImmDecoder"; }
- def s6_0Imm : Operand<i32> { let ParserMatchClass = s6_0ImmOperand;
- let DecoderMethod = "s6_0ImmDecoder"; }
- def s6_3Imm : Operand<i32>;
- def s4_0Imm : Operand<i32> { let ParserMatchClass = s4_0ImmOperand;
- let DecoderMethod = "s4_0ImmDecoder"; }
- def s4_1Imm : Operand<i32> { let ParserMatchClass = s4_1ImmOperand;
- let DecoderMethod = "s4_1ImmDecoder"; }
- def s4_2Imm : Operand<i32> { let ParserMatchClass = s4_2ImmOperand;
- let DecoderMethod = "s4_2ImmDecoder"; }
- def s4_3Imm : Operand<i32> { let ParserMatchClass = s4_3ImmOperand;
- let DecoderMethod = "s4_3ImmDecoder"; }
- def u64_0Imm : Operand<i64> { let ParserMatchClass = u64_0ImmOperand; }
- def u32_0Imm : Operand<i32> { let ParserMatchClass = u32_0ImmOperand; }
- def u26_6Imm : Operand<i32> { let ParserMatchClass = u26_6ImmOperand; }
- def u16_0Imm : Operand<i32> { let ParserMatchClass = u16_0ImmOperand; }
- def u16_1Imm : Operand<i32> { let ParserMatchClass = u16_1ImmOperand; }
- def u16_2Imm : Operand<i32> { let ParserMatchClass = u16_2ImmOperand; }
- def u16_3Imm : Operand<i32> { let ParserMatchClass = u16_3ImmOperand; }
- def u11_3Imm : Operand<i32> { let ParserMatchClass = u11_3ImmOperand; }
- def u10_0Imm : Operand<i32> { let ParserMatchClass = u10_0ImmOperand; }
- def u9_0Imm : Operand<i32> { let ParserMatchClass = u9_0ImmOperand; }
- def u8_0Imm : Operand<i32> { let ParserMatchClass = u8_0ImmOperand; }
- def u7_0Imm : Operand<i32> { let ParserMatchClass = u7_0ImmOperand; }
- def u6_0Imm : Operand<i32> { let ParserMatchClass = u6_0ImmOperand; }
- def u6_1Imm : Operand<i32> { let ParserMatchClass = u6_1ImmOperand; }
- def u6_2Imm : Operand<i32> { let ParserMatchClass = u6_2ImmOperand; }
- def u6_3Imm : Operand<i32> { let ParserMatchClass = u6_3ImmOperand; }
- def u5_0Imm : Operand<i32> { let ParserMatchClass = u5_0ImmOperand; }
- def u5_1Imm : Operand<i32>;
- def u5_2Imm : Operand<i32>;
- def u5_3Imm : Operand<i32>;
- def u4_0Imm : Operand<i32> { let ParserMatchClass = u4_0ImmOperand; }
- def u4_1Imm : Operand<i32>;
- def u4_2Imm : Operand<i32>;
- def u4_3Imm : Operand<i32>;
- def u3_0Imm : Operand<i32> { let ParserMatchClass = u3_0ImmOperand; }
- def u3_1Imm : Operand<i32>;
- def u3_2Imm : Operand<i32>;
- def u3_3Imm : Operand<i32>;
- def u2_0Imm : Operand<i32> { let ParserMatchClass = u2_0ImmOperand; }
- def u1_0Imm : Operand<i32> { let ParserMatchClass = u1_0ImmOperand; }
- def n8_0Imm : Operand<i32> { let ParserMatchClass = n8_0ImmOperand; }
-}
-
-let OperandType = "OPERAND_IMMEDIATE" in {
- def s4_6Imm : Operand<i32> { let ParserMatchClass = s4_6ImmOperand;
- let PrintMethod = "prints4_6ImmOperand";
- let DecoderMethod = "s4_6ImmDecoder";}
- def s4_7Imm : Operand<i32> { let PrintMethod = "prints4_7ImmOperand";
- let DecoderMethod = "s4_6ImmDecoder";}
- def s3_6Imm : Operand<i32> { let ParserMatchClass = s3_6ImmOperand;
- let PrintMethod = "prints3_6ImmOperand";
- let DecoderMethod = "s3_6ImmDecoder";}
- def s3_7Imm : Operand<i32> { let PrintMethod = "prints3_7ImmOperand";
- let DecoderMethod = "s3_6ImmDecoder";}
-}
-def n1ConstOperand : AsmOperandClass { let Name = "n1Const"; }
-def n1Const : Operand<i32> { let ParserMatchClass = n1ConstOperand; }
-
-//
-// Immediate predicates
-//
-def s32_0ImmPred : PatLeaf<(i32 imm), [{
+def f32ImmOperand : AsmOperandClass { let Name = "f32Imm"; }
+def f32Imm : Operand<f32> { let ParserMatchClass = f32ImmOperand; }
+def f64ImmOperand : AsmOperandClass { let Name = "f64Imm"; }
+def f64Imm : Operand<f64> { let ParserMatchClass = f64ImmOperand; }
+def s8_0Imm64Pred : PatLeaf<(i64 imm), [{ return isInt<8>(N->getSExtValue()); }]>;
+def s9_0ImmOperand : AsmOperandClass { let Name = "s9_0Imm"; }
+def s9_0Imm : Operand<i32> { let ParserMatchClass = s9_0ImmOperand; }
+def s23_2ImmOperand : AsmOperandClass { let Name = "s23_2Imm"; let RenderMethod = "addSignedImmOperands"; }
+def s23_2Imm : Operand<i32> { let ParserMatchClass = s23_2ImmOperand; }
+def r32_0ImmPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
return isInt<32>(v);
}]>;
-
-def s31_1ImmPred : PatLeaf<(i32 imm), [{
- int64_t v = (int64_t)N->getSExtValue();
- return isShiftedInt<31,1>(v);
-}]>;
-
-def s30_2ImmPred : PatLeaf<(i32 imm), [{
- int64_t v = (int64_t)N->getSExtValue();
- return isShiftedInt<30,2>(v);
-}]>;
-
-def s29_3ImmPred : PatLeaf<(i32 imm), [{
- int64_t v = (int64_t)N->getSExtValue();
- return isShiftedInt<29,3>(v);
-}]>;
-
-def s10_0ImmPred : PatLeaf<(i32 imm), [{
- int64_t v = (int64_t)N->getSExtValue();
- return isInt<10>(v);
-}]>;
-
-def s8_0ImmPred : PatLeaf<(i32 imm), [{
- int64_t v = (int64_t)N->getSExtValue();
- return isInt<8>(v);
-}]>;
-
-def s8_0Imm64Pred : PatLeaf<(i64 imm), [{
- int64_t v = (int64_t)N->getSExtValue();
- return isInt<8>(v);
-}]>;
-
-def s6_0ImmPred : PatLeaf<(i32 imm), [{
- int64_t v = (int64_t)N->getSExtValue();
- return isInt<6>(v);
-}]>;
-
-def s4_0ImmPred : PatLeaf<(i32 imm), [{
- int64_t v = (int64_t)N->getSExtValue();
- return isInt<4>(v);
-}]>;
-
-def s4_1ImmPred : PatLeaf<(i32 imm), [{
- int64_t v = (int64_t)N->getSExtValue();
- return isShiftedInt<4,1>(v);
-}]>;
-
-def s4_2ImmPred : PatLeaf<(i32 imm), [{
- int64_t v = (int64_t)N->getSExtValue();
- return isShiftedInt<4,2>(v);
-}]>;
-
-def s4_3ImmPred : PatLeaf<(i32 imm), [{
- int64_t v = (int64_t)N->getSExtValue();
- return isShiftedInt<4,3>(v);
-}]>;
-
-def u32_0ImmPred : PatLeaf<(i32 imm), [{
- int64_t v = (int64_t)N->getSExtValue();
- return isUInt<32>(v);
-}]>;
-
-def u16_0ImmPred : PatLeaf<(i32 imm), [{
- int64_t v = (int64_t)N->getSExtValue();
- return isUInt<16>(v);
-}]>;
-
-def u11_3ImmPred : PatLeaf<(i32 imm), [{
- int64_t v = (int64_t)N->getSExtValue();
- return isShiftedUInt<11,3>(v);
-}]>;
-
def u9_0ImmPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
return isUInt<9>(v);
}]>;
-
-def u8_0ImmPred : PatLeaf<(i32 imm), [{
- int64_t v = (int64_t)N->getSExtValue();
- return isUInt<8>(v);
-}]>;
-
-def u6_0ImmPred : PatLeaf<(i32 imm), [{
- int64_t v = (int64_t)N->getSExtValue();
- return isUInt<6>(v);
-}]>;
-
-def u6_1ImmPred : PatLeaf<(i32 imm), [{
- int64_t v = (int64_t)N->getSExtValue();
- return isShiftedUInt<6,1>(v);
-}]>;
-
-def u6_2ImmPred : PatLeaf<(i32 imm), [{
- int64_t v = (int64_t)N->getSExtValue();
- return isShiftedUInt<6,2>(v);
-}]>;
-
-def u5_0ImmPred : PatLeaf<(i32 imm), [{
- int64_t v = (int64_t)N->getSExtValue();
- return isUInt<5>(v);
-}]>;
-
-def u4_0ImmPred : PatLeaf<(i32 imm), [{
- int64_t v = (int64_t)N->getSExtValue();
- return isUInt<4>(v);
-}]>;
-
-def u3_0ImmPred : PatLeaf<(i32 imm), [{
- int64_t v = (int64_t)N->getSExtValue();
- return isUInt<3>(v);
-}]>;
-
-def u2_0ImmPred : PatLeaf<(i32 imm), [{
- int64_t v = (int64_t)N->getSExtValue();
- return isUInt<2>(v);
-}]>;
-
-// Extendable immediate operands.
-def f32ExtOperand : AsmOperandClass { let Name = "f32Ext"; }
-def s16_0ExtOperand : AsmOperandClass { let Name = "s16_0Ext"; }
-def s12_0ExtOperand : AsmOperandClass { let Name = "s12_0Ext"; }
-def s10_0ExtOperand : AsmOperandClass { let Name = "s10_0Ext"; }
-def s9_0ExtOperand : AsmOperandClass { let Name = "s9_0Ext"; }
-def s8_0ExtOperand : AsmOperandClass { let Name = "s8_0Ext"; }
-def s7_0ExtOperand : AsmOperandClass { let Name = "s7_0Ext"; }
-def s6_0ExtOperand : AsmOperandClass { let Name = "s6_0Ext"; }
-def s11_0ExtOperand : AsmOperandClass { let Name = "s11_0Ext"; }
-def s11_1ExtOperand : AsmOperandClass { let Name = "s11_1Ext"; }
-def s11_2ExtOperand : AsmOperandClass { let Name = "s11_2Ext"; }
-def s11_3ExtOperand : AsmOperandClass { let Name = "s11_3Ext"; }
-def u6_0ExtOperand : AsmOperandClass { let Name = "u6_0Ext"; }
-def u7_0ExtOperand : AsmOperandClass { let Name = "u7_0Ext"; }
-def u8_0ExtOperand : AsmOperandClass { let Name = "u8_0Ext"; }
-def u9_0ExtOperand : AsmOperandClass { let Name = "u9_0Ext"; }
-def u10_0ExtOperand : AsmOperandClass { let Name = "u10_0Ext"; }
-def u6_1ExtOperand : AsmOperandClass { let Name = "u6_1Ext"; }
-def u6_2ExtOperand : AsmOperandClass { let Name = "u6_2Ext"; }
-def u6_3ExtOperand : AsmOperandClass { let Name = "u6_3Ext"; }
-def u32_0MustExtOperand : AsmOperandClass { let Name = "u32_0MustExt"; }
-
-
-
-let OperandType = "OPERAND_IMMEDIATE", PrintMethod = "printExtOperand",
- DecoderMethod = "unsignedImmDecoder" in {
- def f32Ext : Operand<f32> { let ParserMatchClass = f32ExtOperand; }
- def s16_0Ext : Operand<i32> { let ParserMatchClass = s16_0ExtOperand;
- let DecoderMethod = "s16_0ImmDecoder"; }
- def s12_0Ext : Operand<i32> { let ParserMatchClass = s12_0ExtOperand;
- let DecoderMethod = "s12_0ImmDecoder"; }
- def s11_0Ext : Operand<i32> { let ParserMatchClass = s11_0ExtOperand;
- let DecoderMethod = "s11_0ImmDecoder"; }
- def s11_1Ext : Operand<i32> { let ParserMatchClass = s11_1ExtOperand;
- let DecoderMethod = "s11_1ImmDecoder"; }
- def s11_2Ext : Operand<i32> { let ParserMatchClass = s11_2ExtOperand;
- let DecoderMethod = "s11_2ImmDecoder"; }
- def s11_3Ext : Operand<i32> { let ParserMatchClass = s11_3ExtOperand;
- let DecoderMethod = "s11_3ImmDecoder"; }
- def s10_0Ext : Operand<i32> { let ParserMatchClass = s10_0ExtOperand;
- let DecoderMethod = "s10_0ImmDecoder"; }
- def s9_0Ext : Operand<i32> { let ParserMatchClass = s9_0ExtOperand;
- let DecoderMethod = "s9_0ImmDecoder"; }
- def s8_0Ext : Operand<i32> { let ParserMatchClass = s8_0ExtOperand;
- let DecoderMethod = "s8_0ImmDecoder"; }
- def s7_0Ext : Operand<i32> { let ParserMatchClass = s7_0ExtOperand; }
- def s6_0Ext : Operand<i32> { let ParserMatchClass = s6_0ExtOperand;
- let DecoderMethod = "s6_0ImmDecoder"; }
- def u7_0Ext : Operand<i32> { let ParserMatchClass = u7_0ExtOperand; }
- def u8_0Ext : Operand<i32> { let ParserMatchClass = u8_0ExtOperand; }
- def u9_0Ext : Operand<i32> { let ParserMatchClass = u9_0ExtOperand; }
- def u10_0Ext : Operand<i32> { let ParserMatchClass = u10_0ExtOperand; }
- def u6_0Ext : Operand<i32> { let ParserMatchClass = u6_0ExtOperand; }
- def u6_1Ext : Operand<i32> { let ParserMatchClass = u6_1ExtOperand; }
- def u6_2Ext : Operand<i32> { let ParserMatchClass = u6_2ExtOperand; }
- def u6_3Ext : Operand<i32> { let ParserMatchClass = u6_3ExtOperand; }
- def u32_0MustExt : Operand<i32> { let ParserMatchClass = u32_0MustExtOperand; }
-}
-
+def u64_0ImmOperand : AsmOperandClass { let Name = "u64_0Imm"; let RenderMethod = "addImmOperands"; }
+def u64_0Imm : Operand<i64> { let ParserMatchClass = u64_0ImmOperand; }
+def n1ConstOperand : AsmOperandClass { let Name = "n1Const"; }
+def n1Const : Operand<i32> { let ParserMatchClass = n1ConstOperand; }
// This complex pattern exists only to create a machine instruction operand
// of type "frame index". There doesn't seem to be a way to do that directly
@@ -305,28 +40,6 @@ def AddrFI : ComplexPattern<i32, 1, "Sel
def AddrGA : ComplexPattern<i32, 1, "SelectAddrGA", [], []>;
def AddrGP : ComplexPattern<i32, 1, "SelectAddrGP", [], []>;
-// Address operands.
-
-let PrintMethod = "printGlobalOperand" in {
- def globaladdress : Operand<i32>;
- def globaladdressExt : Operand<i32>;
-}
-
-let PrintMethod = "printJumpTable" in
-def jumptablebase : Operand<i32>;
-
-def brtarget : Operand<OtherVT> {
- let DecoderMethod = "brtargetDecoder";
- let PrintMethod = "printBrtarget";
-}
-def brtargetExt : Operand<OtherVT> {
- let DecoderMethod = "brtargetDecoder";
- let PrintMethod = "printBrtarget";
-}
-def calltarget : Operand<i32> {
- let DecoderMethod = "brtargetDecoder";
- let PrintMethod = "printBrtarget";
-}
def bblabel : Operand<i32>;
def bbl : SDNode<"ISD::BasicBlock", SDTPtrLeaf, [], "BasicBlockSDNode">;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td Fri Feb 10 09:33:13 2017
@@ -153,8 +153,12 @@ def: Pat<(sub s32_0ImmPred:$s10, IntRegs
def: Pat<(not I32:$src1),
(A2_subri -1, IntRegs:$src1)>;
+def TruncI64ToI32: SDNodeXForm<imm, [{
+ return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32);
+}]>;
+
def: Pat<(s32_0ImmPred:$s16), (A2_tfrsi imm:$s16)>;
-def: Pat<(s8_0Imm64Pred:$s8), (A2_tfrpi imm:$s8)>;
+def: Pat<(s8_0Imm64Pred:$s8), (A2_tfrpi (TruncI64ToI32 $s8))>;
def : Pat<(select I1:$Pu, s32_0ImmPred:$s8, I32:$Rs),
(C2_muxri I1:$Pu, imm:$s8, I32:$Rs)>;
@@ -274,7 +278,7 @@ def retflag : SDNode<"HexagonISD::RET_FL
[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
def eh_return: SDNode<"HexagonISD::EH_RETURN", SDTNone, [SDNPHasChain]>;
-def: Pat<(br bb:$dst), (J2_jump brtarget:$dst)>;
+def: Pat<(br bb:$dst), (J2_jump b30_2Imm:$dst)>;
def: Pat<(brcond I1:$src1, bb:$block), (J2_jumpt PredRegs:$src1, bb:$block)>;
def: Pat<(brind I32:$dst), (J2_jumpr IntRegs:$dst)>;
@@ -695,8 +699,8 @@ def HexagonCONST32 : SDNode<"HexagonI
def HexagonCONST32_GP : SDNode<"HexagonISD::CONST32_GP", SDTHexagonCONST32>;
// Map TLS addressses to A2_tfrsi.
-def: Pat<(HexagonCONST32 tglobaltlsaddr:$addr), (A2_tfrsi s16_0Ext:$addr)>;
-def: Pat<(HexagonCONST32 bbl:$label), (A2_tfrsi s16_0Ext:$label)>;
+def: Pat<(HexagonCONST32 tglobaltlsaddr:$addr), (A2_tfrsi s32_0Imm:$addr)>;
+def: Pat<(HexagonCONST32 bbl:$label), (A2_tfrsi s32_0Imm:$label)>;
def: Pat<(i64 imm:$v), (CONST64 imm:$v)>;
def: Pat<(i1 0), (PS_false)>;
@@ -2718,17 +2722,6 @@ def unalignedstore : PatFrag<(ops node:$
}]>;
-def s4_6ImmPred: PatLeaf<(i32 imm), [{
- int64_t V = N->getSExtValue();
- return isShiftedInt<4,6>(V);
-}]>;
-
-def s4_7ImmPred: PatLeaf<(i32 imm), [{
- int64_t V = N->getSExtValue();
- return isShiftedInt<4,7>(V);
-}]>;
-
-
multiclass vS32b_ai_pats <ValueType VTSgl, ValueType VTDbl> {
// Aligned stores
def : Pat<(alignedstore (VTSgl VectorRegs:$src1), IntRegs:$addr),
@@ -3253,8 +3246,8 @@ def vmpyh: OutPatFrag<(ops node:$Rs, nod
(M2_vmpy2s_s0 (i32 $Rs), (i32 $Rt))>;
def: Pat<(v2i16 (mul V2I16:$Rs, V2I16:$Rt)),
- (LoReg (S2_vtrunewh (v2i32 (A2_combineii 0, 0)),
- (v2i32 (vmpyh V2I16:$Rs, V2I16:$Rt))))>;
+ (LoReg (S2_vtrunewh (A2_combineii 0, 0),
+ (vmpyh V2I16:$Rs, V2I16:$Rt)))>;
// Multiplies two v4i16 vectors.
def: Pat<(v4i16 (mul V4I16:$Rs, V4I16:$Rt)),
Added: llvm/trunk/lib/Target/Hexagon/HexagonPseudo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonPseudo.td?rev=294753&view=auto
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonPseudo.td (added)
+++ llvm/trunk/lib/Target/Hexagon/HexagonPseudo.td Fri Feb 10 09:33:13 2017
@@ -0,0 +1,538 @@
+//===--- HexagonPseudo.td -------------------------------------------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+let PrintMethod = "printGlobalOperand" in {
+ def globaladdress : Operand<i32>;
+ def globaladdressExt : Operand<i32>;
+}
+
+let isPseudo = 1 in {
+let isCodeGenOnly = 0 in
+def A2_iconst : Pseudo<(outs IntRegs:$Rd32), (ins s23_2Imm:$Ii), "${Rd32}=iconst(#${Ii})">;
+def DUPLEX_Pseudo : InstHexagon<(outs), (ins s32_0Imm:$offset), "DUPLEX", [], "", DUPLEX, TypePSEUDO>;
+}
+
+let isExtendable = 1, opExtendable = 1, opExtentBits = 6,
+ isAsmParserOnly = 1 in
+def TFRI64_V2_ext : ALU64_rr<(outs DoubleRegs:$dst),
+ (ins s32_0Imm:$src1, s8_0Imm:$src2),
+ "$dst=combine(#$src1,#$src2)">;
+
+// HI/LO Instructions
+let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0,
+ hasNewValue = 1, opNewValue = 0 in
+class REG_IMMED<string RegHalf, bit Rs, bits<3> MajOp, bit MinOp>
+ : InstHexagon<(outs IntRegs:$dst),
+ (ins u16_0Imm:$imm_value),
+ "$dst"#RegHalf#"=#$imm_value", [], "", ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, OpcodeHexagon {
+ bits<5> dst;
+ bits<32> imm_value;
+
+ let Inst{27} = Rs;
+ let Inst{26-24} = MajOp;
+ let Inst{21} = MinOp;
+ let Inst{20-16} = dst;
+ let Inst{23-22} = imm_value{15-14};
+ let Inst{13-0} = imm_value{13-0};
+}
+
+let isAsmParserOnly = 1 in {
+ def LO : REG_IMMED<".l", 0b0, 0b001, 0b1>;
+ def HI : REG_IMMED<".h", 0b0, 0b010, 0b1>;
+}
+
+let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in {
+ def CONST32 : CONSTLDInst<(outs IntRegs:$Rd), (ins i32imm:$v),
+ "$Rd = CONST32(#$v)", []>;
+ def CONST64 : CONSTLDInst<(outs DoubleRegs:$Rd), (ins i64imm:$v),
+ "$Rd = CONST64(#$v)", []>;
+}
+
+let hasSideEffects = 0, isReMaterializable = 1, isPseudo = 1,
+ isCodeGenOnly = 1 in
+def PS_true : SInst<(outs PredRegs:$dst), (ins), "", []>;
+
+let hasSideEffects = 0, isReMaterializable = 1, isPseudo = 1,
+ isCodeGenOnly = 1 in
+def PS_false : SInst<(outs PredRegs:$dst), (ins), "", []>;
+
+let Defs = [R29, R30], Uses = [R31, R30, R29], isPseudo = 1 in
+def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
+ ".error \"should not emit\" ", []>;
+
+let Defs = [R29, R30, R31], Uses = [R29], isPseudo = 1 in
+def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
+ ".error \"should not emit\" ", []>;
+
+
+let isBranch = 1, isTerminator = 1, hasSideEffects = 0,
+ Defs = [PC, LC0], Uses = [SA0, LC0] in {
+def ENDLOOP0 : Endloop<(outs), (ins b30_2Imm:$offset),
+ ":endloop0",
+ []>;
+}
+
+let isBranch = 1, isTerminator = 1, hasSideEffects = 0,
+ Defs = [PC, LC1], Uses = [SA1, LC1] in {
+def ENDLOOP1 : Endloop<(outs), (ins b30_2Imm:$offset),
+ ":endloop1",
+ []>;
+}
+
+let isExtendable = 1, isExtentSigned = 1, opExtentBits = 9, opExtentAlign = 2,
+ opExtendable = 0, hasSideEffects = 0 in
+class LOOP_iBase<string mnemonic, Operand brOp, bit mustExtend = 0>
+ : CRInst<(outs), (ins brOp:$offset, u10_0Imm:$src2),
+ #mnemonic#"($offset,#$src2)",
+ [], "" , CR_tc_3x_SLOT3> {
+ bits<9> offset;
+ bits<10> src2;
+
+ let IClass = 0b0110;
+
+ let Inst{27-22} = 0b100100;
+ let Inst{21} = !if (!eq(mnemonic, "loop0"), 0b0, 0b1);
+ let Inst{20-16} = src2{9-5};
+ let Inst{12-8} = offset{8-4};
+ let Inst{7-5} = src2{4-2};
+ let Inst{4-3} = offset{3-2};
+ let Inst{1-0} = src2{1-0};
+}
+
+let isExtendable = 1, isExtentSigned = 1, opExtentBits = 9, opExtentAlign = 2,
+ opExtendable = 0, hasSideEffects = 0 in
+class LOOP_rBase<string mnemonic, Operand brOp, bit mustExtend = 0>
+ : CRInst<(outs), (ins brOp:$offset, IntRegs:$src2),
+ #mnemonic#"($offset,$src2)",
+ [], "" ,CR_tc_3x_SLOT3> {
+ bits<9> offset;
+ bits<5> src2;
+
+ let IClass = 0b0110;
+
+ let Inst{27-22} = 0b000000;
+ let Inst{21} = !if (!eq(mnemonic, "loop0"), 0b0, 0b1);
+ let Inst{20-16} = src2;
+ let Inst{12-8} = offset{8-4};
+ let Inst{4-3} = offset{3-2};
+ }
+
+multiclass LOOP_ri<string mnemonic> {
+ let isCodeGenOnly = 1, isExtended = 1, opExtendable = 0 in {
+ def iext: LOOP_iBase<mnemonic, b30_2Imm, 1>;
+ def rext: LOOP_rBase<mnemonic, b30_2Imm, 1>;
+ }
+}
+
+
+let Defs = [SA0, LC0, USR] in
+defm J2_loop0 : LOOP_ri<"loop0">;
+
+// Interestingly only loop0's appear to set usr.lpcfg
+let Defs = [SA1, LC1] in
+defm J2_loop1 : LOOP_ri<"loop1">;
+
+let isCall = 1, hasSideEffects = 1, isPredicable = 0,
+ isExtended = 0, isExtendable = 1, opExtendable = 0,
+ isExtentSigned = 1, opExtentBits = 24, opExtentAlign = 2 in
+class T_Call<bit CSR, string ExtStr>
+ : JInst<(outs), (ins a30_2Imm:$dst),
+ "call " # ExtStr # "$dst", [], "", J_tc_2early_SLOT23> {
+ let BaseOpcode = "call";
+ bits<24> dst;
+
+ let Defs = !if (CSR, VolatileV3.Regs, []);
+ let IClass = 0b0101;
+ let Inst{27-25} = 0b101;
+ let Inst{24-16,13-1} = dst{23-2};
+ let Inst{0} = 0b0;
+}
+
+let isCodeGenOnly = 1, isCall = 1, hasSideEffects = 1, Defs = [R16],
+ isPredicable = 0 in
+def CALLProfile : T_Call<1, "">;
+
+let isCodeGenOnly = 1, isCall = 1, hasSideEffects = 1,
+ Defs = [PC, R31, R6, R7, P0] in
+def PS_call_stk : T_Call<0, "">;
+
+let isCall = 1, hasSideEffects = 1, cofMax1 = 1 in
+class JUMPR_MISC_CALLR<bit isPred, bit isPredNot,
+ dag InputDag = (ins IntRegs:$Rs)>
+ : JInst<(outs), InputDag,
+ !if(isPred, !if(isPredNot, "if (!$Pu) callr $Rs",
+ "if ($Pu) callr $Rs"),
+ "callr $Rs"),
+ [], "", J_tc_2early_SLOT2> {
+ bits<5> Rs;
+ bits<2> Pu;
+ let isPredicated = isPred;
+ let isPredicatedFalse = isPredNot;
+
+ let IClass = 0b0101;
+ let Inst{27-25} = 0b000;
+ let Inst{24-23} = !if (isPred, 0b10, 0b01);
+ let Inst{22} = 0;
+ let Inst{21} = isPredNot;
+ let Inst{9-8} = !if (isPred, Pu, 0b00);
+ let Inst{20-16} = Rs;
+
+ }
+
+let isCodeGenOnly = 1, Defs = VolatileV3.Regs in {
+ def PS_callr_nr : JUMPR_MISC_CALLR<0, 1>; // Call, no return.
+}
+
+let isCall = 1, hasSideEffects = 1, Defs = VolatileV3.Regs,
+ isExtended = 0, isExtendable = 1, opExtendable = 0, isCodeGenOnly = 1,
+ BaseOpcode = "PS_call_nr", isExtentSigned = 1, opExtentAlign = 2,
+ Itinerary = J_tc_2early_SLOT23 in
+class Call_nr<bits<5> nbits, bit isPred, bit isFalse, dag iops>
+ : Pseudo<(outs), iops, "">, PredRel {
+ bits<2> Pu;
+ bits<17> dst;
+ let opExtentBits = nbits;
+ let isPredicable = 0; // !if(isPred, 0, 1);
+ let isPredicated = 0; // isPred;
+ let isPredicatedFalse = isFalse;
+}
+
+def PS_call_nr : Call_nr<24, 0, 0, (ins s32_0Imm:$Ii)>;
+//def PS_call_nrt: Call_nr<17, 1, 0, (ins PredRegs:$Pu, s32_0Imm:$dst)>;
+//def PS_call_nrf: Call_nr<17, 1, 1, (ins PredRegs:$Pu, s32_0Imm:$dst)>;
+
+let isBranch = 1, isIndirectBranch = 1, isBarrier = 1, Defs = [PC],
+ isPredicable = 1, hasSideEffects = 0, InputType = "reg",
+ cofMax1 = 1 in
+class T_JMPr
+ : InstHexagon<(outs), (ins IntRegs:$dst), "jumpr $dst", [],
+ "", J_tc_2early_SLOT2, TypeJ>, OpcodeHexagon {
+ bits<5> dst;
+
+ let IClass = 0b0101;
+ let Inst{27-21} = 0b0010100;
+ let Inst{20-16} = dst;
+}
+
+// A return through builtin_eh_return.
+let isReturn = 1, isTerminator = 1, isBarrier = 1, hasSideEffects = 0,
+ isCodeGenOnly = 1, Defs = [PC], Uses = [R28], isPredicable = 0 in
+def EH_RETURN_JMPR : T_JMPr;
+
+// Indirect tail-call.
+let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0,
+ isTerminator = 1, isCodeGenOnly = 1 in
+def PS_tailcall_r : T_JMPr;
+
+//
+// Direct tail-calls.
+let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0,
+ isTerminator = 1, isCodeGenOnly = 1 in
+def PS_tailcall_i : Pseudo<(outs), (ins a30_2Imm:$dst), "", []>;
+
+let isCodeGenOnly = 1, isPseudo = 1, Uses = [R30], hasSideEffects = 0 in
+def PS_aligna : Pseudo<(outs IntRegs:$Rd), (ins u32_0Imm:$A), "", []>;
+
+// Generate frameindex addresses. The main reason for the offset operand is
+// that every instruction that is allowed to have frame index as an operand
+// will then have that operand followed by an immediate operand (the offset).
+// This simplifies the frame-index elimination code.
+//
+let isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1,
+ isPseudo = 1, isCodeGenOnly = 1, hasSideEffects = 0 in {
+ def PS_fi : Pseudo<(outs IntRegs:$Rd),
+ (ins IntRegs:$fi, s32_0Imm:$off), "">;
+ def PS_fia : Pseudo<(outs IntRegs:$Rd),
+ (ins IntRegs:$Rs, IntRegs:$fi, s32_0Imm:$off), "">;
+}
+
+class CondStr<string CReg, bit True, bit New> {
+ string S = "if (" # !if(True,"","!") # CReg # !if(New,".new","") # ") ";
+}
+class JumpOpcStr<string Mnemonic, bit New, bit Taken> {
+ string S = Mnemonic # !if(Taken, ":t", ":nt");
+}
+let isBranch = 1, isIndirectBranch = 1, Defs = [PC], isPredicated = 1,
+ hasSideEffects = 0, InputType = "reg", cofMax1 = 1 in
+class T_JMPr_c <bit PredNot, bit isPredNew, bit isTak>
+ : InstHexagon<(outs), (ins PredRegs:$src, IntRegs:$dst),
+ CondStr<"$src", !if(PredNot,0,1), isPredNew>.S #
+ JumpOpcStr<"jumpr", isPredNew, isTak>.S # " $dst",
+ [], "", J_tc_2early_SLOT2, TypeJ>, OpcodeHexagon {
+
+ let isTaken = isTak;
+ let isPredicatedFalse = PredNot;
+ let isPredicatedNew = isPredNew;
+ bits<2> src;
+ bits<5> dst;
+
+ let IClass = 0b0101;
+
+ let Inst{27-22} = 0b001101;
+ let Inst{21} = PredNot;
+ let Inst{20-16} = dst;
+ let Inst{12} = isTak;
+ let Inst{11} = isPredNew;
+ let Inst{9-8} = src;
+}
+multiclass JMPR_Pred<bit PredNot> {
+ def NAME : T_JMPr_c<PredNot, 0, 0>; // not taken
+ // Predicate new
+ def NAME#newpt : T_JMPr_c<PredNot, 1, 1>; // taken
+ def NAME#new : T_JMPr_c<PredNot, 1, 0>; // not taken
+}
+multiclass JMPR_base<string BaseOp> {
+ let BaseOpcode = BaseOp in {
+ def NAME : T_JMPr;
+ defm t : JMPR_Pred<0>;
+ defm f : JMPR_Pred<1>;
+ }
+}
+let isTerminator = 1, hasSideEffects = 0, isReturn = 1, isCodeGenOnly = 1, isBarrier = 1 in
+defm PS_jmpret : JMPR_base<"JMPret">, PredNewRel;
+
+//defm V6_vtran2x2_map : HexagonMapping<(outs VectorRegs:$Vy32, VectorRegs:$Vx32), (ins VectorRegs:$Vx32in, IntRegs:$Rt32), "vtrans2x2(${Vy32},${Vx32},${Rt32})", (V6_vshuff VectorRegs:$Vy32, VectorRegs:$Vx32, VectorRegs:$Vx32in, IntRegs:$Rt32)>;
+
+// The reason for the custom inserter is to record all ALLOCA instructions
+// in MachineFunctionInfo.
+let Defs = [R29], isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 1 in
+def PS_alloca: InstHexagon<(outs IntRegs:$Rd),
+ (ins IntRegs:$Rs, u32_0Imm:$A), "",
+ [], "", ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>;
+
+// Load predicate.
+let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 13,
+ isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in
+def LDriw_pred : LDInst<(outs PredRegs:$dst),
+ (ins IntRegs:$addr, s32_0Imm:$off),
+ ".error \"should not emit\"", []>;
+
+// Load modifier.
+let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 13,
+ isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in
+def LDriw_mod : LDInst<(outs ModRegs:$dst),
+ (ins IntRegs:$addr, s32_0Imm:$off),
+ ".error \"should not emit\"", []>;
+
+// Vector load
+let Predicates = [HasV60T, UseHVX] in
+let mayLoad = 1, validSubTargets = HasV60SubT, hasSideEffects = 0 in
+ class V6_LDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
+ string cstr = "", InstrItinClass itin = CVI_VM_LD,
+ IType type = TypeCVI_VM_LD>
+ : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, type>;
+
+// Vector store
+let Predicates = [HasV60T, UseHVX] in
+let mayStore = 1, validSubTargets = HasV60SubT, hasSideEffects = 0 in
+class V6_STInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
+ string cstr = "", InstrItinClass itin = CVI_VM_ST,
+ IType type = TypeCVI_VM_ST>
+: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, type>;
+
+let isCodeGenOnly = 1, isPseudo = 1 in
+def PS_pselect : ALU64_rr<(outs DoubleRegs:$Rd),
+ (ins PredRegs:$Pu, DoubleRegs:$Rs, DoubleRegs:$Rt),
+ ".error \"should not emit\" ", []>;
+
+let isBranch = 1, isBarrier = 1, Defs = [PC], hasSideEffects = 0,
+ isPredicable = 1,
+ isExtendable = 1, opExtendable = 0, isExtentSigned = 1,
+ opExtentBits = 24, opExtentAlign = 2, InputType = "imm" in
+class T_JMP<string ExtStr>
+ : JInst_CJUMP_UCJUMP<(outs), (ins b30_2Imm:$dst),
+ "jump " # ExtStr # "$dst",
+ [], "", J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT> {
+ bits<24> dst;
+ let IClass = 0b0101;
+
+ let Inst{27-25} = 0b100;
+ let Inst{24-16} = dst{23-15};
+ let Inst{13-1} = dst{14-2};
+}
+
+// Restore registers and dealloc return function call.
+let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,
+ Defs = [R29, R30, R31, PC], isPredicable = 0, isAsmParserOnly = 1 in {
+ def RESTORE_DEALLOC_RET_JMP_V4 : T_JMP<"">;
+
+ let isExtended = 1, opExtendable = 0 in
+ def RESTORE_DEALLOC_RET_JMP_V4_EXT : T_JMP<"">;
+
+ let Defs = [R14, R15, R28, R29, R30, R31, PC] in {
+ def RESTORE_DEALLOC_RET_JMP_V4_PIC : T_JMP<"">;
+
+ let isExtended = 1, opExtendable = 0 in
+ def RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC : T_JMP<"">;
+ }
+}
+
+// Restore registers and dealloc frame before a tail call.
+let isCall = 1, Defs = [R29, R30, R31, PC], isAsmParserOnly = 1 in {
+ def RESTORE_DEALLOC_BEFORE_TAILCALL_V4 : T_Call<0, "">, PredRel;
+
+ let isExtended = 1, opExtendable = 0 in
+ def RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT : T_Call<0, "">, PredRel;
+
+ let Defs = [R14, R15, R28, R29, R30, R31, PC] in {
+ def RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC : T_Call<0, "">, PredRel;
+
+ let isExtended = 1, opExtendable = 0 in
+ def RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC : T_Call<0, "">, PredRel;
+ }
+}
+
+// Save registers function call.
+let isCall = 1, Uses = [R29, R31], isAsmParserOnly = 1 in {
+ def SAVE_REGISTERS_CALL_V4 : T_Call<0, "">, PredRel;
+
+ let isExtended = 1, opExtendable = 0 in
+ def SAVE_REGISTERS_CALL_V4_EXT : T_Call<0, "">, PredRel;
+
+ let Defs = [P0] in
+ def SAVE_REGISTERS_CALL_V4STK : T_Call<0, "">, PredRel;
+
+ let Defs = [P0], isExtended = 1, opExtendable = 0 in
+ def SAVE_REGISTERS_CALL_V4STK_EXT : T_Call<0, "">, PredRel;
+
+ let Defs = [R14, R15, R28] in
+ def SAVE_REGISTERS_CALL_V4_PIC : T_Call<0, "">, PredRel;
+
+ let Defs = [R14, R15, R28], isExtended = 1, opExtendable = 0 in
+ def SAVE_REGISTERS_CALL_V4_EXT_PIC : T_Call<0, "">, PredRel;
+
+ let Defs = [R14, R15, R28, P0] in
+ def SAVE_REGISTERS_CALL_V4STK_PIC : T_Call<0, "">, PredRel;
+
+ let Defs = [R14, R15, R28, P0], isExtended = 1, opExtendable = 0 in
+ def SAVE_REGISTERS_CALL_V4STK_EXT_PIC : T_Call<0, "">, PredRel;
+}
+
+// Vector load/store pseudos
+
+let isPseudo = 1, isCodeGenOnly = 1, validSubTargets = HasV60SubT in
+class STrivv_template<RegisterClass RC>
+ : V6_STInst<(outs), (ins IntRegs:$addr, s32_0Imm:$off, RC:$src), "", []>;
+
+def PS_vstorerw_ai: STrivv_template<VecDblRegs>,
+ Requires<[HasV60T,UseHVXSgl]>;
+def PS_vstorerwu_ai: STrivv_template<VecDblRegs>,
+ Requires<[HasV60T,UseHVXSgl]>;
+def PS_vstorerw_ai_128B: STrivv_template<VecDblRegs128B>,
+ Requires<[HasV60T,UseHVXDbl]>;
+def PS_vstorerwu_ai_128B: STrivv_template<VecDblRegs128B>,
+ Requires<[HasV60T,UseHVXDbl]>;
+
+
+let isPseudo = 1, isCodeGenOnly = 1, validSubTargets = HasV60SubT in
+class LDrivv_template<RegisterClass RC>
+ : V6_LDInst<(outs RC:$dst), (ins IntRegs:$addr, s32_0Imm:$off), "", []>;
+
+def PS_vloadrw_ai: LDrivv_template<VecDblRegs>,
+ Requires<[HasV60T,UseHVXSgl]>;
+def PS_vloadrwu_ai: LDrivv_template<VecDblRegs>,
+ Requires<[HasV60T,UseHVXSgl]>;
+def PS_vloadrw_ai_128B: LDrivv_template<VecDblRegs128B>,
+ Requires<[HasV60T,UseHVXDbl]>;
+def PS_vloadrwu_ai_128B: LDrivv_template<VecDblRegs128B>,
+ Requires<[HasV60T,UseHVXDbl]>;
+
+// Store vector predicate pseudo.
+let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 13,
+ isCodeGenOnly = 1, isPseudo = 1, mayStore = 1, hasSideEffects = 0 in {
+ def PS_vstorerq_ai : STInst<(outs),
+ (ins IntRegs:$base, s32_0Imm:$offset, VecPredRegs:$src1),
+ ".error \"should not emit\" ", []>,
+ Requires<[HasV60T,UseHVXSgl]>;
+
+ def PS_vstorerq_ai_128B : STInst<(outs),
+ (ins IntRegs:$base, s32_0Imm:$offset, VectorRegs:$src1),
+ ".error \"should not emit\" ", []>,
+ Requires<[HasV60T,UseHVXSgl]>;
+
+ def PS_vloadrq_ai : STInst<(outs),
+ (ins IntRegs:$base, s32_0Imm:$offset, VecPredRegs128B:$src1),
+ ".error \"should not emit\" ", []>,
+ Requires<[HasV60T,UseHVXDbl]>;
+
+ def PS_vloadrq_ai_128B : STInst<(outs),
+ (ins IntRegs:$base, s32_0Imm:$offset, VecPredRegs128B:$src1),
+ ".error \"should not emit\" ", []>,
+ Requires<[HasV60T,UseHVXDbl]>;
+}
+
+class VSELInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
+ string cstr = "", InstrItinClass itin = CVI_VA_DV,
+ IType type = TypeCVI_VA_DV>
+ : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, type>;
+
+let isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in {
+ def PS_vselect: VSELInst<(outs VectorRegs:$dst),
+ (ins PredRegs:$src1, VectorRegs:$src2, VectorRegs:$src3), "", []>,
+ Requires<[HasV60T,UseHVXSgl]>;
+ def PS_vselect_128B: VSELInst<(outs VectorRegs128B:$dst),
+ (ins PredRegs:$src1, VectorRegs128B:$src2, VectorRegs128B:$src3),
+ "", []>, Requires<[HasV60T,UseHVXDbl]>;
+ def PS_wselect: VSELInst<(outs VecDblRegs:$dst),
+ (ins PredRegs:$src1, VecDblRegs:$src2, VecDblRegs:$src3), "", []>,
+ Requires<[HasV60T,UseHVXSgl]>;
+ def PS_wselect_128B: VSELInst<(outs VecDblRegs128B:$dst),
+ (ins PredRegs:$src1, VecDblRegs128B:$src2, VecDblRegs128B:$src3),
+ "", []>, Requires<[HasV60T,UseHVXDbl]>;
+}
+
+// Store predicate.
+let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 13,
+ isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in
+def STriw_pred : STInst<(outs),
+ (ins IntRegs:$addr, s32_0Imm:$off, PredRegs:$src1),
+ ".error \"should not emit\"", []>;
+// Store modifier.
+let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 13,
+ isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in
+def STriw_mod : STInst<(outs),
+ (ins IntRegs:$addr, s32_0Imm:$off, ModRegs:$src1),
+ ".error \"should not emit\"", []>;
+
+let isExtendable = 1, opExtendable = 1, opExtentBits = 6,
+ isAsmParserOnly = 1 in
+def TFRI64_V4 : ALU64_rr<(outs DoubleRegs:$dst), (ins u64_0Imm:$src1),
+ "$dst = #$src1">;
+
+// Hexagon doesn't have a vector multiply with C semantics.
+// Instead, generate a pseudo instruction that gets expaneded into two
+// scalar MPYI instructions.
+// This is expanded by ExpandPostRAPseudos.
+let isPseudo = 1 in
+def PS_vmulw : PseudoM<(outs DoubleRegs:$Rd),
+ (ins DoubleRegs:$Rs, DoubleRegs:$Rt), "", []>;
+
+let isPseudo = 1 in
+def PS_vmulw_acc : PseudoM<(outs DoubleRegs:$Rd),
+ (ins DoubleRegs:$Rx, DoubleRegs:$Rs, DoubleRegs:$Rt), "", [],
+ "$Rd = $Rx">;
+
+def DuplexIClass0: InstDuplex < 0 >;
+def DuplexIClass1: InstDuplex < 1 >;
+def DuplexIClass2: InstDuplex < 2 >;
+let isExtendable = 1 in {
+ def DuplexIClass3: InstDuplex < 3 >;
+ def DuplexIClass4: InstDuplex < 4 >;
+ def DuplexIClass5: InstDuplex < 5 >;
+ def DuplexIClass6: InstDuplex < 6 >;
+ def DuplexIClass7: InstDuplex < 7 >;
+}
+def DuplexIClass8: InstDuplex < 8 >;
+def DuplexIClass9: InstDuplex < 9 >;
+def DuplexIClassA: InstDuplex < 0xA >;
+def DuplexIClassB: InstDuplex < 0xB >;
+def DuplexIClassC: InstDuplex < 0xC >;
+def DuplexIClassD: InstDuplex < 0xD >;
+def DuplexIClassE: InstDuplex < 0xE >;
+def DuplexIClassF: InstDuplex < 0xF >;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.td?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.td Fri Feb 10 09:33:13 2017
@@ -221,6 +221,10 @@ def IntRegs : RegisterClass<"Hexagon", [
}
// Registers are listed in reverse order for allocation preference reasons.
+def GeneralSubRegs : RegisterClass<"Hexagon", [i32], 32,
+ (add R23, R22, R21, R20, R19, R18, R17,
+ R16, R7, R6, R5, R4, R3, R2, R1, R0)>;
+
def IntRegsLow8 : RegisterClass<"Hexagon", [i32], 32,
(add R7, R6, R5, R4, R3, R2, R1, R0)> ;
@@ -228,6 +232,10 @@ def DoubleRegs : RegisterClass<"Hexagon"
(add (sequence "D%u", 0, 4),
(sequence "D%u", 6, 13), D5, D14, D15)>;
+def GeneralDoubleLow8Regs : RegisterClass<"Hexagon", [i64], 64,
+ (add D11, D10, D9, D8, D3, D2, D1,
+ D0)>;
+
def VectorRegs : RegisterClass<"Hexagon", [v64i8, v32i16, v16i32, v8i64], 512,
(add (sequence "V%u", 0, 31))>;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonSchedule.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonSchedule.td?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonSchedule.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonSchedule.td Fri Feb 10 09:33:13 2017
@@ -21,4 +21,3 @@ include "HexagonScheduleV55.td"
//===----------------------------------------------------------------------===//
include "HexagonScheduleV60.td"
-
Modified: llvm/trunk/lib/Target/Hexagon/HexagonScheduleV4.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonScheduleV4.td?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonScheduleV4.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonScheduleV4.td Fri Feb 10 09:33:13 2017
@@ -61,15 +61,21 @@ def J_tc_2early_SLOT23 : InstrItin
def J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT : InstrItinClass;
def J_tc_2early_SLOT2 : InstrItinClass;
def LD_tc_ld_SLOT01 : InstrItinClass;
+def LD_tc_ld_pi_SLOT01 : InstrItinClass;
def LD_tc_ld_SLOT0 : InstrItinClass;
def LD_tc_3or4stall_SLOT0 : InstrItinClass;
def M_tc_2_SLOT23 : InstrItinClass;
+def M_tc_2_acc_SLOT23 : InstrItinClass;
def M_tc_3_SLOT23 : InstrItinClass;
def M_tc_1_SLOT23 : InstrItinClass;
def M_tc_3x_SLOT23 : InstrItinClass;
+def M_tc_3x_acc_SLOT23 : InstrItinClass;
def M_tc_3or4x_SLOT23 : InstrItinClass;
+def M_tc_3or4x_acc_SLOT23 : InstrItinClass;
def ST_tc_st_SLOT01 : InstrItinClass;
+def ST_tc_st_pi_SLOT01 : InstrItinClass;
def ST_tc_st_SLOT0 : InstrItinClass;
+def ST_tc_st_pi_SLOT0 : InstrItinClass;
def ST_tc_ld_SLOT0 : InstrItinClass;
def ST_tc_3stall_SLOT0 : InstrItinClass;
def S_2op_tc_1_SLOT23 : InstrItinClass;
@@ -131,21 +137,27 @@ def HexagonItinerariesV4 :
//Load
InstrItinData<LD_tc_ld_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData<LD_tc_ld_pi_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
InstrItinData<LD_tc_ld_SLOT0 , [InstrStage<1, [SLOT0]>]>,
InstrItinData<LD_tc_3or4stall_SLOT0 , [InstrStage<1, [SLOT0]>]>,
// M
InstrItinData<M_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
InstrItinData<M_tc_2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData<M_tc_2_acc_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
InstrItinData<M_tc_3_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
InstrItinData<M_tc_3x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData<M_tc_3x_acc_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
InstrItinData<M_tc_3or4x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData<M_tc_3or4x_acc_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
// Store
// ST
InstrItinData<ST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData<ST_tc_st_pi_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
// ST0
InstrItinData<ST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>]>,
+ InstrItinData<ST_tc_st_pi_SLOT0 , [InstrStage<1, [SLOT0]>]>,
InstrItinData<ST_tc_ld_SLOT0 , [InstrStage<1, [SLOT0]>]>,
// S
Modified: llvm/trunk/lib/Target/Hexagon/HexagonScheduleV55.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonScheduleV55.td?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonScheduleV55.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonScheduleV55.td Fri Feb 10 09:33:13 2017
@@ -88,6 +88,8 @@ def HexagonItinerariesV55 :
// Load
InstrItinData<LD_tc_ld_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>],
[2, 1]>,
+ InstrItinData<LD_tc_ld_pi_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>],
+ [2, 1]>,
InstrItinData<LD_tc_3or4stall_SLOT0, [InstrStage<1, [SLOT0]>], [2, 1]>,
InstrItinData<LD_tc_ld_SLOT0 , [InstrStage<1, [SLOT0]>], [2, 1]>,
@@ -96,21 +98,30 @@ def HexagonItinerariesV55 :
[1, 1, 1]>,
InstrItinData<M_tc_2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
[2, 1, 1]>,
+ InstrItinData<M_tc_2_acc_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
+ [2, 1, 1]>,
InstrItinData<M_tc_3_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
[1, 1, 1]>,
InstrItinData<M_tc_3x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
[3, 1, 1]>,
+ InstrItinData<M_tc_3x_acc_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>],
+ [3, 1, 1, 1]>,
InstrItinData<M_tc_3or4x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
[3, 1, 1]>,
+ InstrItinData<M_tc_3or4x_acc_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
+ [3, 1, 1]>,
InstrItinData<M_tc_3stall_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>],
[3, 1, 1]>,
// Store
InstrItinData<ST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>],
[1, 1, 1]>,
+ InstrItinData<ST_tc_st_pi_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>],
+ [1, 1, 1]>,
InstrItinData<ST_tc_3stall_SLOT0, [InstrStage<1, [SLOT0]>], [2, 1, 1]>,
InstrItinData<ST_tc_ld_SLOT0 , [InstrStage<1, [SLOT0]>], [2, 1, 1]>,
InstrItinData<ST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>], [1, 1, 1]>,
+ InstrItinData<ST_tc_st_pi_SLOT0 , [InstrStage<1, [SLOT0]>], [1, 1, 1]>,
// S
InstrItinData<S_2op_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
Modified: llvm/trunk/lib/Target/Hexagon/HexagonScheduleV60.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonScheduleV60.td?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonScheduleV60.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonScheduleV60.td Fri Feb 10 09:33:13 2017
@@ -19,6 +19,8 @@ def CVI_LD : FuncUnit;
def CVI_XLSHF : FuncUnit;
def CVI_MPY01 : FuncUnit;
def CVI_ALL : FuncUnit;
+def CVI_XLMPY0 : FuncUnit;
+def CVI_SHFMPY1: FuncUnit;
// Combined functional unit data.
def HexagonComboFuncsV60 :
@@ -26,7 +28,9 @@ def HexagonComboFuncsV60 :
ComboFuncData<CVI_XLSHF , [CVI_XLANE, CVI_SHIFT]>,
ComboFuncData<CVI_MPY01 , [CVI_MPY0, CVI_MPY1]>,
ComboFuncData<CVI_ALL , [CVI_ST, CVI_XLANE, CVI_SHIFT,
- CVI_MPY0, CVI_MPY1, CVI_LD]>
+ CVI_MPY0, CVI_MPY1, CVI_LD]>,
+ ComboFuncData<CVI_XLMPY0 , [CVI_XLANE, CVI_MPY0]>,
+ ComboFuncData<CVI_SHFMPY1 , [CVI_SHIFT, CVI_MPY1]>
]>;
// Note: When adding additional vector scheduling classes, add the
@@ -39,6 +43,7 @@ def CVI_VX : InstrItinClass;
def CVI_VX_DV_LONG : InstrItinClass;
def CVI_VX_DV : InstrItinClass;
def CVI_VX_DV_SLOT2 : InstrItinClass;
+def CVI_VX_DV_SLOT2_LONG_EARLY : InstrItinClass;
def CVI_VP : InstrItinClass;
def CVI_VP_LONG : InstrItinClass;
def CVI_VP_VS_EARLY : InstrItinClass;
@@ -150,22 +155,28 @@ def HexagonItinerariesV60 :
// Load
InstrItinData<LD_tc_ld_SLOT01 , [InstrStage<3, [SLOT0, SLOT1]>]>,
+ InstrItinData<LD_tc_ld_pi_SLOT01 , [InstrStage<3, [SLOT0, SLOT1]>]>,
InstrItinData<LD_tc_3or4stall_SLOT0, [InstrStage<4, [SLOT0]>]>,
InstrItinData<LD_tc_ld_SLOT0 , [InstrStage<3, [SLOT0]>]>,
// M
InstrItinData<M_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
InstrItinData<M_tc_2_SLOT23 , [InstrStage<2, [SLOT2, SLOT3]>]>,
+ InstrItinData<M_tc_2_acc_SLOT23 , [InstrStage<2, [SLOT2, SLOT3]>]>,
InstrItinData<M_tc_3_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>,
InstrItinData<M_tc_3x_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>,
+ InstrItinData<M_tc_3x_acc_SLOT23, [InstrStage<3, [SLOT2, SLOT3]>]>,
InstrItinData<M_tc_3or4x_SLOT23 , [InstrStage<4, [SLOT2, SLOT3]>]>,
+ InstrItinData<M_tc_3or4x_acc_SLOT23 , [InstrStage<4, [SLOT2, SLOT3]>]>,
InstrItinData<M_tc_3stall_SLOT23, [InstrStage<3, [SLOT2, SLOT3]>]>,
// Store
InstrItinData<ST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData<ST_tc_st_pi_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>]>,
InstrItinData<ST_tc_3stall_SLOT0, [InstrStage<3, [SLOT0]>]>,
InstrItinData<ST_tc_ld_SLOT0 , [InstrStage<3, [SLOT0]>]>,
InstrItinData<ST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>]>,
+ InstrItinData<ST_tc_st_pi_SLOT0 , [InstrStage<1, [SLOT0]>]>,
// S
InstrItinData<S_2op_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
Modified: llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.h?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.h (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.h Fri Feb 10 09:33:13 2017
@@ -38,9 +38,7 @@ class HexagonSubtarget : public HexagonG
bool ModeIEEERndNear;
public:
- enum HexagonArchEnum {
- V4, V5, V55, V60
- };
+#include "HexagonDepArch.h"
HexagonArchEnum HexagonArchVersion;
/// True if the target should use Back-Skip-Back scheduling. This is the
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h (original)
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h Fri Feb 10 09:33:13 2017
@@ -17,6 +17,7 @@
#ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONBASEINFO_H
#define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONBASEINFO_H
+#include "HexagonDepITypes.h"
#include "HexagonMCTargetDesc.h"
#include "llvm/Support/ErrorHandling.h"
#include <stdint.h>
@@ -27,48 +28,8 @@ namespace llvm {
/// instruction info tracks.
///
namespace HexagonII {
- // *** The code below must match HexagonInstrFormat*.td *** //
-
- // Insn types.
- // *** Must match HexagonInstrFormat*.td ***
- enum Type {
- TypePSEUDO = 0,
- TypeCR = 2,
- TypeJ = 4,
- TypeLD = 5,
- TypeST = 6,
- TypeV4LDST = 9,
- TypeNCJ = 10,
- TypeDUPLEX = 11,
- TypeCJ = 12,
- TypeCVI_FIRST = 13,
- TypeCVI_VA = TypeCVI_FIRST,
- TypeCVI_VA_DV = 14,
- TypeCVI_VX = 15,
- TypeCVI_VX_DV = 16,
- TypeCVI_VP = 17,
- TypeCVI_VP_VS = 18,
- TypeCVI_VS = 19,
- TypeCVI_VINLANESAT= 20,
- TypeCVI_VM_LD = 21,
- TypeCVI_VM_TMP_LD = 22,
- TypeCVI_VM_CUR_LD = 23,
- TypeCVI_VM_VP_LDU = 24,
- TypeCVI_VM_ST = 25,
- TypeCVI_VM_NEW_ST = 26,
- TypeCVI_VM_STU = 27,
- TypeCVI_HIST = 28,
- TypeCVI_LAST = TypeCVI_HIST,
- TypeEXTENDER = 39,
- TypeENDLOOP = 40,
- TypeS_2op = 41,
- TypeS_3op = 42,
- TypeALU64 = 43,
- TypeM = 44,
- TypeALU32_2op = 45,
- TypeALU32_3op = 46,
- TypeALU32_ADDI = 47
- };
+ unsigned const TypeCVI_FIRST = TypeCVI_HIST;
+ unsigned const TypeCVI_LAST = TypeCVI_VX_DV;
enum SubTarget {
HasV4SubT = 0x3f,
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp Fri Feb 10 09:33:13 2017
@@ -362,7 +362,6 @@ int HexagonMCInstrInfo::getSubTarget(MCI
unsigned HexagonMCInstrInfo::getUnits(MCInstrInfo const &MCII,
MCSubtargetInfo const &STI,
MCInst const &MCI) {
-
const InstrItinerary *II = STI.getSchedModel().InstrItineraries;
int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass();
return ((II[SchedClass].FirstStage + HexagonStages)->getUnits());
@@ -758,22 +757,8 @@ void HexagonMCInstrInfo::padEndloop(MCIn
bool HexagonMCInstrInfo::prefersSlot3(MCInstrInfo const &MCII,
MCInst const &MCI) {
- if (HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCR)
- return false;
-
- unsigned SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass();
- switch (SchedClass) {
- case Hexagon::Sched::ALU32_3op_tc_2_SLOT0123:
- case Hexagon::Sched::ALU64_tc_2_SLOT23:
- case Hexagon::Sched::ALU64_tc_3x_SLOT23:
- case Hexagon::Sched::M_tc_2_SLOT23:
- case Hexagon::Sched::M_tc_3x_SLOT23:
- case Hexagon::Sched::S_2op_tc_2_SLOT23:
- case Hexagon::Sched::S_3op_tc_2_SLOT23:
- case Hexagon::Sched::S_3op_tc_3x_SLOT23:
- return true;
- }
- return false;
+ const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
+ return (F >> HexagonII::PrefersSlot3Pos) & HexagonII::PrefersSlot3Mask;
}
void HexagonMCInstrInfo::replaceDuplex(MCContext &Context, MCInst &MCB,
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.cpp?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.cpp Fri Feb 10 09:33:13 2017
@@ -34,7 +34,7 @@ void HexagonMCShuffler::init(MCInst &MCB
// Copy the bundle for the shuffling.
for (const auto &I : HexagonMCInstrInfo::bundleInstructions(MCB)) {
MCInst &MI = *const_cast<MCInst *>(I.getInst());
- DEBUG(dbgs() << "Shuffling: " << MCII.getName(MI.getOpcode()));
+ DEBUG(dbgs() << "Shuffling: " << MCII.getName(MI.getOpcode()) << '\n');
assert(!HexagonMCInstrInfo::getDesc(MCII, MI).isPseudo());
if (!HexagonMCInstrInfo::isImmext(MI)) {
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp Fri Feb 10 09:33:13 2017
@@ -22,6 +22,7 @@
#include "MCTargetDesc/HexagonMCInstrInfo.h"
#include "HexagonShuffler.h"
#include "llvm/Support/Debug.h"
+#include "llvm/Support/Format.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
@@ -363,6 +364,21 @@ bool HexagonShuffler::check() {
foundBranches.push_back(ISJ);
}
break;
+ case HexagonII::TypeV2LDST:
+ if(HexagonMCInstrInfo::getDesc(MCII, ID).mayLoad()) {
+ ++loads;
+ ++memory;
+ if (ISJ->Core.getUnits() == slotSingleLoad ||
+ HexagonMCInstrInfo::getType(MCII,ID) ==
+ HexagonII::TypeCVI_VM_VP_LDU)
+ ++load0;
+ }
+ else {
+ assert(HexagonMCInstrInfo::getDesc(MCII, ID).mayStore());
+ ++memory;
+ ++stores;
+ }
+ break;
case HexagonII::TypeCR:
// Legacy conditional branch predicated on a register.
case HexagonII::TypeCJ:
Modified: llvm/trunk/test/CodeGen/Hexagon/BranchPredict.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/BranchPredict.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/BranchPredict.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/BranchPredict.ll Fri Feb 10 09:33:13 2017
@@ -9,7 +9,7 @@
@j = external global i32
define i32 @foo(i32 %a) nounwind {
-; CHECK: if{{ *}}(!p{{[0-3]}}.new) jump:nt
+; CHECK: if (!p{{[0-3]}}.new) jump:nt
entry:
%tobool = icmp eq i32 %a, 0
br i1 %tobool, label %if.else, label %if.then, !prof !0
@@ -31,7 +31,7 @@ return:
declare i32 @foobar(...)
define i32 @bar(i32 %a) nounwind {
-; CHECK: if{{ *}}(p{{[0-3]}}.new) jump:nt
+; CHECK: if (p{{[0-3]}}.new) jump:nt
entry:
%tobool = icmp eq i32 %a, 0
br i1 %tobool, label %if.else, label %if.then, !prof !1
@@ -51,7 +51,7 @@ return:
}
define i32 @foo_bar(i32 %a, i16 signext %b) nounwind {
-; CHECK: if{{ *}}(!cmp.eq(r{{[0-9]*}}.new, #0)) jump:nt
+; CHECK: if (!cmp.eq(r{{[0-9]*}}.new,#0)) jump:nt
entry:
%0 = load i32, i32* @j, align 4
%tobool = icmp eq i32 %0, 0
Modified: llvm/trunk/test/CodeGen/Hexagon/adde.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/adde.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/adde.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/adde.ll Fri Feb 10 09:33:13 2017
@@ -1,17 +1,17 @@
; RUN: llc -march=hexagon -disable-hsdr -hexagon-expand-condsets=0 -hexagon-bit=0 -disable-post-ra < %s | FileCheck %s
-; CHECK: r{{[0-9]+:[0-9]+}} = combine(#0, #1)
-; CHECK: r{{[0-9]+:[0-9]+}} = combine(#0, #0)
-; CHECK: r{{[0-9]+:[0-9]+}} = add(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}})
-; CHECK: p{{[0-9]+}} = cmp.gtu(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}})
-; CHECK: p{{[0-9]+}} = cmp.gtu(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}})
-; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}})
-; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}})
-; CHECK: r{{[0-9]+:[0-9]+}} = combine(r{{[0-9]+}}, r{{[0-9]+}})
-; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}})
-; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}})
-; CHECK: r{{[0-9]+:[0-9]+}} = combine(r{{[0-9]+}}, r{{[0-9]+}})
-; CHECK: r{{[0-9]+:[0-9]+}} = add(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}})
+; CHECK: r{{[0-9]+:[0-9]+}} = combine(#0,#1)
+; CHECK: r{{[0-9]+:[0-9]+}} = combine(#0,#0)
+; CHECK: r{{[0-9]+:[0-9]+}} = add(r{{[0-9]+:[0-9]+}},r{{[0-9]+:[0-9]+}})
+; CHECK: p{{[0-9]+}} = cmp.gtu(r{{[0-9]+:[0-9]+}},r{{[0-9]+:[0-9]+}})
+; CHECK: p{{[0-9]+}} = cmp.gtu(r{{[0-9]+:[0-9]+}},r{{[0-9]+:[0-9]+}})
+; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}},r{{[0-9]+}},r{{[0-9]+}})
+; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}},r{{[0-9]+}},r{{[0-9]+}})
+; CHECK: r{{[0-9]+:[0-9]+}} = combine(r{{[0-9]+}},r{{[0-9]+}})
+; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}},r{{[0-9]+}},r{{[0-9]+}})
+; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}},r{{[0-9]+}},r{{[0-9]+}})
+; CHECK: r{{[0-9]+:[0-9]+}} = combine(r{{[0-9]+}},r{{[0-9]+}})
+; CHECK: r{{[0-9]+:[0-9]+}} = add(r{{[0-9]+:[0-9]+}},r{{[0-9]+:[0-9]+}})
define void @check_adde_addc (i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
Modified: llvm/trunk/test/CodeGen/Hexagon/addh-sext-trunc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/addh-sext-trunc.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/addh-sext-trunc.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/addh-sext-trunc.ll Fri Feb 10 09:33:13 2017
@@ -1,5 +1,5 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
-; CHECK: r{{[0-9]+}} = add(r{{[0-9]+}}.{{L|l}}, r{{[0-9]+}}.{{H|h}})
+; CHECK: r{{[0-9]+}} = add(r{{[0-9]+}}.{{L|l}},r{{[0-9]+}}.{{H|h}})
target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32"
target triple = "hexagon-unknown-none"
Modified: llvm/trunk/test/CodeGen/Hexagon/addh-shifted.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/addh-shifted.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/addh-shifted.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/addh-shifted.ll Fri Feb 10 09:33:13 2017
@@ -1,5 +1,5 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
-; CHECK: r{{[0-9]+}} = add(r{{[0-9]+}}.{{L|l}}, r{{[0-9]+}}.{{L|l}}):<<16
+; CHECK: r{{[0-9]+}} = add(r{{[0-9]+}}.{{L|l}},r{{[0-9]+}}.{{L|l}}):<<16
define i64 @test_cast(i64 %arg0, i16 zeroext %arg1, i16 zeroext %arg2) nounwind readnone {
entry:
Modified: llvm/trunk/test/CodeGen/Hexagon/addh.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/addh.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/addh.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/addh.ll Fri Feb 10 09:33:13 2017
@@ -1,5 +1,5 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
-; CHECK: r{{[0-9]+}} = add(r{{[0-9]+}}.{{L|l}}, r{{[0-9]+}}.{{L|l}})
+; CHECK: r{{[0-9]+}} = add(r{{[0-9]+}}.{{L|l}},r{{[0-9]+}}.{{L|l}})
define i64 @test_cast(i64 %arg0, i16 zeroext %arg1, i16 zeroext %arg2) nounwind readnone {
entry:
Modified: llvm/trunk/test/CodeGen/Hexagon/alu64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/alu64.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/alu64.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/alu64.ll Fri Feb 10 09:33:13 2017
@@ -1,7 +1,7 @@
; RUN: llc -march=hexagon -O0 < %s | FileCheck %s
; CHECK-LABEL: @test00
-; CHECK: = cmp.eq(r1:0, r3:2)
+; CHECK: = cmp.eq(r1:0,r3:2)
define i32 @test00(i64 %Rs, i64 %Rt) #0 {
entry:
%0 = tail call i32 @llvm.hexagon.C2.cmpeqp(i64 %Rs, i64 %Rt)
@@ -9,7 +9,7 @@ entry:
}
; CHECK-LABEL: @test01
-; CHECK: = cmp.gt(r1:0, r3:2)
+; CHECK: = cmp.gt(r1:0,r3:2)
define i32 @test01(i64 %Rs, i64 %Rt) #0 {
entry:
%0 = tail call i32 @llvm.hexagon.C2.cmpgtp(i64 %Rs, i64 %Rt)
@@ -17,7 +17,7 @@ entry:
}
; CHECK-LABEL: @test02
-; CHECK: = cmp.gtu(r1:0, r3:2)
+; CHECK: = cmp.gtu(r1:0,r3:2)
define i32 @test02(i64 %Rs, i64 %Rt) #0 {
entry:
%0 = tail call i32 @llvm.hexagon.C2.cmpgtup(i64 %Rs, i64 %Rt)
@@ -25,7 +25,7 @@ entry:
}
; CHECK-LABEL: @test10
-; CHECK: = cmp.eq(r0, r1)
+; CHECK: = cmp.eq(r0,r1)
define i32 @test10(i32 %Rs, i32 %Rt) #0 {
entry:
%0 = tail call i32 @llvm.hexagon.A4.rcmpeq(i32 %Rs, i32 %Rt)
@@ -33,7 +33,7 @@ entry:
}
; CHECK-LABEL: @test11
-; CHECK: = !cmp.eq(r0, r1)
+; CHECK: = !cmp.eq(r0,r1)
define i32 @test11(i32 %Rs, i32 %Rt) #0 {
entry:
%0 = tail call i32 @llvm.hexagon.A4.rcmpneq(i32 %Rs, i32 %Rt)
@@ -41,7 +41,7 @@ entry:
}
; CHECK-LABEL: @test12
-; CHECK: = cmp.eq(r0, #23)
+; CHECK: = cmp.eq(r0,#23)
define i32 @test12(i32 %Rs) #0 {
entry:
%0 = tail call i32 @llvm.hexagon.A4.rcmpeqi(i32 %Rs, i32 23)
@@ -49,7 +49,7 @@ entry:
}
; CHECK-LABEL: @test13
-; CHECK: = !cmp.eq(r0, #47)
+; CHECK: = !cmp.eq(r0,#47)
define i32 @test13(i32 %Rs) #0 {
entry:
%0 = tail call i32 @llvm.hexagon.A4.rcmpneqi(i32 %Rs, i32 47)
@@ -57,7 +57,7 @@ entry:
}
; CHECK-LABEL: @test20
-; CHECK: = cmpb.eq(r0, r1)
+; CHECK: = cmpb.eq(r0,r1)
define i32 @test20(i32 %Rs, i32 %Rt) #0 {
entry:
%0 = tail call i32 @llvm.hexagon.A4.cmpbeq(i32 %Rs, i32 %Rt)
@@ -65,7 +65,7 @@ entry:
}
; CHECK-LABEL: @test21
-; CHECK: = cmpb.gt(r0, r1)
+; CHECK: = cmpb.gt(r0,r1)
define i32 @test21(i32 %Rs, i32 %Rt) #0 {
entry:
%0 = tail call i32 @llvm.hexagon.A4.cmpbgt(i32 %Rs, i32 %Rt)
@@ -73,7 +73,7 @@ entry:
}
; CHECK-LABEL: @test22
-; CHECK: = cmpb.gtu(r0, r1)
+; CHECK: = cmpb.gtu(r0,r1)
define i32 @test22(i32 %Rs, i32 %Rt) #0 {
entry:
%0 = tail call i32 @llvm.hexagon.A4.cmpbgtu(i32 %Rs, i32 %Rt)
@@ -81,7 +81,7 @@ entry:
}
; CHECK-LABEL: @test23
-; CHECK: = cmpb.eq(r0, #56)
+; CHECK: = cmpb.eq(r0,#56)
define i32 @test23(i32 %Rs) #0 {
entry:
%0 = tail call i32 @llvm.hexagon.A4.cmpbeqi(i32 %Rs, i32 56)
@@ -89,7 +89,7 @@ entry:
}
; CHECK-LABEL: @test24
-; CHECK: = cmpb.gt(r0, #29)
+; CHECK: = cmpb.gt(r0,#29)
define i32 @test24(i32 %Rs) #0 {
entry:
%0 = tail call i32 @llvm.hexagon.A4.cmpbgti(i32 %Rs, i32 29)
@@ -97,7 +97,7 @@ entry:
}
; CHECK-LABEL: @test25
-; CHECK: = cmpb.gtu(r0, #111)
+; CHECK: = cmpb.gtu(r0,#111)
define i32 @test25(i32 %Rs) #0 {
entry:
%0 = tail call i32 @llvm.hexagon.A4.cmpbgtui(i32 %Rs, i32 111)
@@ -105,7 +105,7 @@ entry:
}
; CHECK-LABEL: @test30
-; CHECK: = cmph.eq(r0, r1)
+; CHECK: = cmph.eq(r0,r1)
define i32 @test30(i32 %Rs, i32 %Rt) #0 {
entry:
%0 = tail call i32 @llvm.hexagon.A4.cmpheq(i32 %Rs, i32 %Rt)
@@ -113,7 +113,7 @@ entry:
}
; CHECK-LABEL: @test31
-; CHECK: = cmph.gt(r0, r1)
+; CHECK: = cmph.gt(r0,r1)
define i32 @test31(i32 %Rs, i32 %Rt) #0 {
entry:
%0 = tail call i32 @llvm.hexagon.A4.cmphgt(i32 %Rs, i32 %Rt)
@@ -121,7 +121,7 @@ entry:
}
; CHECK-LABEL: @test32
-; CHECK: = cmph.gtu(r0, r1)
+; CHECK: = cmph.gtu(r0,r1)
define i32 @test32(i32 %Rs, i32 %Rt) #0 {
entry:
%0 = tail call i32 @llvm.hexagon.A4.cmphgtu(i32 %Rs, i32 %Rt)
@@ -129,7 +129,7 @@ entry:
}
; CHECK-LABEL: @test33
-; CHECK: = cmph.eq(r0, #-123)
+; CHECK: = cmph.eq(r0,#-123)
define i32 @test33(i32 %Rs) #0 {
entry:
%0 = tail call i32 @llvm.hexagon.A4.cmpheqi(i32 %Rs, i32 -123)
@@ -137,7 +137,7 @@ entry:
}
; CHECK-LABEL: @test34
-; CHECK: = cmph.gt(r0, #-3)
+; CHECK: = cmph.gt(r0,#-3)
define i32 @test34(i32 %Rs) #0 {
entry:
%0 = tail call i32 @llvm.hexagon.A4.cmphgti(i32 %Rs, i32 -3)
@@ -145,7 +145,7 @@ entry:
}
; CHECK-LABEL: @test35
-; CHECK: = cmph.gtu(r0, #13)
+; CHECK: = cmph.gtu(r0,#13)
define i32 @test35(i32 %Rs) #0 {
entry:
%0 = tail call i32 @llvm.hexagon.A4.cmphgtui(i32 %Rs, i32 13)
@@ -153,7 +153,7 @@ entry:
}
; CHECK-LABEL: @test40
-; CHECK: = vmux(p0, r3:2, r5:4)
+; CHECK: = vmux(p0,r3:2,r5:4)
define i64 @test40(i32 %Pu, i64 %Rs, i64 %Rt) #0 {
entry:
%0 = tail call i64 @llvm.hexagon.C2.vmux(i32 %Pu, i64 %Rs, i64 %Rt)
@@ -161,7 +161,7 @@ entry:
}
; CHECK-LABEL: @test41
-; CHECK: = any8(vcmpb.eq(r1:0, r3:2))
+; CHECK: = any8(vcmpb.eq(r1:0,r3:2))
define i32 @test41(i64 %Rs, i64 %Rt) #0 {
entry:
%0 = tail call i32 @llvm.hexagon.A4.vcmpbeq.any(i64 %Rs, i64 %Rt)
@@ -169,7 +169,7 @@ entry:
}
; CHECK-LABEL: @test50
-; CHECK: = add(r1:0, r3:2)
+; CHECK: = add(r1:0,r3:2)
define i64 @test50(i64 %Rs, i64 %Rt) #0 {
entry:
%0 = tail call i64 @llvm.hexagon.A2.addp(i64 %Rs, i64 %Rt)
@@ -177,7 +177,7 @@ entry:
}
; CHECK-LABEL: @test51
-; CHECK: = add(r1:0, r3:2):sat
+; CHECK: = add(r1:0,r3:2):sat
define i64 @test51(i64 %Rs, i64 %Rt) #0 {
entry:
%0 = tail call i64 @llvm.hexagon.A2.addpsat(i64 %Rs, i64 %Rt)
@@ -185,7 +185,7 @@ entry:
}
; CHECK-LABEL: @test52
-; CHECK: = sub(r1:0, r3:2)
+; CHECK: = sub(r1:0,r3:2)
define i64 @test52(i64 %Rs, i64 %Rt) #0 {
entry:
%0 = tail call i64 @llvm.hexagon.A2.subp(i64 %Rs, i64 %Rt)
@@ -193,7 +193,7 @@ entry:
}
; CHECK-LABEL: @test53
-; CHECK: = add(r1:0, r3:2):raw:
+; CHECK: = add(r1:0,r3:2):raw:
define i64 @test53(i32 %Rs, i64 %Rt) #0 {
entry:
%0 = tail call i64 @llvm.hexagon.A2.addsp(i32 %Rs, i64 %Rt)
@@ -201,7 +201,7 @@ entry:
}
; CHECK-LABEL: @test54
-; CHECK: = and(r1:0, r3:2)
+; CHECK: = and(r1:0,r3:2)
define i64 @test54(i64 %Rs, i64 %Rt) #0 {
entry:
%0 = tail call i64 @llvm.hexagon.A2.andp(i64 %Rs, i64 %Rt)
@@ -209,7 +209,7 @@ entry:
}
; CHECK-LABEL: @test55
-; CHECK: = or(r1:0, r3:2)
+; CHECK: = or(r1:0,r3:2)
define i64 @test55(i64 %Rs, i64 %Rt) #0 {
entry:
%0 = tail call i64 @llvm.hexagon.A2.orp(i64 %Rs, i64 %Rt)
@@ -217,7 +217,7 @@ entry:
}
; CHECK-LABEL: @test56
-; CHECK: = xor(r1:0, r3:2)
+; CHECK: = xor(r1:0,r3:2)
define i64 @test56(i64 %Rs, i64 %Rt) #0 {
entry:
%0 = tail call i64 @llvm.hexagon.A2.xorp(i64 %Rs, i64 %Rt)
@@ -225,7 +225,7 @@ entry:
}
; CHECK-LABEL: @test57
-; CHECK: = and(r1:0, ~r3:2)
+; CHECK: = and(r1:0,~r3:2)
define i64 @test57(i64 %Rs, i64 %Rt) #0 {
entry:
%0 = tail call i64 @llvm.hexagon.A4.andnp(i64 %Rs, i64 %Rt)
@@ -233,7 +233,7 @@ entry:
}
; CHECK-LABEL: @test58
-; CHECK: = or(r1:0, ~r3:2)
+; CHECK: = or(r1:0,~r3:2)
define i64 @test58(i64 %Rs, i64 %Rt) #0 {
entry:
%0 = tail call i64 @llvm.hexagon.A4.ornp(i64 %Rs, i64 %Rt)
@@ -241,7 +241,7 @@ entry:
}
; CHECK-LABEL: @test60
-; CHECK: = add(r0.l, r1.l)
+; CHECK: = add(r0.l,r1.l)
define i32 @test60(i32 %Rs, i32 %Rt) #0 {
entry:
%0 = tail call i32 @llvm.hexagon.A2.addh.l16.ll(i32 %Rs, i32 %Rt)
@@ -249,7 +249,7 @@ entry:
}
; CHECK-LABEL: @test61
-; CHECK: = add(r0.l, r1.h)
+; CHECK: = add(r0.l,r1.h)
define i32 @test61(i32 %Rs, i32 %Rt) #0 {
entry:
%0 = tail call i32 @llvm.hexagon.A2.addh.l16.hl(i32 %Rs, i32 %Rt)
@@ -257,7 +257,7 @@ entry:
}
; CHECK-LABEL: @test62
-; CHECK: = add(r0.l, r1.l):sat
+; CHECK: = add(r0.l,r1.l):sat
define i32 @test62(i32 %Rs, i32 %Rt) #0 {
entry:
%0 = tail call i32 @llvm.hexagon.A2.addh.l16.sat.ll(i32 %Rs, i32 %Rt)
@@ -265,7 +265,7 @@ entry:
}
; CHECK-LABEL: @test63
-; CHECK: = add(r0.l, r1.h):sat
+; CHECK: = add(r0.l,r1.h):sat
define i32 @test63(i32 %Rs, i32 %Rt) #0 {
entry:
%0 = tail call i32 @llvm.hexagon.A2.addh.l16.sat.hl(i32 %Rs, i32 %Rt)
@@ -273,7 +273,7 @@ entry:
}
; CHECK-LABEL: @test64
-; CHECK: = add(r0.l, r1.l):<<16
+; CHECK: = add(r0.l,r1.l):<<16
define i32 @test64(i32 %Rs, i32 %Rt) #0 {
entry:
%0 = tail call i32 @llvm.hexagon.A2.addh.h16.ll(i32 %Rs, i32 %Rt)
@@ -281,7 +281,7 @@ entry:
}
; CHECK-LABEL: @test65
-; CHECK: = add(r0.l, r1.h):<<16
+; CHECK: = add(r0.l,r1.h):<<16
define i32 @test65(i32 %Rs, i32 %Rt) #0 {
entry:
%0 = tail call i32 @llvm.hexagon.A2.addh.h16.lh(i32 %Rs, i32 %Rt)
@@ -289,7 +289,7 @@ entry:
}
; CHECK-LABEL: @test66
-; CHECK: = add(r0.h, r1.l):<<16
+; CHECK: = add(r0.h,r1.l):<<16
define i32 @test66(i32 %Rs, i32 %Rt) #0 {
entry:
%0 = tail call i32 @llvm.hexagon.A2.addh.h16.hl(i32 %Rs, i32 %Rt)
@@ -297,7 +297,7 @@ entry:
}
; CHECK-LABEL: @test67
-; CHECK: = add(r0.h, r1.h):<<16
+; CHECK: = add(r0.h,r1.h):<<16
define i32 @test67(i32 %Rs, i32 %Rt) #0 {
entry:
%0 = tail call i32 @llvm.hexagon.A2.addh.h16.hh(i32 %Rs, i32 %Rt)
@@ -305,7 +305,7 @@ entry:
}
; CHECK-LABEL: @test68
-; CHECK: = add(r0.l, r1.l):sat:<<16
+; CHECK: = add(r0.l,r1.l):sat:<<16
define i32 @test68(i32 %Rs, i32 %Rt) #0 {
entry:
%0 = tail call i32 @llvm.hexagon.A2.addh.h16.sat.ll(i32 %Rs, i32 %Rt)
@@ -313,7 +313,7 @@ entry:
}
; CHECK-LABEL: @test69
-; CHECK: = add(r0.l, r1.h):sat:<<16
+; CHECK: = add(r0.l,r1.h):sat:<<16
define i32 @test69(i32 %Rs, i32 %Rt) #0 {
entry:
%0 = tail call i32 @llvm.hexagon.A2.addh.h16.sat.lh(i32 %Rs, i32 %Rt)
@@ -321,7 +321,7 @@ entry:
}
; CHECK-LABEL: @test6A
-; CHECK: = add(r0.h, r1.l):sat:<<16
+; CHECK: = add(r0.h,r1.l):sat:<<16
define i32 @test6A(i32 %Rs, i32 %Rt) #0 {
entry:
%0 = tail call i32 @llvm.hexagon.A2.addh.h16.sat.hl(i32 %Rs, i32 %Rt)
@@ -329,7 +329,7 @@ entry:
}
; CHECK-LABEL: @test6B
-; CHECK: = add(r0.h, r1.h):sat:<<16
+; CHECK: = add(r0.h,r1.h):sat:<<16
define i32 @test6B(i32 %Rs, i32 %Rt) #0 {
entry:
%0 = tail call i32 @llvm.hexagon.A2.addh.h16.sat.hh(i32 %Rs, i32 %Rt)
@@ -337,7 +337,7 @@ entry:
}
; CHECK-LABEL: @test70
-; CHECK: = sub(r0.l, r1.l)
+; CHECK: = sub(r0.l,r1.l)
define i32 @test70(i32 %Rs, i32 %Rt) #0 {
entry:
%0 = tail call i32 @llvm.hexagon.A2.subh.l16.ll(i32 %Rs, i32 %Rt)
@@ -345,7 +345,7 @@ entry:
}
; CHECK-LABEL: @test71
-; CHECK: = sub(r0.l, r1.h)
+; CHECK: = sub(r0.l,r1.h)
define i32 @test71(i32 %Rs, i32 %Rt) #0 {
entry:
%0 = tail call i32 @llvm.hexagon.A2.subh.l16.hl(i32 %Rs, i32 %Rt)
@@ -353,7 +353,7 @@ entry:
}
; CHECK-LABEL: @test72
-; CHECK: = sub(r0.l, r1.l):sat
+; CHECK: = sub(r0.l,r1.l):sat
define i32 @test72(i32 %Rs, i32 %Rt) #0 {
entry:
%0 = tail call i32 @llvm.hexagon.A2.subh.l16.sat.ll(i32 %Rs, i32 %Rt)
@@ -361,7 +361,7 @@ entry:
}
; CHECK-LABEL: @test73
-; CHECK: = sub(r0.l, r1.h):sat
+; CHECK: = sub(r0.l,r1.h):sat
define i32 @test73(i32 %Rs, i32 %Rt) #0 {
entry:
%0 = tail call i32 @llvm.hexagon.A2.subh.l16.sat.hl(i32 %Rs, i32 %Rt)
@@ -369,7 +369,7 @@ entry:
}
; CHECK-LABEL: @test74
-; CHECK: = sub(r0.l, r1.l):<<16
+; CHECK: = sub(r0.l,r1.l):<<16
define i32 @test74(i32 %Rs, i32 %Rt) #0 {
entry:
%0 = tail call i32 @llvm.hexagon.A2.subh.h16.ll(i32 %Rs, i32 %Rt)
@@ -377,7 +377,7 @@ entry:
}
; CHECK-LABEL: @test75
-; CHECK: = sub(r0.l, r1.h):<<16
+; CHECK: = sub(r0.l,r1.h):<<16
define i32 @test75(i32 %Rs, i32 %Rt) #0 {
entry:
%0 = tail call i32 @llvm.hexagon.A2.subh.h16.lh(i32 %Rs, i32 %Rt)
@@ -385,7 +385,7 @@ entry:
}
; CHECK-LABEL: @test76
-; CHECK: = sub(r0.h, r1.l):<<16
+; CHECK: = sub(r0.h,r1.l):<<16
define i32 @test76(i32 %Rs, i32 %Rt) #0 {
entry:
%0 = tail call i32 @llvm.hexagon.A2.subh.h16.hl(i32 %Rs, i32 %Rt)
@@ -393,7 +393,7 @@ entry:
}
; CHECK-LABEL: @test77
-; CHECK: = sub(r0.h, r1.h):<<16
+; CHECK: = sub(r0.h,r1.h):<<16
define i32 @test77(i32 %Rs, i32 %Rt) #0 {
entry:
%0 = tail call i32 @llvm.hexagon.A2.subh.h16.hh(i32 %Rs, i32 %Rt)
@@ -401,7 +401,7 @@ entry:
}
; CHECK-LABEL: @test78
-; CHECK: = sub(r0.l, r1.l):sat:<<16
+; CHECK: = sub(r0.l,r1.l):sat:<<16
define i32 @test78(i32 %Rs, i32 %Rt) #0 {
entry:
%0 = tail call i32 @llvm.hexagon.A2.subh.h16.sat.ll(i32 %Rs, i32 %Rt)
@@ -409,7 +409,7 @@ entry:
}
; CHECK-LABEL: @test79
-; CHECK: = sub(r0.l, r1.h):sat:<<16
+; CHECK: = sub(r0.l,r1.h):sat:<<16
define i32 @test79(i32 %Rs, i32 %Rt) #0 {
entry:
%0 = tail call i32 @llvm.hexagon.A2.subh.h16.sat.lh(i32 %Rs, i32 %Rt)
@@ -417,7 +417,7 @@ entry:
}
; CHECK-LABEL: @test7A
-; CHECK: = sub(r0.h, r1.l):sat:<<16
+; CHECK: = sub(r0.h,r1.l):sat:<<16
define i32 @test7A(i32 %Rs, i32 %Rt) #0 {
entry:
%0 = tail call i32 @llvm.hexagon.A2.subh.h16.sat.hl(i32 %Rs, i32 %Rt)
@@ -425,7 +425,7 @@ entry:
}
; CHECK-LABEL: @test7B
-; CHECK: = sub(r0.h, r1.h):sat:<<16
+; CHECK: = sub(r0.h,r1.h):sat:<<16
define i32 @test7B(i32 %Rs, i32 %Rt) #0 {
entry:
%0 = tail call i32 @llvm.hexagon.A2.subh.h16.sat.hh(i32 %Rs, i32 %Rt)
@@ -433,7 +433,7 @@ entry:
}
; CHECK-LABEL: @test90
-; CHECK: = and(#1, asl(r0, #2))
+; CHECK: = and(#1,asl(r0,#2))
define i32 @test90(i32 %Rs) #0 {
entry:
%0 = tail call i32 @llvm.hexagon.S4.andi.asl.ri(i32 1, i32 %Rs, i32 2)
@@ -441,7 +441,7 @@ entry:
}
; CHECK-LABEL: @test91
-; CHECK: = or(#1, asl(r0, #2))
+; CHECK: = or(#1,asl(r0,#2))
define i32 @test91(i32 %Rs) #0 {
entry:
%0 = tail call i32 @llvm.hexagon.S4.ori.asl.ri(i32 1, i32 %Rs, i32 2)
@@ -449,7 +449,7 @@ entry:
}
; CHECK-LABEL: @test92
-; CHECK: = add(#1, asl(r0, #2))
+; CHECK: = add(#1,asl(r0,#2))
define i32 @test92(i32 %Rs) #0 {
entry:
%0 = tail call i32 @llvm.hexagon.S4.addi.asl.ri(i32 1, i32 %Rs, i32 2)
@@ -457,7 +457,7 @@ entry:
}
; CHECK-LABEL: @test93
-; CHECK: = sub(#1, asl(r0, #2))
+; CHECK: = sub(#1,asl(r0,#2))
define i32 @test93(i32 %Rs) #0 {
entry:
%0 = tail call i32 @llvm.hexagon.S4.subi.asl.ri(i32 1, i32 %Rs, i32 2)
@@ -465,7 +465,7 @@ entry:
}
; CHECK-LABEL: @test94
-; CHECK: = and(#1, lsr(r0, #2))
+; CHECK: = and(#1,lsr(r0,#2))
define i32 @test94(i32 %Rs) #0 {
entry:
%0 = tail call i32 @llvm.hexagon.S4.andi.lsr.ri(i32 1, i32 %Rs, i32 2)
@@ -473,7 +473,7 @@ entry:
}
; CHECK-LABEL: @test95
-; CHECK: = or(#1, lsr(r0, #2))
+; CHECK: = or(#1,lsr(r0,#2))
define i32 @test95(i32 %Rs) #0 {
entry:
%0 = tail call i32 @llvm.hexagon.S4.ori.lsr.ri(i32 1, i32 %Rs, i32 2)
@@ -481,7 +481,7 @@ entry:
}
; CHECK-LABEL: @test96
-; CHECK: = add(#1, lsr(r0, #2))
+; CHECK: = add(#1,lsr(r0,#2))
define i32 @test96(i32 %Rs) #0 {
entry:
%0 = tail call i32 @llvm.hexagon.S4.addi.lsr.ri(i32 1, i32 %Rs, i32 2)
@@ -489,7 +489,7 @@ entry:
}
; CHECK-LABEL: @test97
-; CHECK: = sub(#1, lsr(r0, #2))
+; CHECK: = sub(#1,lsr(r0,#2))
define i32 @test97(i32 %Rs) #0 {
entry:
%0 = tail call i32 @llvm.hexagon.S4.subi.lsr.ri(i32 1, i32 %Rs, i32 2)
@@ -497,7 +497,7 @@ entry:
}
; CHECK-LABEL: @test100
-; CHECK: = bitsplit(r0, r1)
+; CHECK: = bitsplit(r0,r1)
define i64 @test100(i32 %Rs, i32 %Rt) #0 {
entry:
%0 = tail call i64 @llvm.hexagon.A4.bitsplit(i32 %Rs, i32 %Rt)
@@ -505,7 +505,7 @@ entry:
}
; CHECK-LABEL: @test101
-; CHECK: = modwrap(r0, r1)
+; CHECK: = modwrap(r0,r1)
define i32 @test101(i32 %Rs, i32 %Rt) #0 {
entry:
%0 = tail call i32 @llvm.hexagon.A4.modwrapu(i32 %Rs, i32 %Rt)
@@ -513,7 +513,7 @@ entry:
}
; CHECK-LABEL: @test102
-; CHECK: = parity(r1:0, r3:2)
+; CHECK: = parity(r1:0,r3:2)
define i32 @test102(i64 %Rs, i64 %Rt) #0 {
entry:
%0 = tail call i32 @llvm.hexagon.S2.parityp(i64 %Rs, i64 %Rt)
@@ -521,7 +521,7 @@ entry:
}
; CHECK-LABEL: @test103
-; CHECK: = parity(r0, r1)
+; CHECK: = parity(r0,r1)
define i32 @test103(i32 %Rs, i32 %Rt) #0 {
entry:
%0 = tail call i32 @llvm.hexagon.S4.parity(i32 %Rs, i32 %Rt)
Modified: llvm/trunk/test/CodeGen/Hexagon/args.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/args.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/args.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/args.ll Fri Feb 10 09:33:13 2017
@@ -1,8 +1,8 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
-; CHECK: r5:4 = combine(#6, #5)
-; CHECK: r3:2 = combine(#4, #3)
-; CHECK: r1:0 = combine(#2, #1)
-; CHECK: memw(r29+#0)=#7
+; CHECK: r5:4 = combine(#6,#5)
+; CHECK: r3:2 = combine(#4,#3)
+; CHECK: r1:0 = combine(#2,#1)
+; CHECK: memw(r29+#0) = #7
define void @foo() nounwind {
Modified: llvm/trunk/test/CodeGen/Hexagon/bit-eval.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/bit-eval.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/bit-eval.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/bit-eval.ll Fri Feb 10 09:33:13 2017
@@ -20,7 +20,7 @@ entry:
}
; CHECK-LABEL: test3:
-; CHECK: r1:0 = combine(#0, #1)
+; CHECK: r1:0 = combine(#0,#1)
define i64 @test3() #0 {
entry:
%0 = tail call i64 @llvm.hexagon.S4.extractp(i64 -1, i32 63, i32 63)
Modified: llvm/trunk/test/CodeGen/Hexagon/bit-skip-byval.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/bit-skip-byval.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/bit-skip-byval.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/bit-skip-byval.ll Fri Feb 10 09:33:13 2017
@@ -1,7 +1,7 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
;
; Either and or zxtb.
-; CHECK: r0 = and(r1, #255)
+; CHECK: r0 = and(r1,#255)
%struct.t0 = type { i32 }
Modified: llvm/trunk/test/CodeGen/Hexagon/branchfolder-keep-impdef.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/branchfolder-keep-impdef.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/branchfolder-keep-impdef.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/branchfolder-keep-impdef.ll Fri Feb 10 09:33:13 2017
@@ -3,7 +3,7 @@
; Check that the testcase compiles successfully. Expect that if-conversion
; took place.
; CHECK-LABEL: fred:
-; CHECK: if (!p0) r1 = memw(r0 + #0)
+; CHECK: if (!p0) r1 = memw(r0+#0)
target triple = "hexagon"
Modified: llvm/trunk/test/CodeGen/Hexagon/brev_ld.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/brev_ld.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/brev_ld.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/brev_ld.ll Fri Feb 10 09:33:13 2017
@@ -29,7 +29,7 @@ entry:
%1 = bitcast i64* %inputLR to i8*
%sub = sub i32 13, %shr1
%shl = shl i32 1, %sub
-; CHECK: = memd(r{{[0-9]*}} ++ m{{[0-1]}}:brev)
+; CHECK: = memd(r{{[0-9]*}}++m{{[0-1]}}:brev)
%2 = call i8* @llvm.hexagon.brev.ldd(i8* %0, i8* %1, i32 %shl)
%3 = bitcast i8* %1 to i64*
%4 = load i64, i64* %3, align 8, !tbaa !0
@@ -49,7 +49,7 @@ entry:
%1 = bitcast i32* %inputLR to i8*
%sub = sub i32 14, %shr1
%shl = shl i32 1, %sub
-; CHECK: = memw(r{{[0-9]*}} ++ m{{[0-1]}}:brev)
+; CHECK: = memw(r{{[0-9]*}}++m{{[0-1]}}:brev)
%2 = call i8* @llvm.hexagon.brev.ldw(i8* %0, i8* %1, i32 %shl)
%3 = bitcast i8* %1 to i32*
%4 = load i32, i32* %3, align 4, !tbaa !2
@@ -69,7 +69,7 @@ entry:
%1 = bitcast i16* %inputLR to i8*
%sub = sub i32 15, %shr1
%shl = shl i32 1, %sub
-; CHECK: = memh(r{{[0-9]*}} ++ m0:brev)
+; CHECK: = memh(r{{[0-9]*}}++m0:brev)
%2 = call i8* @llvm.hexagon.brev.ldh(i8* %0, i8* %1, i32 %shl)
%3 = bitcast i8* %1 to i16*
%4 = load i16, i16* %3, align 2, !tbaa !3
@@ -89,7 +89,7 @@ entry:
%1 = bitcast i16* %inputLR to i8*
%sub = sub i32 15, %shr1
%shl = shl i32 1, %sub
-; CHECK: = memuh(r{{[0-9]*}} ++ m0:brev)
+; CHECK: = memuh(r{{[0-9]*}}++m0:brev)
%2 = call i8* @llvm.hexagon.brev.lduh(i8* %0, i8* %1, i32 %shl)
%3 = bitcast i8* %1 to i16*
%4 = load i16, i16* %3, align 2, !tbaa !3
@@ -108,7 +108,7 @@ entry:
%0 = bitcast i16* %arrayidx to i8*
%sub = sub nsw i32 16, %shr1
%shl = shl i32 1, %sub
-; CHECK: = memub(r{{[0-9]*}} ++ m{{[0-1]}}:brev)
+; CHECK: = memub(r{{[0-9]*}}++m{{[0-1]}}:brev)
%1 = call i8* @llvm.hexagon.brev.ldub(i8* %0, i8* %inputLR, i32 %shl)
%2 = load i8, i8* %inputLR, align 1, !tbaa !0
ret i8 %2
@@ -126,7 +126,7 @@ entry:
%0 = bitcast i16* %arrayidx to i8*
%sub = sub nsw i32 16, %shr1
%shl = shl i32 1, %sub
-; CHECK: = memb(r{{[0-9]*}} ++ m{{[0-1]}}:brev)
+; CHECK: = memb(r{{[0-9]*}}++m{{[0-1]}}:brev)
%1 = call i8* @llvm.hexagon.brev.ldb(i8* %0, i8* %inputLR, i32 %shl)
%2 = load i8, i8* %inputLR, align 1, !tbaa !0
ret i8 %2
Modified: llvm/trunk/test/CodeGen/Hexagon/brev_st.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/brev_st.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/brev_st.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/brev_st.ll Fri Feb 10 09:33:13 2017
@@ -26,7 +26,7 @@ entry:
%0 = bitcast i16* %arrayidx to i8*
%sub = sub i32 13, %shr2
%shl = shl i32 1, %sub
-; CHECK: memd(r{{[0-9]*}} ++ m{{[0-1]}}:brev)
+; CHECK: memd(r{{[0-9]*}}++m{{[0-1]}}:brev)
%1 = tail call i8* @llvm.hexagon.brev.std(i8* %0, i64 undef, i32 %shl)
ret i64 0
}
@@ -42,7 +42,7 @@ entry:
%0 = bitcast i16* %arrayidx to i8*
%sub = sub i32 14, %shr1
%shl = shl i32 1, %sub
-; CHECK: memw(r{{[0-9]*}} ++ m{{[0-1]}}:brev)
+; CHECK: memw(r{{[0-9]*}}++m{{[0-1]}}:brev)
%1 = tail call i8* @llvm.hexagon.brev.stw(i8* %0, i32 undef, i32 %shl)
ret i32 0
}
@@ -58,7 +58,7 @@ entry:
%0 = bitcast i16* %arrayidx to i8*
%sub = sub i32 15, %shr2
%shl = shl i32 1, %sub
-; CHECK: memh(r{{[0-9]*}} ++ m{{[0-1]}}:brev)
+; CHECK: memh(r{{[0-9]*}}++m{{[0-1]}}:brev)
%1 = tail call i8* @llvm.hexagon.brev.sth(i8* %0, i32 0, i32 %shl)
ret i16 0
}
@@ -74,7 +74,7 @@ entry:
%0 = bitcast i16* %arrayidx to i8*
%sub = sub i32 15, %shr2
%shl = shl i32 1, %sub
-; CHECK: memh(r{{[0-9]*}} ++ m{{[0-1]}}:brev){{ *}}={{ *}}r{{[0-9]*}}.h
+; CHECK: memh(r{{[0-9]*}}++m{{[0-1]}}:brev) = r{{[0-9]*}}.h
%1 = tail call i8* @llvm.hexagon.brev.sthhi(i8* %0, i32 0, i32 %shl)
ret i16 0
}
@@ -89,7 +89,7 @@ entry:
%arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom
%0 = bitcast i16* %arrayidx to i8*
%sub = sub nsw i32 16, %shr2
- ; CHECK: memb(r{{[0-9]*}} ++ m{{[0-1]}}:brev)
+ ; CHECK: memb(r{{[0-9]*}}++m{{[0-1]}}:brev)
%shl = shl i32 1, %sub
%1 = tail call i8* @llvm.hexagon.brev.stb(i8* %0, i32 0, i32 %shl)
ret i8 0
Modified: llvm/trunk/test/CodeGen/Hexagon/cext-valid-packet1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/cext-valid-packet1.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/cext-valid-packet1.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/cext-valid-packet1.ll Fri Feb 10 09:33:13 2017
@@ -3,8 +3,8 @@
; Check that the packetizer generates valid packets with constant
; extended instructions.
; CHECK: {
-; CHECK-NEXT: r{{[0-9]+}}{{ *}}={{ *}}add(r{{[0-9]+}}, ##{{[0-9]+}})
-; CHECK-NEXT: r{{[0-9]+}}{{ *}}={{ *}}add(r{{[0-9]+}}, ##{{[0-9]+}})
+; CHECK-NEXT: r{{[0-9]+}} = add(r{{[0-9]+}},##{{[0-9]+}})
+; CHECK-NEXT: r{{[0-9]+}} = add(r{{[0-9]+}},##{{[0-9]+}})
; CHECK-NEXT: }
define i32 @check-packet1(i32 %a, i32 %b, i32 %c) nounwind readnone {
Modified: llvm/trunk/test/CodeGen/Hexagon/circ_ld.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/circ_ld.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/circ_ld.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/circ_ld.ll Fri Feb 10 09:33:13 2017
@@ -26,7 +26,7 @@ entry:
%arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom
%0 = bitcast i16* %arrayidx to i8*
%or = or i32 %shr1, 33554432
-; CHECK: = memb(r{{[0-9]*.}}++{{.}}#-1:circ(m{{[0-1]}}))
+; CHECK: = memb(r{{[0-9]*}}++#-1:circ(m{{[0-1]}}))
%1 = call i8* @llvm.hexagon.circ.ldb(i8* %0, i8* %inputLR, i32 %or, i32 -1)
%2 = load i8, i8* %inputLR, align 1, !tbaa !0
ret i8 %2
@@ -45,7 +45,7 @@ entry:
%1 = bitcast i64* %inputLR to i8*
%shl = shl nuw nsw i32 %shr1, 3
%or = or i32 %shl, 83886080
-; CHECK: = memd(r{{[0-9]*.}}++{{.}}#-8:circ(m{{[0-1]}}))
+; CHECK: = memd(r{{[0-9]*}}++#-8:circ(m{{[0-1]}}))
%2 = call i8* @llvm.hexagon.circ.ldd(i8* %0, i8* %1, i32 %or, i32 -8)
%3 = bitcast i8* %1 to i64*
%4 = load i64, i64* %3, align 8, !tbaa !0
@@ -64,7 +64,7 @@ entry:
%0 = bitcast i16* %arrayidx to i8*
%1 = bitcast i16* %inputLR to i8*
%or = or i32 %shr1, 50331648
-; CHECK: = memh(r{{[0-9]*.}}++{{.}}#-2:circ(m{{[0-1]}}))
+; CHECK: = memh(r{{[0-9]*}}++#-2:circ(m{{[0-1]}}))
%2 = call i8* @llvm.hexagon.circ.ldh(i8* %0, i8* %1, i32 %or, i32 -2)
%3 = bitcast i8* %1 to i16*
%4 = load i16, i16* %3, align 2, !tbaa !2
@@ -82,7 +82,7 @@ entry:
%arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom
%0 = bitcast i16* %arrayidx to i8*
%or = or i32 %shr1, 33554432
-; CHECK: = memub(r{{[0-9]*.}}++{{.}}#-1:circ(m{{[0-1]}}))
+; CHECK: = memub(r{{[0-9]*}}++#-1:circ(m{{[0-1]}}))
%1 = call i8* @llvm.hexagon.circ.ldub(i8* %0, i8* %inputLR, i32 %or, i32 -1)
%2 = load i8, i8* %inputLR, align 1, !tbaa !0
ret i8 %2
@@ -100,7 +100,7 @@ entry:
%0 = bitcast i16* %arrayidx to i8*
%1 = bitcast i16* %inputLR to i8*
%or = or i32 %shr1, 50331648
-; CHECK: = memuh(r{{[0-9]*.}}++{{.}}#-2:circ(m{{[0-1]}}))
+; CHECK: = memuh(r{{[0-9]*}}++#-2:circ(m{{[0-1]}}))
%2 = call i8* @llvm.hexagon.circ.lduh(i8* %0, i8* %1, i32 %or, i32 -2)
%3 = bitcast i8* %1 to i16*
%4 = load i16, i16* %3, align 2, !tbaa !2
@@ -120,7 +120,7 @@ entry:
%1 = bitcast i32* %inputLR to i8*
%shl = shl nuw nsw i32 %shr1, 2
%or = or i32 %shl, 67108864
-; CHECK: = memw(r{{[0-9]*.}}++{{.}}#-4:circ(m{{[0-1]}}))
+; CHECK: = memw(r{{[0-9]*}}++#-4:circ(m{{[0-1]}}))
%2 = call i8* @llvm.hexagon.circ.ldw(i8* %0, i8* %1, i32 %or, i32 -4)
%3 = bitcast i8* %1 to i32*
%4 = load i32, i32* %3, align 4, !tbaa !3
Modified: llvm/trunk/test/CodeGen/Hexagon/circ_ldw.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/circ_ldw.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/circ_ldw.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/circ_ldw.ll Fri Feb 10 09:33:13 2017
@@ -1,5 +1,5 @@
; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
-; CHECK: r{{[0-9]*}} = memw(r{{[0-9]*.}}++{{.}}#-4:circ(m0))
+; CHECK: r{{[0-9]*}} = memw(r{{[0-9]*}}++#-4:circ(m0))
%union.vect64 = type { i64 }
Modified: llvm/trunk/test/CodeGen/Hexagon/circ_st.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/circ_st.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/circ_st.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/circ_st.ll Fri Feb 10 09:33:13 2017
@@ -23,7 +23,7 @@ entry:
%arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom
%0 = bitcast i16* %arrayidx to i8*
%or = or i32 %shr2, 33554432
-; CHECK: memb(r{{[0-9]*}}{{.}}++{{.}}#-1:circ(m{{[0-1]}}))
+; CHECK: memb(r{{[0-9]*}}++#-1:circ(m{{[0-1]}}))
%1 = tail call i8* @llvm.hexagon.circ.stb(i8* %0, i32 0, i32 %or, i32 -1)
ret i8 0
}
@@ -39,7 +39,7 @@ entry:
%0 = bitcast i16* %arrayidx to i8*
%shl = shl nuw nsw i32 %shr1, 3
%or = or i32 %shl, 83886080
-; CHECK: memd(r{{[0-9]*}}{{.}}++{{.}}#-8:circ(m{{[0-1]}}))
+; CHECK: memd(r{{[0-9]*}}++#-8:circ(m{{[0-1]}}))
%1 = tail call i8* @llvm.hexagon.circ.std(i8* %0, i64 undef, i32 %or, i32 -8)
ret i64 0
}
@@ -54,7 +54,7 @@ entry:
%arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom
%0 = bitcast i16* %arrayidx to i8*
%or = or i32 %shr2, 50331648
-; CHECK: memh(r{{[0-9]*}}{{.}}++{{.}}#-2:circ(m{{[0-1]}}))
+; CHECK: memh(r{{[0-9]*}}++#-2:circ(m{{[0-1]}}))
%1 = tail call i8* @llvm.hexagon.circ.sth(i8* %0, i32 0, i32 %or, i32 -2)
ret i16 0
}
@@ -69,7 +69,7 @@ entry:
%arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom
%0 = bitcast i16* %arrayidx to i8*
%or = or i32 %shr2, 50331648
-; CHECK: memh(r{{[0-9]*}}{{.}}++{{.}}#-2:circ(m{{[0-1]}})){{ *}}={{ *}}r{{[0-9]*}}.h
+; CHECK: memh(r{{[0-9]*}}++#-2:circ(m{{[0-1]}})) = r{{[0-9]*}}.h
%1 = tail call i8* @llvm.hexagon.circ.sthhi(i8* %0, i32 0, i32 %or, i32 -2)
ret i16 0
}
@@ -85,7 +85,7 @@ entry:
%0 = bitcast i16* %arrayidx to i8*
%shl = shl nuw nsw i32 %shr1, 2
%or = or i32 %shl, 67108864
-; CHECK: memw(r{{[0-9]*}}{{.}}++{{.}}#-4:circ(m{{[0-1]}}))
+; CHECK: memw(r{{[0-9]*}}++#-4:circ(m{{[0-1]}}))
%1 = tail call i8* @llvm.hexagon.circ.stw(i8* %0, i32 undef, i32 %or, i32 -4)
ret i32 0
}
Modified: llvm/trunk/test/CodeGen/Hexagon/clr_set_toggle.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/clr_set_toggle.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/clr_set_toggle.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/clr_set_toggle.ll Fri Feb 10 09:33:13 2017
@@ -4,7 +4,7 @@
define i32 @my_clrbit(i32 %x) nounwind {
entry:
; CHECK-LABEL: my_clrbit
-; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #31)
+; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}},#31)
%x.addr = alloca i32, align 4
store i32 %x, i32* %x.addr, align 4
%0 = load i32, i32* %x.addr, align 4
@@ -15,7 +15,7 @@ entry:
define i64 @my_clrbit2(i64 %x) nounwind {
entry:
; CHECK-LABEL: my_clrbit2
-; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #31)
+; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}},#31)
%x.addr = alloca i64, align 8
store i64 %x, i64* %x.addr, align 8
%0 = load i64, i64* %x.addr, align 8
@@ -26,7 +26,7 @@ entry:
define i64 @my_clrbit3(i64 %x) nounwind {
entry:
; CHECK-LABEL: my_clrbit3
-; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #31)
+; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}},#31)
%x.addr = alloca i64, align 8
store i64 %x, i64* %x.addr, align 8
%0 = load i64, i64* %x.addr, align 8
@@ -37,7 +37,7 @@ entry:
define i32 @my_clrbit4(i32 %x) nounwind {
entry:
; CHECK-LABEL: my_clrbit4
-; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #13)
+; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}},#13)
%x.addr = alloca i32, align 4
store i32 %x, i32* %x.addr, align 4
%0 = load i32, i32* %x.addr, align 4
@@ -48,7 +48,7 @@ entry:
define i64 @my_clrbit5(i64 %x) nounwind {
entry:
; CHECK-LABEL: my_clrbit5
-; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #13)
+; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}},#13)
%x.addr = alloca i64, align 8
store i64 %x, i64* %x.addr, align 8
%0 = load i64, i64* %x.addr, align 8
@@ -59,7 +59,7 @@ entry:
define i64 @my_clrbit6(i64 %x) nounwind {
entry:
; CHECK-LABEL: my_clrbit6
-; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #27)
+; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}},#27)
%x.addr = alloca i64, align 8
store i64 %x, i64* %x.addr, align 8
%0 = load i64, i64* %x.addr, align 8
@@ -70,7 +70,7 @@ entry:
define zeroext i16 @my_setbit(i16 zeroext %crc) nounwind {
entry:
; CHECK-LABEL: my_setbit
-; CHECK: memh(r{{[0-9]+}}+#{{[0-9]+}}){{ *}}={{ *}}setbit(#15)
+; CHECK: memh(r{{[0-9]+}}+#{{[0-9]+}}) = setbit(#15)
%crc.addr = alloca i16, align 2
store i16 %crc, i16* %crc.addr, align 2
%0 = load i16, i16* %crc.addr, align 2
@@ -85,7 +85,7 @@ entry:
define i32 @my_setbit2(i32 %x) nounwind {
entry:
; CHECK-LABEL: my_setbit2
-; CHECK: r{{[0-9]+}}{{ *}}={{ *}}setbit(r{{[0-9]+}}, #15)
+; CHECK: r{{[0-9]+}} = setbit(r{{[0-9]+}},#15)
%x.addr = alloca i32, align 4
store i32 %x, i32* %x.addr, align 4
%0 = load i32, i32* %x.addr, align 4
@@ -96,7 +96,7 @@ entry:
define i64 @my_setbit3(i64 %x) nounwind {
entry:
; CHECK-LABEL: my_setbit3
-; CHECK: r{{[0-9]+}}{{ *}}={{ *}}setbit(r{{[0-9]+}}, #15)
+; CHECK: r{{[0-9]+}} = setbit(r{{[0-9]+}},#15)
%x.addr = alloca i64, align 8
store i64 %x, i64* %x.addr, align 8
%0 = load i64, i64* %x.addr, align 8
@@ -107,7 +107,7 @@ entry:
define i32 @my_setbit4(i32 %x) nounwind {
entry:
; CHECK-LABEL: my_setbit4
-; CHECK: r{{[0-9]+}}{{ *}}={{ *}}setbit(r{{[0-9]+}}, #31)
+; CHECK: r{{[0-9]+}} = setbit(r{{[0-9]+}},#31)
%x.addr = alloca i32, align 4
store i32 %x, i32* %x.addr, align 4
%0 = load i32, i32* %x.addr, align 4
@@ -118,7 +118,7 @@ entry:
define i64 @my_setbit5(i64 %x) nounwind {
entry:
; CHECK-LABEL: my_setbit5
-; CHECK: r{{[0-9]+}}{{ *}}={{ *}}setbit(r{{[0-9]+}}, #13)
+; CHECK: r{{[0-9]+}} = setbit(r{{[0-9]+}},#13)
%x.addr = alloca i64, align 8
store i64 %x, i64* %x.addr, align 8
%0 = load i64, i64* %x.addr, align 8
@@ -129,7 +129,7 @@ entry:
define zeroext i16 @my_togglebit(i16 zeroext %crc) nounwind {
entry:
; CHECK-LABEL: my_togglebit
-; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #15)
+; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}},#15)
%crc.addr = alloca i16, align 2
store i16 %crc, i16* %crc.addr, align 2
%0 = load i16, i16* %crc.addr, align 2
@@ -144,7 +144,7 @@ entry:
define i32 @my_togglebit2(i32 %x) nounwind {
entry:
; CHECK-LABEL: my_togglebit2
-; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #15)
+; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}},#15)
%x.addr = alloca i32, align 4
store i32 %x, i32* %x.addr, align 4
%0 = load i32, i32* %x.addr, align 4
@@ -155,7 +155,7 @@ entry:
define i64 @my_togglebit3(i64 %x) nounwind {
entry:
; CHECK-LABEL: my_togglebit3
-; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #15)
+; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}},#15)
%x.addr = alloca i64, align 8
store i64 %x, i64* %x.addr, align 8
%0 = load i64, i64* %x.addr, align 8
@@ -166,7 +166,7 @@ entry:
define i64 @my_togglebit4(i64 %x) nounwind {
entry:
; CHECK-LABEL: my_togglebit4
-; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #20)
+; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}},#20)
%x.addr = alloca i64, align 8
store i64 %x, i64* %x.addr, align 8
%0 = load i64, i64* %x.addr, align 8
Modified: llvm/trunk/test/CodeGen/Hexagon/cmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/cmp.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/cmp.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/cmp.ll Fri Feb 10 09:33:13 2017
@@ -9,7 +9,7 @@ entry:
%1 = call i32 @llvm.hexagon.C2.cmpeq(i32 %0, i32 1)
ret i32 %1
}
-; CHECK: { p{{[0-3]}} = cmp.eq(r{{[0-9]}}, r{{[0-9]}})
+; CHECK: { p{{[0-3]}} = cmp.eq(r{{[0-9]}},r{{[0-9]}})
; Function Attrs: nounwind readnone
declare i32 @llvm.hexagon.C2.cmpeq(i32, i32) #1
@@ -23,7 +23,7 @@ entry:
%1 = call i32 @llvm.hexagon.C2.cmpgt(i32 %0, i32 2)
ret i32 %1
}
-; CHECK: { p{{[0-3]}} = cmp.gt(r{{[0-9]}}, r{{[0-9]}})
+; CHECK: { p{{[0-3]}} = cmp.gt(r{{[0-9]}},r{{[0-9]}})
; Function Attrs: nounwind readnone
declare i32 @llvm.hexagon.C2.cmpgt(i32, i32) #1
@@ -37,7 +37,7 @@ entry:
%1 = call i32 @llvm.hexagon.C2.cmpgtu(i32 %0, i32 3)
ret i32 %1
}
-; CHECK: { p{{[0-3]}} = cmp.gtu(r{{[0-9]}}, r{{[0-9]}})
+; CHECK: { p{{[0-3]}} = cmp.gtu(r{{[0-9]}},r{{[0-9]}})
; Function Attrs: nounwind readnone
declare i32 @llvm.hexagon.C2.cmpgtu(i32, i32) #1
@@ -51,7 +51,7 @@ entry:
%1 = call i32 @llvm.hexagon.C2.cmplt(i32 %0, i32 4)
ret i32 %1
}
-; CHECK: { p{{[0-3]}} = cmp.gt(r{{[0-9]}}, r{{[0-9]}})
+; CHECK: { p{{[0-3]}} = cmp.gt(r{{[0-9]}},r{{[0-9]}})
; Function Attrs: nounwind readnone
declare i32 @llvm.hexagon.C2.cmplt(i32, i32) #1
@@ -65,7 +65,7 @@ entry:
%1 = call i32 @llvm.hexagon.C2.cmpltu(i32 %0, i32 5)
ret i32 %1
}
-; CHECK: { p{{[0-3]}} = cmp.gtu(r{{[0-9]}}, r{{[0-9]}})
+; CHECK: { p{{[0-3]}} = cmp.gtu(r{{[0-9]}},r{{[0-9]}})
; Function Attrs: nounwind readnone
declare i32 @llvm.hexagon.C2.cmpltu(i32, i32) #1
@@ -79,7 +79,7 @@ entry:
%1 = call i32 @llvm.hexagon.C2.cmpeqi(i32 %0, i32 10)
ret i32 %1
}
-; CHECK: { p{{[0-3]}} = cmp.eq(r{{[0-9]}}, {{.*}}#10)
+; CHECK: { p{{[0-3]}} = cmp.eq(r{{[0-9]}},#10)
; Function Attrs: nounwind readnone
declare i32 @llvm.hexagon.C2.cmpeqi(i32, i32) #1
@@ -93,7 +93,7 @@ entry:
%1 = call i32 @llvm.hexagon.C2.cmpgti(i32 %0, i32 20)
ret i32 %1
}
-; CHECK: { p{{[0-3]}} = cmp.gt(r{{[0-9]}}, {{.*}}#20)
+; CHECK: { p{{[0-3]}} = cmp.gt(r{{[0-9]}},#20)
; Function Attrs: nounwind readnone
declare i32 @llvm.hexagon.C2.cmpgti(i32, i32) #1
@@ -107,7 +107,7 @@ entry:
%1 = call i32 @llvm.hexagon.C2.cmpgtui(i32 %0, i32 40)
ret i32 %1
}
-; CHECK: { p{{[0-3]}} = cmp.gtu(r{{[0-9]}}, {{.*}}#40)
+; CHECK: { p{{[0-3]}} = cmp.gtu(r{{[0-9]}},#40)
; Function Attrs: nounwind readnone
declare i32 @llvm.hexagon.C2.cmpgtui(i32, i32) #1
@@ -121,7 +121,7 @@ entry:
%1 = call i32 @llvm.hexagon.C2.cmpgei(i32 %0, i32 3)
ret i32 %1
}
-; CHECK: { p{{[0-3]}} = cmp.gt(r{{[0-9]}}, {{.*}}#2)
+; CHECK: { p{{[0-3]}} = cmp.gt(r{{[0-9]}},#2)
; Function Attrs: nounwind readnone
declare i32 @llvm.hexagon.C2.cmpgei(i32, i32) #1
@@ -135,7 +135,7 @@ entry:
%1 = call i32 @llvm.hexagon.C2.cmpgeui(i32 %0, i32 3)
ret i32 %1
}
-; CHECK: { p{{[0-3]}} = cmp.gtu(r{{[0-9]}}, {{.*}}#2)
+; CHECK: { p{{[0-3]}} = cmp.gtu(r{{[0-9]}},#2)
; Function Attrs: nounwind readnone
declare i32 @llvm.hexagon.C2.cmpgeui(i32, i32) #1
@@ -149,7 +149,7 @@ entry:
%1 = call i32 @llvm.hexagon.C2.cmpgeui(i32 %0, i32 0)
ret i32 %1
}
-; CHECK: { p{{[0-3]}} = cmp.eq(r{{[0-9]}}, r{{[0-9]}})
+; CHECK: { p{{[0-3]}} = cmp.eq(r{{[0-9]}},r{{[0-9]}})
attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
Modified: llvm/trunk/test/CodeGen/Hexagon/combine.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/combine.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/combine.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/combine.ll Fri Feb 10 09:33:13 2017
@@ -1,5 +1,5 @@
; RUN: llc -march=hexagon -mcpu=hexagonv5 -disable-hsdr -hexagon-bit=0 < %s | FileCheck %s
-; CHECK: combine(r{{[0-9]+}}, r{{[0-9]+}})
+; CHECK: combine(r{{[0-9]+}},r{{[0-9]+}})
@j = external global i32
@k = external global i64
Modified: llvm/trunk/test/CodeGen/Hexagon/constp-combine-neg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/constp-combine-neg.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/constp-combine-neg.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/constp-combine-neg.ll Fri Feb 10 09:33:13 2017
@@ -19,9 +19,9 @@ entry:
; The instructions seem to be in a different order in the .s file than
; the corresponding values in the .ll file, so just run the test three
; times and each time test for a different instruction.
-; CHECK-TEST1: combine(#-2, #3)
-; CHECK-TEST2: combine(#6, #-4)
-; CHECK-TEST3: combine(#-10, #-8)
+; CHECK-TEST1: combine(#-2,#3)
+; CHECK-TEST2: combine(#6,#-4)
+; CHECK-TEST3: combine(#-10,#-8)
attributes #0 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
Modified: llvm/trunk/test/CodeGen/Hexagon/ctlz-cttz-ctpop.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/ctlz-cttz-ctpop.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/ctlz-cttz-ctpop.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/ctlz-cttz-ctpop.ll Fri Feb 10 09:33:13 2017
@@ -4,7 +4,7 @@
; CHECK-DAG: cl0({{r[0-9]*:[0-9]*}})
; CHECK-DAG: ct0({{r[0-9]*}})
; CHECK-DAG: cl0({{r[0-9]*}})
-; CHECK-DAG: r{{[0-9]+}} += lsr(r{{[0-9]+}}, #4)
+; CHECK-DAG: r{{[0-9]+}} += lsr(r{{[0-9]+}},#4)
define i32 @foo(i64 %a, i32 %b) nounwind {
entry:
Modified: llvm/trunk/test/CodeGen/Hexagon/dead-store-stack.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/dead-store-stack.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/dead-store-stack.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/dead-store-stack.ll Fri Feb 10 09:33:13 2017
@@ -1,6 +1,6 @@
; RUN: llc -O2 -march=hexagon < %s | FileCheck %s
; CHECK: ParseFunc:
-; CHECK: r[[ARG0:[0-9]+]] = memuh(r[[ARG1:[0-9]+]] + #[[OFFSET:[0-9]+]])
+; CHECK: r[[ARG0:[0-9]+]] = memuh(r[[ARG1:[0-9]+]]+#[[OFFSET:[0-9]+]])
; CHECK: memw(r[[ARG1]]+#[[OFFSET]]) = r[[ARG0]]
@.str.3 = external unnamed_addr constant [8 x i8], align 1
Modified: llvm/trunk/test/CodeGen/Hexagon/eh_return.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/eh_return.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/eh_return.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/eh_return.ll Fri Feb 10 09:33:13 2017
@@ -4,7 +4,7 @@
; CHECK: deallocframe
; CHECK-NEXT: }
; CHECK-NEXT: {
-; CHECK-NEXT: r29 = add(r29, r28)
+; CHECK-NEXT: r29 = add(r29,r28)
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: jumpr r31
Modified: llvm/trunk/test/CodeGen/Hexagon/extload-combine.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/extload-combine.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/extload-combine.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/extload-combine.ll Fri Feb 10 09:33:13 2017
@@ -15,8 +15,8 @@
; Function Attrs: nounwind
define i64 @short_test1() #0 {
-; CHECK: [[VAR:r[0-9]+]]{{ *}}={{ *}}memuh(##
-; CHECK: combine(#0, [[VAR]])
+; CHECK: [[VAR:r[0-9]+]] = memuh(##
+; CHECK: combine(#0,[[VAR]])
entry:
store i16 0, i16* @a, align 2
%0 = load i16, i16* @b, align 2
@@ -26,7 +26,7 @@ entry:
; Function Attrs: nounwind
define i64 @short_test2() #0 {
-; CHECK: [[VAR1:r[0-9]+]]{{ *}}={{ *}}memh(##
+; CHECK: [[VAR1:r[0-9]+]] = memh(##
; CHECK: sxtw([[VAR1]])
entry:
store i16 0, i16* @a, align 2
@@ -37,8 +37,8 @@ entry:
; Function Attrs: nounwind
define i64 @char_test1() #0 {
-; CHECK: [[VAR2:r[0-9]+]]{{ *}}={{ *}}memub(##
-; CHECK: combine(#0, [[VAR2]])
+; CHECK: [[VAR2:r[0-9]+]] = memub(##
+; CHECK: combine(#0,[[VAR2]])
entry:
store i8 0, i8* @char_a, align 1
%0 = load i8, i8* @char_b, align 1
@@ -48,7 +48,7 @@ entry:
; Function Attrs: nounwind
define i64 @char_test2() #0 {
-; CHECK: [[VAR3:r[0-9]+]]{{ *}}={{ *}}memb(##
+; CHECK: [[VAR3:r[0-9]+]] = memb(##
; CHECK: sxtw([[VAR3]])
entry:
store i8 0, i8* @char_a, align 1
@@ -59,8 +59,8 @@ entry:
; Function Attrs: nounwind
define i64 @int_test1() #0 {
-; CHECK: [[VAR4:r[0-9]+]]{{ *}}={{ *}}memw(##
-; CHECK: combine(#0, [[VAR4]])
+; CHECK: [[VAR4:r[0-9]+]] = memw(##
+; CHECK: combine(#0,[[VAR4]])
entry:
store i32 0, i32* @int_a, align 4
%0 = load i32, i32* @int_b, align 4
@@ -70,7 +70,7 @@ entry:
; Function Attrs: nounwind
define i64 @int_test2() #0 {
-; CHECK: [[VAR5:r[0-9]+]]{{ *}}={{ *}}memw(##
+; CHECK: [[VAR5:r[0-9]+]] = memw(##
; CHECK: sxtw([[VAR5]])
entry:
store i32 0, i32* @int_a, align 4
Modified: llvm/trunk/test/CodeGen/Hexagon/extract-basic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/extract-basic.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/extract-basic.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/extract-basic.ll Fri Feb 10 09:33:13 2017
@@ -1,8 +1,8 @@
; RUN: llc -O2 -march=hexagon < %s | FileCheck %s
-; CHECK-DAG: extractu(r{{[0-9]*}}, #3, #4)
-; CHECK-DAG: extractu(r{{[0-9]*}}, #8, #7)
-; CHECK-DAG: extractu(r{{[0-9]*}}, #8, #16)
+; CHECK-DAG: extractu(r{{[0-9]*}},#3,#4)
+; CHECK-DAG: extractu(r{{[0-9]*}},#8,#7)
+; CHECK-DAG: extractu(r{{[0-9]*}},#8,#16)
; C source:
; typedef struct {
Modified: llvm/trunk/test/CodeGen/Hexagon/fadd.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/fadd.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/fadd.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/fadd.ll Fri Feb 10 09:33:13 2017
@@ -1,7 +1,7 @@
; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
; Check that we generate sp floating point add in V5.
-; CHECK: r{{[0-9]+}} = sfadd(r{{[0-9]+}}, r{{[0-9]+}})
+; CHECK: r{{[0-9]+}} = sfadd(r{{[0-9]+}},r{{[0-9]+}})
define i32 @main() nounwind {
entry:
Modified: llvm/trunk/test/CodeGen/Hexagon/float-amode.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/float-amode.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/float-amode.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/float-amode.ll Fri Feb 10 09:33:13 2017
@@ -12,9 +12,9 @@
@a = common global float 0.000000e+00, align 4
; CHECK-LABEL: test1
-; CHECK: [[REG11:(r[0-9]+)]]{{ *}}={{ *}}memw(r{{[0-9]+}} + r{{[0-9]+}}<<#2)
+; CHECK: [[REG11:(r[0-9]+)]] = memw(r{{[0-9]+}}+r{{[0-9]+}}<<#2)
; CHECK: [[REG12:(r[0-9]+)]] += sfmpy({{.*}}[[REG11]]
-; CHECK: memw(r{{[0-9]+}} + r{{[0-9]+}}<<#2) = [[REG12]].new
+; CHECK: memw(r{{[0-9]+}}+r{{[0-9]+}}<<#2) = [[REG12]].new
; Function Attrs: norecurse nounwind
define void @test1(%struct.matrix_params* nocapture readonly %params, i32 %col1) {
@@ -35,7 +35,7 @@ entry:
}
; CHECK-LABEL: test2
-; CHECK: [[REG21:(r[0-9]+)]]{{ *}}={{ *}}memw(##globB+92)
+; CHECK: [[REG21:(r[0-9]+)]] = memw(##globB+92)
; CHECK: [[REG22:(r[0-9]+)]] = sfadd({{.*}}[[REG21]]
; CHECK: memw(##globA+84) = [[REG22]]
@@ -54,7 +54,7 @@ entry:
}
; CHECK-LABEL: test3
-; CHECK: [[REG31:(r[0-9]+)]]{{ *}}={{ *}}memw(gp+#b)
+; CHECK: [[REG31:(r[0-9]+)]] = memw(gp+#b)
; CHECK: [[REG32:(r[0-9]+)]] = sfadd({{.*}}[[REG31]]
; CHECK: memw(gp+#a) = [[REG32]]
@@ -73,9 +73,9 @@ entry:
}
; CHECK-LABEL: test4
-; CHECK: [[REG41:(r[0-9]+)]]{{ *}}={{ *}}memw(r0<<#2 + ##globB+52)
+; CHECK: [[REG41:(r[0-9]+)]] = memw(r0<<#2+##globB+52)
; CHECK: [[REG42:(r[0-9]+)]] = sfadd({{.*}}[[REG41]]
-; CHECK: memw(r0<<#2 + ##globA+60) = [[REG42]]
+; CHECK: memw(r0<<#2+##globA+60) = [[REG42]]
; Function Attrs: noinline norecurse nounwind
define void @test4(i32 %col1) {
entry:
Modified: llvm/trunk/test/CodeGen/Hexagon/fmul.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/fmul.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/fmul.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/fmul.ll Fri Feb 10 09:33:13 2017
@@ -1,7 +1,7 @@
; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
; Check that we generate single precision floating point multiply in V5.
-; CHECK: r{{[0-9]+}} = sfmpy(r{{[0-9]+}}, r{{[0-9]+}})
+; CHECK: r{{[0-9]+}} = sfmpy(r{{[0-9]+}},r{{[0-9]+}})
define i32 @main() nounwind {
Modified: llvm/trunk/test/CodeGen/Hexagon/fsel.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/fsel.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/fsel.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/fsel.ll Fri Feb 10 09:33:13 2017
@@ -1,7 +1,7 @@
; RUN: llc -march=hexagon -O0 < %s | FileCheck %s
; CHECK-LABEL: danny:
-; CHECK: mux(p0, r1, ##1065353216)
+; CHECK: mux(p0,r1,##1065353216)
define float @danny(i32 %x, float %f) #0 {
%t = icmp sgt i32 %x, 0
@@ -10,7 +10,7 @@ define float @danny(i32 %x, float %f) #0
}
; CHECK-LABEL: sammy:
-; CHECK: mux(p0, ##1069547520, r1)
+; CHECK: mux(p0,##1069547520,r1)
define float @sammy(i32 %x, float %f) #0 {
%t = icmp sgt i32 %x, 0
Modified: llvm/trunk/test/CodeGen/Hexagon/fsub.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/fsub.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/fsub.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/fsub.ll Fri Feb 10 09:33:13 2017
@@ -1,7 +1,7 @@
; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
; Check that we generate sp floating point subtract in V5.
-; CHECK: r{{[0-9]+}} = sfsub(r{{[0-9]+}}, r{{[0-9]+}})
+; CHECK: r{{[0-9]+}} = sfsub(r{{[0-9]+}},r{{[0-9]+}})
define i32 @main() nounwind {
entry:
Modified: llvm/trunk/test/CodeGen/Hexagon/fusedandshift.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/fusedandshift.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/fusedandshift.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/fusedandshift.ll Fri Feb 10 09:33:13 2017
@@ -2,7 +2,7 @@
; Check that we generate fused logical and with shift instruction.
; Disable "extract" generation, since it may eliminate the and/lsr.
-; CHECK: r{{[0-9]+}} = and(#15, lsr(r{{[0-9]+}}, #{{[0-9]+}})
+; CHECK: r{{[0-9]+}} = and(#15,lsr(r{{[0-9]+}},#{{[0-9]+}})
define i32 @main(i16* %a, i16* %b) nounwind {
entry:
Modified: llvm/trunk/test/CodeGen/Hexagon/hwloop-cleanup.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/hwloop-cleanup.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/hwloop-cleanup.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/hwloop-cleanup.ll Fri Feb 10 09:33:13 2017
@@ -5,7 +5,7 @@
; Bug 6685.
; CHECK: loop0
-; CHECK-NOT: r{{[0-9]+}}{{.}}={{.}}add(r{{[0-9]+}},{{.}}#-1)
+; CHECK-NOT: r{{[0-9]+}} = add(r{{[0-9]+}},#-1)
; CHECK-NOT: cmp.eq
; CHECK: endloop0
@@ -39,7 +39,7 @@ for.end:
; This test checks that that initial loop count value is removed.
; CHECK-NOT: ={{.}}#40
; CHECK: loop0
-; CHECK-NOT: r{{[0-9]+}}{{.}}={{.}}add(r{{[0-9]+}},{{.}}#-1)
+; CHECK-NOT: r{{[0-9]+}} = add(r{{[0-9]+}},#-1)
; CHECK-NOT: cmp.eq
; CHECK: endloop0
@@ -64,7 +64,7 @@ for.end:
; This test checks that we don't remove the induction variable since it's used.
; CHECK: loop0
-; CHECK: r{{[0-9]+}}{{.}}={{.}}add(r{{[0-9]+}},{{.}}#1)
+; CHECK: r{{[0-9]+}} = add(r{{[0-9]+}},#1)
; CHECK-NOT: cmp.eq
; CHECK: endloop0
define i32 @test3(i32* nocapture %b) nounwind {
Modified: llvm/trunk/test/CodeGen/Hexagon/hwloop-loop1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/hwloop-loop1.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/hwloop-loop1.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/hwloop-loop1.ll Fri Feb 10 09:33:13 2017
@@ -2,8 +2,8 @@
;
; Generate loop1 instruction for double loop sequence.
-; CHECK: loop1(.LBB{{.}}_{{.}}, #100)
-; CHECK: loop0(.LBB{{.}}_{{.}}, #100)
+; CHECK: loop1(.LBB{{.}}_{{.}},#100)
+; CHECK: loop0(.LBB{{.}}_{{.}},#100)
; CHECK: endloop0
; CHECK: endloop1
Modified: llvm/trunk/test/CodeGen/Hexagon/hwloop1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/hwloop1.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/hwloop1.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/hwloop1.ll Fri Feb 10 09:33:13 2017
@@ -3,7 +3,7 @@
; Case 1 : Loop with a constant number of iterations.
; CHECK-LABEL: @hwloop1
-; CHECK: loop0(.LBB{{.}}_{{.}}, #10)
+; CHECK: loop0(.LBB{{.}}_{{.}},#10)
; CHECK: endloop0
@a = common global [10 x i32] zeroinitializer, align 4
@@ -23,7 +23,7 @@ for.end:
; Case 2 : Loop with a run-time number of iterations.
; CHECK-LABEL: @hwloop2
-; CHECK: loop0(.LBB{{.}}_{{.}}, r{{[0-9]+}})
+; CHECK: loop0(.LBB{{.}}_{{.}},r{{[0-9]+}})
; CHECK: endloop0
define i32 @hwloop2(i32 %n, i32* nocapture %b) nounwind {
@@ -54,8 +54,8 @@ for.end:
; Case 3 : Induction variable increment more than 1.
; CHECK-LABEL: @hwloop3
-; CHECK: lsr(r{{[0-9]+}}, #2)
-; CHECK: loop0(.LBB{{.}}_{{.}}, r{{[0-9]+}})
+; CHECK: lsr(r{{[0-9]+}},#2)
+; CHECK: loop0(.LBB{{.}}_{{.}},r{{[0-9]+}})
; CHECK: endloop0
define i32 @hwloop3(i32 %n, i32* nocapture %b) nounwind {
@@ -86,7 +86,7 @@ for.end:
; Case 4 : Loop exit compare uses register instead of immediate value.
; CHECK-LABEL: @hwloop4
-; CHECK: loop0(.LBB{{.}}_{{.}}, r{{[0-9]+}})
+; CHECK: loop0(.LBB{{.}}_{{.}},r{{[0-9]+}})
; CHECK: endloop0
define i32 @hwloop4(i32 %n, i32* nocapture %b) nounwind {
@@ -114,7 +114,7 @@ for.end:
; Case 5: After LSR, the initial value is 100 and the iv decrements to 0.
; CHECK-LABEL: @hwloop5
-; CHECK: loop0(.LBB{{.}}_{{.}}, #100)
+; CHECK: loop0(.LBB{{.}}_{{.}},#100)
; CHECK: endloop0
define void @hwloop5(i32* nocapture %a, i32* nocapture %res) nounwind {
@@ -138,8 +138,8 @@ for.end:
; Case 6: Large immediate offset
; CHECK-LABEL: @hwloop6
-; CHECK-NOT: loop0(.LBB{{.}}_{{.}}, #1024)
-; CHECK: loop0(.LBB{{.}}_{{.}}, r{{[0-9]+}})
+; CHECK-NOT: loop0(.LBB{{.}}_{{.}},#1024)
+; CHECK: loop0(.LBB{{.}}_{{.}},r{{[0-9]+}})
; CHECK: endloop0
define void @hwloop6(i32* nocapture %a, i32* nocapture %res) nounwind {
Modified: llvm/trunk/test/CodeGen/Hexagon/hwloop2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/hwloop2.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/hwloop2.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/hwloop2.ll Fri Feb 10 09:33:13 2017
@@ -2,7 +2,7 @@
; Test for multiple phis with induction variables.
-; CHECK: loop0(.LBB{{.}}_{{.}}, r{{[0-9]+}})
+; CHECK: loop0(.LBB{{.}}_{{.}},r{{[0-9]+}})
; CHECK: endloop0
define i32 @hwloop4(i32* nocapture %s, i32* nocapture %a, i32 %n) {
Modified: llvm/trunk/test/CodeGen/Hexagon/hwloop4.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/hwloop4.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/hwloop4.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/hwloop4.ll Fri Feb 10 09:33:13 2017
@@ -2,9 +2,9 @@
;
; Remove the unnecessary 'add' instruction used for the hardware loop setup.
-; CHECK: [[OP0:r[0-9]+]] = add([[OP1:r[0-9]+]], #-[[OP2:[0-9]+]]
-; CHECK-NOT: add([[OP0]], #[[OP2]])
-; CHECK: lsr([[OP1]], #{{[0-9]+}})
+; CHECK: [[OP0:r[0-9]+]] = add([[OP1:r[0-9]+]],#-[[OP2:[0-9]+]]
+; CHECK-NOT: add([[OP0]],#[[OP2]])
+; CHECK: lsr([[OP1]],#{{[0-9]+}})
; CHECK: loop0
define void @matrix_mul_matrix(i32 %N, i32* nocapture %C, i16* nocapture readnone %A, i16* nocapture readnone %B) #0 {
Modified: llvm/trunk/test/CodeGen/Hexagon/hwloop5.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/hwloop5.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/hwloop5.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/hwloop5.ll Fri Feb 10 09:33:13 2017
@@ -2,9 +2,9 @@
;
; Generate hardware loop when unknown trip count loop is vectorized.
-; CHECK: loop0(.LBB{{[0-9]*}}_{{[0-9]*}}, r{{[0-9]+}})
+; CHECK: loop0(.LBB{{[0-9]*}}_{{[0-9]*}},r{{[0-9]+}})
; CHECK: endloop0
-; CHECK: loop0(.LBB{{[0-9]*}}_{{[0-9]*}}, r{{[0-9]+}})
+; CHECK: loop0(.LBB{{[0-9]*}}_{{[0-9]*}},r{{[0-9]+}})
; CHECK: endloop0
@A = common global [1000 x i32] zeroinitializer, align 8
Modified: llvm/trunk/test/CodeGen/Hexagon/ifcvt-diamond-bug-2016-08-26.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/ifcvt-diamond-bug-2016-08-26.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/ifcvt-diamond-bug-2016-08-26.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/ifcvt-diamond-bug-2016-08-26.ll Fri Feb 10 09:33:13 2017
@@ -15,7 +15,7 @@ entry:
br i1 %cmp199, label %if.then200, label %if.else201
; CHECK-DAG: [[R4:r[0-9]+]] = #4
-; CHECK: p0 = cmp.eq(r0, #0)
+; CHECK: p0 = cmp.eq(r0,#0)
; CHECK: if (!p0.new) [[R3:r[0-9]+]] = #3
; CHECK-DAG: if (!p0) memh(##t) = [[R3]]
; CHECK-DAG: if (p0) memh(##t) = [[R4]]
Modified: llvm/trunk/test/CodeGen/Hexagon/insert-basic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/insert-basic.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/insert-basic.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/insert-basic.ll Fri Feb 10 09:33:13 2017
@@ -1,8 +1,8 @@
; RUN: llc -O2 -march=hexagon < %s | FileCheck %s
-; CHECK-DAG: insert(r{{[0-9]*}}, #17, #0)
-; CHECK-DAG: insert(r{{[0-9]*}}, #18, #0)
-; CHECK-DAG: insert(r{{[0-9]*}}, #22, #0)
-; CHECK-DAG: insert(r{{[0-9]*}}, #12, #0)
+; CHECK-DAG: insert(r{{[0-9]*}},#17,#0)
+; CHECK-DAG: insert(r{{[0-9]*}},#18,#0)
+; CHECK-DAG: insert(r{{[0-9]*}},#22,#0)
+; CHECK-DAG: insert(r{{[0-9]*}},#12,#0)
; C source:
; typedef struct {
Modified: llvm/trunk/test/CodeGen/Hexagon/insert4.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/insert4.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/insert4.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/insert4.ll Fri Feb 10 09:33:13 2017
@@ -1,8 +1,8 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
;
; Check that we no longer generate 4 inserts.
-; CHECK: combine(r{{[0-9]+}}.l, r{{[0-9]+}}.l)
-; CHECK: combine(r{{[0-9]+}}.l, r{{[0-9]+}}.l)
+; CHECK: combine(r{{[0-9]+}}.l,r{{[0-9]+}}.l)
+; CHECK: combine(r{{[0-9]+}}.l,r{{[0-9]+}}.l)
; CHECK-NOT: insert
target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32"
Modified: llvm/trunk/test/CodeGen/Hexagon/intrinsics/alu32_alu.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/intrinsics/alu32_alu.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/intrinsics/alu32_alu.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/intrinsics/alu32_alu.ll Fri Feb 10 09:33:13 2017
@@ -10,21 +10,21 @@ define i32 @A2_addi(i32 %a) {
%z = call i32 @llvm.hexagon.A2.addi(i32 %a, i32 0)
ret i32 %z
}
-; CHECK: = add({{.*}}, #0)
+; CHECK: = add({{.*}},#0)
declare i32 @llvm.hexagon.A2.add(i32, i32)
define i32 @A2_add(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.A2.add(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = add({{.*}}, {{.*}})
+; CHECK: = add({{.*}},{{.*}})
declare i32 @llvm.hexagon.A2.addsat(i32, i32)
define i32 @A2_addsat(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.A2.addsat(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = add({{.*}}, {{.*}}):sat
+; CHECK: = add({{.*}},{{.*}}):sat
; Logical operations
declare i32 @llvm.hexagon.A2.and(i32, i32)
@@ -32,35 +32,35 @@ define i32 @A2_and(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.A2.and(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = and({{.*}}, {{.*}})
+; CHECK: = and({{.*}},{{.*}})
declare i32 @llvm.hexagon.A2.or(i32, i32)
define i32 @A2_or(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.A2.or(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = or({{.*}}, {{.*}})
+; CHECK: = or({{.*}},{{.*}})
declare i32 @llvm.hexagon.A2.xor(i32, i32)
define i32 @A2_xor(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.A2.xor(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = xor({{.*}}, {{.*}})
+; CHECK: = xor({{.*}},{{.*}})
declare i32 @llvm.hexagon.A4.andn(i32, i32)
define i32 @A4_andn(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.A4.andn(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = and({{.*}}, ~{{.*}})
+; CHECK: = and({{.*}},~{{.*}})
declare i32 @llvm.hexagon.A4.orn(i32, i32)
define i32 @A4_orn(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.A4.orn(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = or({{.*}}, ~{{.*}})
+; CHECK: = or({{.*}},~{{.*}})
; Subtract
declare i32 @llvm.hexagon.A2.sub(i32, i32)
@@ -68,14 +68,14 @@ define i32 @A2_sub(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.A2.sub(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = sub({{.*}}, {{.*}})
+; CHECK: = sub({{.*}},{{.*}})
declare i32 @llvm.hexagon.A2.subsat(i32, i32)
define i32 @A2_subsat(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.A2.subsat(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = sub({{.*}}, {{.*}}):sat
+; CHECK: = sub({{.*}},{{.*}}):sat
; Sign extend
declare i32 @llvm.hexagon.A2.sxtb(i32)
@@ -128,21 +128,21 @@ define i32 @A2_svaddh(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.A2.svaddh(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = vaddh({{.*}}, {{.*}})
+; CHECK: = vaddh({{.*}},{{.*}})
declare i32 @llvm.hexagon.A2.svaddhs(i32, i32)
define i32 @A2_svaddhs(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.A2.svaddhs(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = vaddh({{.*}}, {{.*}}):sat
+; CHECK: = vaddh({{.*}},{{.*}}):sat
declare i32 @llvm.hexagon.A2.svadduhs(i32, i32)
define i32 @A2_svadduhs(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.A2.svadduhs(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = vadduh({{.*}}, {{.*}}):sat
+; CHECK: = vadduh({{.*}},{{.*}}):sat
; Vector average halfwords
declare i32 @llvm.hexagon.A2.svavgh(i32, i32)
@@ -150,21 +150,21 @@ define i32 @A2_svavgh(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.A2.svavgh(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = vavgh({{.*}}, {{.*}})
+; CHECK: = vavgh({{.*}},{{.*}})
declare i32 @llvm.hexagon.A2.svavghs(i32, i32)
define i32 @A2_svavghs(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.A2.svavghs(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = vavgh({{.*}}, {{.*}}):rnd
+; CHECK: = vavgh({{.*}},{{.*}}):rnd
declare i32 @llvm.hexagon.A2.svnavgh(i32, i32)
define i32 @A2_svnavgh(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.A2.svnavgh(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = vnavgh({{.*}}, {{.*}})
+; CHECK: = vnavgh({{.*}},{{.*}})
; Vector subtract halfwords
declare i32 @llvm.hexagon.A2.svsubh(i32, i32)
@@ -172,21 +172,21 @@ define i32 @A2_svsubh(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.A2.svsubh(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = vsubh({{.*}}, {{.*}})
+; CHECK: = vsubh({{.*}},{{.*}})
declare i32 @llvm.hexagon.A2.svsubhs(i32, i32)
define i32 @A2_svsubhs(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.A2.svsubhs(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = vsubh({{.*}}, {{.*}}):sat
+; CHECK: = vsubh({{.*}},{{.*}}):sat
declare i32 @llvm.hexagon.A2.svsubuhs(i32, i32)
define i32 @A2_svsubuhs(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.A2.svsubuhs(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = vsubuh({{.*}}, {{.*}}):sat
+; CHECK: = vsubuh({{.*}},{{.*}}):sat
; Zero extend
declare i32 @llvm.hexagon.A2.zxth(i32)
Modified: llvm/trunk/test/CodeGen/Hexagon/intrinsics/alu32_perm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/intrinsics/alu32_perm.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/intrinsics/alu32_perm.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/intrinsics/alu32_perm.ll Fri Feb 10 09:33:13 2017
@@ -10,56 +10,56 @@ define i64 @A4_combineri(i32 %a) {
%z = call i64 @llvm.hexagon.A4.combineri(i32 %a, i32 0)
ret i64 %z
}
-; CHECK: = combine({{.*}}, #0)
+; CHECK: = combine({{.*}},#0)
declare i64 @llvm.hexagon.A4.combineir(i32, i32)
define i64 @A4_combineir(i32 %a) {
%z = call i64 @llvm.hexagon.A4.combineir(i32 0, i32 %a)
ret i64 %z
}
-; CHECK: = combine(#0, {{.*}})
+; CHECK: = combine(#0,{{.*}})
declare i64 @llvm.hexagon.A2.combineii(i32, i32)
define i64 @A2_combineii() {
%z = call i64 @llvm.hexagon.A2.combineii(i32 0, i32 0)
ret i64 %z
}
-; CHECK: = combine(#0, #0)
+; CHECK: = combine(#0,#0)
declare i32 @llvm.hexagon.A2.combine.hh(i32, i32)
define i32 @A2_combine_hh(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.A2.combine.hh(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = combine({{.*}}, {{.*}})
+; CHECK: = combine({{.*}},{{.*}})
declare i32 @llvm.hexagon.A2.combine.hl(i32, i32)
define i32 @A2_combine_hl(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.A2.combine.hl(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = combine({{.*}}, {{.*}})
+; CHECK: = combine({{.*}},{{.*}})
declare i32 @llvm.hexagon.A2.combine.lh(i32, i32)
define i32 @A2_combine_lh(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.A2.combine.lh(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = combine({{.*}}, {{.*}})
+; CHECK: = combine({{.*}},{{.*}})
declare i32 @llvm.hexagon.A2.combine.ll(i32, i32)
define i32 @A2_combine_ll(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.A2.combine.ll(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = combine({{.*}}, {{.*}})
+; CHECK: = combine({{.*}},{{.*}})
declare i64 @llvm.hexagon.A2.combinew(i32, i32)
define i64 @A2_combinew(i32 %a, i32 %b) {
%z = call i64 @llvm.hexagon.A2.combinew(i32 %a, i32 %b)
ret i64 %z
}
-; CHECK: = combine({{.*}}, {{.*}})
+; CHECK: = combine({{.*}},{{.*}})
; Mux
declare i32 @llvm.hexagon.C2.muxri(i32, i32, i32)
@@ -67,21 +67,21 @@ define i32 @C2_muxri(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.C2.muxri(i32 %a, i32 0, i32 %b)
ret i32 %z
}
-; CHECK: = mux({{.*}}, #0, {{.*}})
+; CHECK: = mux({{.*}},#0,{{.*}})
declare i32 @llvm.hexagon.C2.muxir(i32, i32, i32)
define i32 @C2_muxir(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.C2.muxir(i32 %a, i32 %b, i32 0)
ret i32 %z
}
-; CHECK: = mux({{.*}}, {{.*}}, #0)
+; CHECK: = mux({{.*}},{{.*}},#0)
declare i32 @llvm.hexagon.C2.mux(i32, i32, i32)
define i32 @C2_mux(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.C2.mux(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: = mux({{.*}}, {{.*}}, {{.*}})
+; CHECK: = mux({{.*}},{{.*}},{{.*}})
; Shift word by 16
declare i32 @llvm.hexagon.A2.aslh(i32)
@@ -104,4 +104,4 @@ define i64 @S2_packhl(i32 %a, i32 %b) {
%z = call i64 @llvm.hexagon.S2.packhl(i32 %a, i32 %b)
ret i64 %z
}
-; CHECK: = packhl({{.*}}, {{.*}})
+; CHECK: = packhl({{.*}},{{.*}})
Modified: llvm/trunk/test/CodeGen/Hexagon/intrinsics/cr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/intrinsics/cr.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/intrinsics/cr.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/intrinsics/cr.ll Fri Feb 10 09:33:13 2017
@@ -10,14 +10,14 @@ define i32 @C4_fastcorner9(i32 %a, i32 %
%z = call i32 at llvm.hexagon.C4.fastcorner9(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = fastcorner9({{.*}}, {{.*}})
+; CHECK: = fastcorner9({{.*}},{{.*}})
declare i32 @llvm.hexagon.C4.fastcorner9.not(i32, i32)
define i32 @C4_fastcorner9_not(i32 %a, i32 %b) {
%z = call i32 at llvm.hexagon.C4.fastcorner9.not(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = !fastcorner9({{.*}}, {{.*}})
+; CHECK: = !fastcorner9({{.*}},{{.*}})
; Logical reductions on predicates
declare i32 @llvm.hexagon.C2.any8(i32)
@@ -41,70 +41,70 @@ define i32 @C2_and(i32 %a, i32 %b) {
%z = call i32 at llvm.hexagon.C2.and(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = and({{.*}}, {{.*}})
+; CHECK: = and({{.*}},{{.*}})
declare i32 @llvm.hexagon.C4.and.and(i32, i32, i32)
define i32 @C4_and_and(i32 %a, i32 %b, i32 %c) {
%z = call i32 at llvm.hexagon.C4.and.and(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: = and({{.*}}, and({{.*}}, {{.*}}))
+; CHECK: = and({{.*}},and({{.*}},{{.*}}))
declare i32 @llvm.hexagon.C2.or(i32, i32)
define i32 @C2_or(i32 %a, i32 %b) {
%z = call i32 at llvm.hexagon.C2.or(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = or({{.*}}, {{.*}})
+; CHECK: = or({{.*}},{{.*}})
declare i32 @llvm.hexagon.C4.and.or(i32, i32, i32)
define i32 @C4_and_or(i32 %a, i32 %b, i32 %c) {
%z = call i32 at llvm.hexagon.C4.and.or(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: = and({{.*}}, or({{.*}}, {{.*}}))
+; CHECK: = and({{.*}},or({{.*}},{{.*}}))
declare i32 @llvm.hexagon.C2.xor(i32, i32)
define i32 @C2_xor(i32 %a, i32 %b) {
%z = call i32 at llvm.hexagon.C2.xor(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = xor({{.*}}, {{.*}})
+; CHECK: = xor({{.*}},{{.*}})
declare i32 @llvm.hexagon.C4.or.and(i32, i32, i32)
define i32 @C4_or_and(i32 %a, i32 %b, i32 %c) {
%z = call i32 at llvm.hexagon.C4.or.and(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: = or({{.*}}, and({{.*}}, {{.*}}))
+; CHECK: = or({{.*}},and({{.*}},{{.*}}))
declare i32 @llvm.hexagon.C2.andn(i32, i32)
define i32 @C2_andn(i32 %a, i32 %b) {
%z = call i32 at llvm.hexagon.C2.andn(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = and({{.*}}, !{{.*}})
+; CHECK: = and({{.*}},!{{.*}})
declare i32 @llvm.hexagon.C4.or.or(i32, i32, i32)
define i32 @C4_or_or(i32 %a, i32 %b, i32 %c) {
%z = call i32 at llvm.hexagon.C4.or.or(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: = or({{.*}}, or({{.*}}, {{.*}}))
+; CHECK: = or({{.*}},or({{.*}},{{.*}}))
declare i32 @llvm.hexagon.C4.and.andn(i32, i32, i32)
define i32 @C4_and_andn(i32 %a, i32 %b, i32 %c) {
%z = call i32 at llvm.hexagon.C4.and.andn(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: = and({{.*}}, and({{.*}}, !{{.*}}))
+; CHECK: = and({{.*}},and({{.*}},!{{.*}}))
declare i32 @llvm.hexagon.C4.and.orn(i32, i32, i32)
define i32 @C4_and_orn(i32 %a, i32 %b, i32 %c) {
%z = call i32 at llvm.hexagon.C4.and.orn(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: = and({{.*}}, or({{.*}}, !{{.*}}))
+; CHECK: = and({{.*}},or({{.*}},!{{.*}}))
declare i32 @llvm.hexagon.C2.not(i32)
define i32 @C2_not(i32 %a) {
@@ -118,18 +118,18 @@ define i32 @C4_or_andn(i32 %a, i32 %b, i
%z = call i32 at llvm.hexagon.C4.or.andn(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: = or({{.*}}, and({{.*}}, !{{.*}}))
+; CHECK: = or({{.*}},and({{.*}},!{{.*}}))
declare i32 @llvm.hexagon.C2.orn(i32, i32)
define i32 @C2_orn(i32 %a, i32 %b) {
%z = call i32 at llvm.hexagon.C2.orn(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = or({{.*}}, !{{.*}})
+; CHECK: = or({{.*}},!{{.*}})
declare i32 @llvm.hexagon.C4.or.orn(i32, i32, i32)
define i32 @C4_or_orn(i32 %a, i32 %b, i32 %c) {
%z = call i32 at llvm.hexagon.C4.or.orn(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: = or({{.*}}, or({{.*}}, !{{.*}}))
+; CHECK: = or({{.*}},or({{.*}},!{{.*}}))
Modified: llvm/trunk/test/CodeGen/Hexagon/intrinsics/system_user.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/intrinsics/system_user.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/intrinsics/system_user.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/intrinsics/system_user.ll Fri Feb 10 09:33:13 2017
@@ -10,4 +10,4 @@ define void @prefetch(i8* %a) {
call void @llvm.hexagon.prefetch(i8* %a)
ret void
}
-; CHECK: dcfetch({{.*}} + #0)
+; CHECK: dcfetch({{.*}}+#0)
Modified: llvm/trunk/test/CodeGen/Hexagon/intrinsics/xtype_alu.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/intrinsics/xtype_alu.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/intrinsics/xtype_alu.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/intrinsics/xtype_alu.ll Fri Feb 10 09:33:13 2017
@@ -34,42 +34,42 @@ define i32 @S4_addaddi(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.S4.addaddi(i32 %a, i32 %b, i32 0)
ret i32 %z
}
-; CHECK: = add({{.*}}, add({{.*}}, #0))
+; CHECK: = add({{.*}},add({{.*}},#0))
declare i32 @llvm.hexagon.S4.subaddi(i32, i32, i32)
define i32 @S4_subaddi(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.S4.subaddi(i32 %a, i32 0, i32 %b)
ret i32 %z
}
-; CHECK: = add({{.*}}, sub(#0, {{.*}}))
+; CHECK: = add({{.*}},sub(#0,{{.*}}))
declare i32 @llvm.hexagon.M2.accii(i32, i32, i32)
define i32 @M2_accii(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.M2.accii(i32 %a, i32 %b, i32 0)
ret i32 %z
}
-; CHECK: += add({{.*}}, #0)
+; CHECK: += add({{.*}},#0)
declare i32 @llvm.hexagon.M2.naccii(i32, i32, i32)
define i32 @M2_naccii(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.M2.naccii(i32 %a, i32 %b, i32 0)
ret i32 %z
}
-; CHECK: -= add({{.*}}, #0)
+; CHECK: -= add({{.*}},#0)
declare i32 @llvm.hexagon.M2.acci(i32, i32, i32)
define i32 @M2_acci(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M2.acci(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: += add({{.*}}, {{.*}})
+; CHECK: += add({{.*}},{{.*}})
declare i32 @llvm.hexagon.M2.nacci(i32, i32, i32)
define i32 @M2_nacci(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M2.nacci(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: -= add({{.*}}, {{.*}})
+; CHECK: -= add({{.*}},{{.*}})
; Add doublewords
declare i64 @llvm.hexagon.A2.addp(i64, i64)
@@ -77,14 +77,14 @@ define i64 @A2_addp(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.A2.addp(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = add({{.*}}, {{.*}})
+; CHECK: = add({{.*}},{{.*}})
declare i64 @llvm.hexagon.A2.addpsat(i64, i64)
define i64 @A2_addpsat(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.A2.addpsat(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = add({{.*}}, {{.*}}):sat
+; CHECK: = add({{.*}},{{.*}}):sat
; Add halfword
declare i32 @llvm.hexagon.A2.addh.l16.ll(i32, i32)
@@ -92,84 +92,84 @@ define i32 @A2_addh_l16_ll(i32 %a, i32 %
%z = call i32 @llvm.hexagon.A2.addh.l16.ll(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = add({{.*}}.l, {{.*}}.l)
+; CHECK: = add({{.*}}.l,{{.*}}.l)
declare i32 @llvm.hexagon.A2.addh.l16.hl(i32, i32)
define i32 @A2_addh_l16_hl(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.A2.addh.l16.hl(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = add({{.*}}.l, {{.*}}.h)
+; CHECK: = add({{.*}}.l,{{.*}}.h)
declare i32 @llvm.hexagon.A2.addh.l16.sat.ll(i32, i32)
define i32 @A2_addh_l16_sat.ll(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.A2.addh.l16.sat.ll(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = add({{.*}}.l, {{.*}}.l):sat
+; CHECK: = add({{.*}}.l,{{.*}}.l):sat
declare i32 @llvm.hexagon.A2.addh.l16.sat.hl(i32, i32)
define i32 @A2_addh_l16_sat.hl(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.A2.addh.l16.sat.hl(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = add({{.*}}.l, {{.*}}.h):sat
+; CHECK: = add({{.*}}.l,{{.*}}.h):sat
declare i32 @llvm.hexagon.A2.addh.h16.ll(i32, i32)
define i32 @A2_addh_h16_ll(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.A2.addh.h16.ll(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = add({{.*}}.l, {{.*}}.l):<<16
+; CHECK: = add({{.*}}.l,{{.*}}.l):<<16
declare i32 @llvm.hexagon.A2.addh.h16.lh(i32, i32)
define i32 @A2_addh_h16_lh(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.A2.addh.h16.lh(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = add({{.*}}.l, {{.*}}.h):<<16
+; CHECK: = add({{.*}}.l,{{.*}}.h):<<16
declare i32 @llvm.hexagon.A2.addh.h16.hl(i32, i32)
define i32 @A2_addh_h16_hl(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.A2.addh.h16.hl(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = add({{.*}}.h, {{.*}}.l):<<16
+; CHECK: = add({{.*}}.h,{{.*}}.l):<<16
declare i32 @llvm.hexagon.A2.addh.h16.hh(i32, i32)
define i32 @A2_addh_h16_hh(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.A2.addh.h16.hh(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = add({{.*}}.h, {{.*}}.h):<<16
+; CHECK: = add({{.*}}.h,{{.*}}.h):<<16
declare i32 @llvm.hexagon.A2.addh.h16.sat.ll(i32, i32)
define i32 @A2_addh_h16_sat_ll(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.A2.addh.h16.sat.ll(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = add({{.*}}.l, {{.*}}.l):sat:<<16
+; CHECK: = add({{.*}}.l,{{.*}}.l):sat:<<16
declare i32 @llvm.hexagon.A2.addh.h16.sat.lh(i32, i32)
define i32 @A2_addh_h16_sat_lh(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.A2.addh.h16.sat.lh(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = add({{.*}}.l, {{.*}}.h):sat:<<16
+; CHECK: = add({{.*}}.l,{{.*}}.h):sat:<<16
declare i32 @llvm.hexagon.A2.addh.h16.sat.hl(i32, i32)
define i32 @A2_addh_h16_sat_hl(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.A2.addh.h16.sat.hl(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = add({{.*}}.h, {{.*}}.l):sat:<<16
+; CHECK: = add({{.*}}.h,{{.*}}.l):sat:<<16
declare i32 @llvm.hexagon.A2.addh.h16.sat.hh(i32, i32)
define i32 @A2_addh_h16_sat_hh(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.A2.addh.h16.sat.hh(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = add({{.*}}.h, {{.*}}.h):sat:<<16
+; CHECK: = add({{.*}}.h,{{.*}}.h):sat:<<16
; Logical doublewords
declare i64 @llvm.hexagon.A2.notp(i64)
@@ -184,35 +184,35 @@ define i64 @A2_andp(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.A2.andp(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = and({{.*}}, {{.*}})
+; CHECK: = and({{.*}},{{.*}})
declare i64 @llvm.hexagon.A4.andnp(i64, i64)
define i64 @A2_andnp(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.A4.andnp(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = and({{.*}}, ~{{.*}})
+; CHECK: = and({{.*}},~{{.*}})
declare i64 @llvm.hexagon.A2.orp(i64, i64)
define i64 @A2_orp(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.A2.orp(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = or({{.*}}, {{.*}})
+; CHECK: = or({{.*}},{{.*}})
declare i64 @llvm.hexagon.A4.ornp(i64, i64)
define i64 @A2_ornp(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.A4.ornp(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = or({{.*}}, ~{{.*}})
+; CHECK: = or({{.*}},~{{.*}})
declare i64 @llvm.hexagon.A2.xorp(i64, i64)
define i64 @A2_xorp(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.A2.xorp(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = xor({{.*}}, {{.*}})
+; CHECK: = xor({{.*}},{{.*}})
; Logical-logical doublewords
declare i64 @llvm.hexagon.M4.xor.xacc(i64, i64, i64)
@@ -220,7 +220,7 @@ define i64 @M4_xor_xacc(i64 %a, i64 %b,
%z = call i64 @llvm.hexagon.M4.xor.xacc(i64 %a, i64 %b, i64 %c)
ret i64 %z
}
-; CHECK: ^= xor({{.*}}, {{.*}})
+; CHECK: ^= xor({{.*}},{{.*}})
; Logical-logical words
declare i32 @llvm.hexagon.S4.or.andi(i32, i32, i32)
@@ -228,91 +228,91 @@ define i32 @S4_or_andi(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.S4.or.andi(i32 %a, i32 %b, i32 0)
ret i32 %z
}
-; CHECK: |= and({{.*}}, #0)
+; CHECK: |= and({{.*}},#0)
declare i32 @llvm.hexagon.S4.or.andix(i32, i32, i32)
define i32 @S4_or_andix(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.S4.or.andix(i32 %a, i32 %b, i32 0)
ret i32 %z
}
-; CHECK: = or({{.*}}, and({{.*}}, #0))
+; CHECK: = or({{.*}},and({{.*}},#0))
declare i32 @llvm.hexagon.M4.or.andn(i32, i32, i32)
define i32 @M4_or_andn(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M4.or.andn(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: |= and({{.*}}, ~{{.*}})
+; CHECK: |= and({{.*}},~{{.*}})
declare i32 @llvm.hexagon.M4.and.andn(i32, i32, i32)
define i32 @M4_and_andn(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M4.and.andn(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: &= and({{.*}}, ~{{.*}})
+; CHECK: &= and({{.*}},~{{.*}})
declare i32 @llvm.hexagon.M4.xor.andn(i32, i32, i32)
define i32 @M4_xor_andn(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M4.xor.andn(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: ^= and({{.*}}, ~{{.*}})
+; CHECK: ^= and({{.*}},~{{.*}})
declare i32 @llvm.hexagon.M4.and.and(i32, i32, i32)
define i32 @M4_and_and(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M4.and.and(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: &= and({{.*}}, {{.*}})
+; CHECK: &= and({{.*}},{{.*}})
declare i32 @llvm.hexagon.M4.and.or(i32, i32, i32)
define i32 @M4_and_or(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M4.and.or(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: &= or({{.*}}, {{.*}})
+; CHECK: &= or({{.*}},{{.*}})
declare i32 @llvm.hexagon.M4.and.xor(i32, i32, i32)
define i32 @M4_and_xor(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M4.and.xor(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: &= xor({{.*}}, {{.*}})
+; CHECK: &= xor({{.*}},{{.*}})
declare i32 @llvm.hexagon.M4.or.and(i32, i32, i32)
define i32 @M4_or_and(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M4.or.and(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: |= and({{.*}}, {{.*}})
+; CHECK: |= and({{.*}},{{.*}})
declare i32 @llvm.hexagon.M4.or.or(i32, i32, i32)
define i32 @M4_or_or(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M4.or.or(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: |= or({{.*}}, {{.*}})
+; CHECK: |= or({{.*}},{{.*}})
declare i32 @llvm.hexagon.M4.or.xor(i32, i32, i32)
define i32 @M4_or_xor(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M4.or.xor(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: |= xor({{.*}}, {{.*}})
+; CHECK: |= xor({{.*}},{{.*}})
declare i32 @llvm.hexagon.M4.xor.and(i32, i32, i32)
define i32 @M4_xor_and(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M4.xor.and(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: ^= and({{.*}}, {{.*}})
+; CHECK: ^= and({{.*}},{{.*}})
declare i32 @llvm.hexagon.M4.xor.or(i32, i32, i32)
define i32 @M4_xor_or(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M4.xor.or(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: ^= or({{.*}}, {{.*}})
+; CHECK: ^= or({{.*}},{{.*}})
; Maximum words
declare i32 @llvm.hexagon.A2.max(i32, i32)
@@ -320,14 +320,14 @@ define i32 @A2_max(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.A2.max(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = max({{.*}}, {{.*}})
+; CHECK: = max({{.*}},{{.*}})
declare i32 @llvm.hexagon.A2.maxu(i32, i32)
define i32 @A2_maxu(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.A2.maxu(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = maxu({{.*}}, {{.*}})
+; CHECK: = maxu({{.*}},{{.*}})
; Maximum doublewords
declare i64 @llvm.hexagon.A2.maxp(i64, i64)
@@ -335,14 +335,14 @@ define i64 @A2_maxp(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.A2.maxp(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = max({{.*}}, {{.*}})
+; CHECK: = max({{.*}},{{.*}})
declare i64 @llvm.hexagon.A2.maxup(i64, i64)
define i64 @A2_maxup(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.A2.maxup(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = maxu({{.*}}, {{.*}})
+; CHECK: = maxu({{.*}},{{.*}})
; Minimum words
declare i32 @llvm.hexagon.A2.min(i32, i32)
@@ -350,14 +350,14 @@ define i32 @A2_min(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.A2.min(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = min({{.*}}, {{.*}})
+; CHECK: = min({{.*}},{{.*}})
declare i32 @llvm.hexagon.A2.minu(i32, i32)
define i32 @A2_minu(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.A2.minu(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = minu({{.*}}, {{.*}})
+; CHECK: = minu({{.*}},{{.*}})
; Minimum doublewords
declare i64 @llvm.hexagon.A2.minp(i64, i64)
@@ -365,14 +365,14 @@ define i64 @A2_minp(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.A2.minp(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = min({{.*}}, {{.*}})
+; CHECK: = min({{.*}},{{.*}})
declare i64 @llvm.hexagon.A2.minup(i64, i64)
define i64 @A2_minup(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.A2.minup(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = minu({{.*}}, {{.*}})
+; CHECK: = minu({{.*}},{{.*}})
; Module wrap
declare i32 @llvm.hexagon.A4.modwrapu(i32, i32)
@@ -380,7 +380,7 @@ define i32 @A4_modwrapu(i32 %a, i32 %b)
%z = call i32 @llvm.hexagon.A4.modwrapu(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = modwrap({{.*}}, {{.*}})
+; CHECK: = modwrap({{.*}},{{.*}})
; Negate
declare i64 @llvm.hexagon.A2.negp(i64)
@@ -410,42 +410,42 @@ define i32 @A4_cround_ri(i32 %a) {
%z = call i32 @llvm.hexagon.A4.cround.ri(i32 %a, i32 0)
ret i32 %z
}
-; CHECK: = cround({{.*}}, #0)
+; CHECK: = cround({{.*}},#0)
declare i32 @llvm.hexagon.A4.round.ri(i32, i32)
define i32 @A4_round_ri(i32 %a) {
%z = call i32 @llvm.hexagon.A4.round.ri(i32 %a, i32 0)
ret i32 %z
}
-; CHECK: = round({{.*}}, #0)
+; CHECK: = round({{.*}},#0)
declare i32 @llvm.hexagon.A4.round.ri.sat(i32, i32)
define i32 @A4_round_ri_sat(i32 %a) {
%z = call i32 @llvm.hexagon.A4.round.ri.sat(i32 %a, i32 0)
ret i32 %z
}
-; CHECK: = round({{.*}}, #0):sat
+; CHECK: = round({{.*}},#0):sat
declare i32 @llvm.hexagon.A4.cround.rr(i32, i32)
define i32 @A4_cround_rr(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.A4.cround.rr(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = cround({{.*}}, {{.*}})
+; CHECK: = cround({{.*}},{{.*}})
declare i32 @llvm.hexagon.A4.round.rr(i32, i32)
define i32 @A4_round_rr(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.A4.round.rr(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = round({{.*}}, {{.*}})
+; CHECK: = round({{.*}},{{.*}})
declare i32 @llvm.hexagon.A4.round.rr.sat(i32, i32)
define i32 @A4_round_rr_sat(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.A4.round.rr.sat(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = round({{.*}}, {{.*}}):sat
+; CHECK: = round({{.*}},{{.*}}):sat
; Subtract doublewords
declare i64 @llvm.hexagon.A2.subp(i64, i64)
@@ -453,7 +453,7 @@ define i64 @A2_subp(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.A2.subp(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = sub({{.*}}, {{.*}})
+; CHECK: = sub({{.*}},{{.*}})
; Subtract and accumulate
declare i32 @llvm.hexagon.M2.subacc(i32, i32, i32)
@@ -461,7 +461,7 @@ define i32 @M2_subacc(i32 %a, i32 %b, i3
%z = call i32 @llvm.hexagon.M2.subacc(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: += sub({{.*}}, {{.*}})
+; CHECK: += sub({{.*}},{{.*}})
; Subtract halfwords
declare i32 @llvm.hexagon.A2.subh.l16.ll(i32, i32)
@@ -469,84 +469,84 @@ define i32 @A2_subh_l16_ll(i32 %a, i32 %
%z = call i32 @llvm.hexagon.A2.subh.l16.ll(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = sub({{.*}}.l, {{.*}}.l)
+; CHECK: = sub({{.*}}.l,{{.*}}.l)
declare i32 @llvm.hexagon.A2.subh.l16.hl(i32, i32)
define i32 @A2_subh_l16_hl(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.A2.subh.l16.hl(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = sub({{.*}}.l, {{.*}}.h)
+; CHECK: = sub({{.*}}.l,{{.*}}.h)
declare i32 @llvm.hexagon.A2.subh.l16.sat.ll(i32, i32)
define i32 @A2_subh_l16_sat.ll(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.A2.subh.l16.sat.ll(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = sub({{.*}}.l, {{.*}}.l):sat
+; CHECK: = sub({{.*}}.l,{{.*}}.l):sat
declare i32 @llvm.hexagon.A2.subh.l16.sat.hl(i32, i32)
define i32 @A2_subh_l16_sat.hl(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.A2.subh.l16.sat.hl(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = sub({{.*}}.l, {{.*}}.h):sat
+; CHECK: = sub({{.*}}.l,{{.*}}.h):sat
declare i32 @llvm.hexagon.A2.subh.h16.ll(i32, i32)
define i32 @A2_subh_h16_ll(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.A2.subh.h16.ll(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = sub({{.*}}.l, {{.*}}.l):<<16
+; CHECK: = sub({{.*}}.l,{{.*}}.l):<<16
declare i32 @llvm.hexagon.A2.subh.h16.lh(i32, i32)
define i32 @A2_subh_h16_lh(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.A2.subh.h16.lh(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = sub({{.*}}.l, {{.*}}.h):<<16
+; CHECK: = sub({{.*}}.l,{{.*}}.h):<<16
declare i32 @llvm.hexagon.A2.subh.h16.hl(i32, i32)
define i32 @A2_subh_h16_hl(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.A2.subh.h16.hl(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = sub({{.*}}.h, {{.*}}.l):<<16
+; CHECK: = sub({{.*}}.h,{{.*}}.l):<<16
declare i32 @llvm.hexagon.A2.subh.h16.hh(i32, i32)
define i32 @A2_subh_h16_hh(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.A2.subh.h16.hh(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = sub({{.*}}.h, {{.*}}.h):<<16
+; CHECK: = sub({{.*}}.h,{{.*}}.h):<<16
declare i32 @llvm.hexagon.A2.subh.h16.sat.ll(i32, i32)
define i32 @A2_subh_h16_sat_ll(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.A2.subh.h16.sat.ll(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = sub({{.*}}.l, {{.*}}.l):sat:<<16
+; CHECK: = sub({{.*}}.l,{{.*}}.l):sat:<<16
declare i32 @llvm.hexagon.A2.subh.h16.sat.lh(i32, i32)
define i32 @A2_subh_h16_sat_lh(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.A2.subh.h16.sat.lh(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = sub({{.*}}.l, {{.*}}.h):sat:<<16
+; CHECK: = sub({{.*}}.l,{{.*}}.h):sat:<<16
declare i32 @llvm.hexagon.A2.subh.h16.sat.hl(i32, i32)
define i32 @A2_subh_h16_sat_hl(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.A2.subh.h16.sat.hl(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = sub({{.*}}.h, {{.*}}.l):sat:<<16
+; CHECK: = sub({{.*}}.h,{{.*}}.l):sat:<<16
declare i32 @llvm.hexagon.A2.subh.h16.sat.hh(i32, i32)
define i32 @A2_subh_h16_sat_hh(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.A2.subh.h16.sat.hh(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = sub({{.*}}.h, {{.*}}.h):sat:<<16
+; CHECK: = sub({{.*}}.h,{{.*}}.h):sat:<<16
; Sign extend word to doubleword
declare i64 @llvm.hexagon.A2.sxtw(i32)
@@ -592,7 +592,7 @@ define i64 @M2_vabsdiffh(i64 %a, i64 %b)
%z = call i64 @llvm.hexagon.M2.vabsdiffh(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vabsdiffh({{.*}}, {{.*}})
+; CHECK: = vabsdiffh({{.*}},{{.*}})
; Vector absolute difference words
declare i64 @llvm.hexagon.M2.vabsdiffw(i64, i64)
@@ -600,7 +600,7 @@ define i64 @M2_vabsdiffw(i64 %a, i64 %b)
%z = call i64 @llvm.hexagon.M2.vabsdiffw(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vabsdiffw({{.*}}, {{.*}})
+; CHECK: = vabsdiffw({{.*}},{{.*}})
; Vector add halfwords
declare i64 @llvm.hexagon.A2.vaddh(i64, i64)
@@ -608,21 +608,21 @@ define i64 @A2_vaddh(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.A2.vaddh(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vaddh({{.*}}, {{.*}})
+; CHECK: = vaddh({{.*}},{{.*}})
declare i64 @llvm.hexagon.A2.vaddhs(i64, i64)
define i64 @A2_vaddhs(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.A2.vaddhs(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vaddh({{.*}}, {{.*}}):sat
+; CHECK: = vaddh({{.*}},{{.*}}):sat
declare i64 @llvm.hexagon.A2.vadduhs(i64, i64)
define i64 @A2_vadduhs(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.A2.vadduhs(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vadduh({{.*}}, {{.*}}):sat
+; CHECK: = vadduh({{.*}},{{.*}}):sat
; Vector add halfwords with saturate and pack to unsigned bytes
declare i32 @llvm.hexagon.A5.vaddhubs(i64, i64)
@@ -630,7 +630,7 @@ define i32 @A5_vaddhubs(i64 %a, i64 %b)
%z = call i32 @llvm.hexagon.A5.vaddhubs(i64 %a, i64 %b)
ret i32 %z
}
-; CHECK: = vaddhub({{.*}}, {{.*}}):sat
+; CHECK: = vaddhub({{.*}},{{.*}}):sat
; Vector reduce add unsigned bytes
declare i64 @llvm.hexagon.A2.vraddub(i64, i64)
@@ -638,14 +638,14 @@ define i64 @A2_vraddub(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.A2.vraddub(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vraddub({{.*}}, {{.*}})
+; CHECK: = vraddub({{.*}},{{.*}})
declare i64 @llvm.hexagon.A2.vraddub.acc(i64, i64, i64)
define i64 @A2_vraddub_acc(i64 %a, i64 %b, i64 %c) {
%z = call i64 @llvm.hexagon.A2.vraddub.acc(i64 %a, i64 %b, i64 %c)
ret i64 %z
}
-; CHECK: += vraddub({{.*}}, {{.*}})
+; CHECK: += vraddub({{.*}},{{.*}})
; Vector reduce add halfwords
declare i32 @llvm.hexagon.M2.vradduh(i64, i64)
@@ -653,14 +653,14 @@ define i32 @M2_vradduh(i64 %a, i64 %b) {
%z = call i32 @llvm.hexagon.M2.vradduh(i64 %a, i64 %b)
ret i32 %z
}
-; CHECK: = vradduh({{.*}}, {{.*}})
+; CHECK: = vradduh({{.*}},{{.*}})
declare i32 @llvm.hexagon.M2.vraddh(i64, i64)
define i32 @M2_vraddh(i64 %a, i64 %b) {
%z = call i32 @llvm.hexagon.M2.vraddh(i64 %a, i64 %b)
ret i32 %z
}
-; CHECK: = vraddh({{.*}}, {{.*}})
+; CHECK: = vraddh({{.*}},{{.*}})
; Vector add bytes
declare i64 @llvm.hexagon.A2.vaddub(i64, i64)
@@ -668,14 +668,14 @@ define i64 @A2_vaddub(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.A2.vaddub(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vaddub({{.*}}, {{.*}})
+; CHECK: = vaddub({{.*}},{{.*}})
declare i64 @llvm.hexagon.A2.vaddubs(i64, i64)
define i64 @A2_vaddubs(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.A2.vaddubs(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vaddub({{.*}}, {{.*}}):sat
+; CHECK: = vaddub({{.*}},{{.*}}):sat
; Vector add words
declare i64 @llvm.hexagon.A2.vaddw(i64, i64)
@@ -683,14 +683,14 @@ define i64 @A2_vaddw(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.A2.vaddw(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vaddw({{.*}}, {{.*}})
+; CHECK: = vaddw({{.*}},{{.*}})
declare i64 @llvm.hexagon.A2.vaddws(i64, i64)
define i64 @A2_vaddws(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.A2.vaddws(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vaddw({{.*}}, {{.*}}):sat
+; CHECK: = vaddw({{.*}},{{.*}}):sat
; Vector average halfwords
declare i64 @llvm.hexagon.A2.vavgh(i64, i64)
@@ -698,56 +698,56 @@ define i64 @A2_vavgh(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.A2.vavgh(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vavgh({{.*}}, {{.*}})
+; CHECK: = vavgh({{.*}},{{.*}})
declare i64 @llvm.hexagon.A2.vavghr(i64, i64)
define i64 @A2_vavghr(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.A2.vavghr(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vavgh({{.*}}, {{.*}}):rnd
+; CHECK: = vavgh({{.*}},{{.*}}):rnd
declare i64 @llvm.hexagon.A2.vavghcr(i64, i64)
define i64 @A2_vavghcr(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.A2.vavghcr(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vavgh({{.*}}, {{.*}}):crnd
+; CHECK: = vavgh({{.*}},{{.*}}):crnd
declare i64 @llvm.hexagon.A2.vavguh(i64, i64)
define i64 @A2_vavguh(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.A2.vavguh(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vavguh({{.*}}, {{.*}})
+; CHECK: = vavguh({{.*}},{{.*}})
declare i64 @llvm.hexagon.A2.vavguhr(i64, i64)
define i64 @A2_vavguhr(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.A2.vavguhr(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vavguh({{.*}}, {{.*}}):rnd
+; CHECK: = vavguh({{.*}},{{.*}}):rnd
declare i64 @llvm.hexagon.A2.vnavgh(i64, i64)
define i64 @A2_vnavgh(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.A2.vnavgh(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vnavgh({{.*}}, {{.*}})
+; CHECK: = vnavgh({{.*}},{{.*}})
declare i64 @llvm.hexagon.A2.vnavghr(i64, i64)
define i64 @A2_vnavghr(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.A2.vnavghr(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vnavgh({{.*}}, {{.*}}):rnd
+; CHECK: = vnavgh({{.*}},{{.*}}):rnd
declare i64 @llvm.hexagon.A2.vnavghcr(i64, i64)
define i64 @A2_vnavghcr(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.A2.vnavghcr(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vnavgh({{.*}}, {{.*}}):crnd
+; CHECK: = vnavgh({{.*}},{{.*}}):crnd
; Vector average unsigned bytes
declare i64 @llvm.hexagon.A2.vavgub(i64, i64)
@@ -755,14 +755,14 @@ define i64 @A2_vavgub(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.A2.vavgub(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: vavgub({{.*}}, {{.*}})
+; CHECK: vavgub({{.*}},{{.*}})
declare i64 @llvm.hexagon.A2.vavgubr(i64, i64)
define i64 @A2_vavgubr(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.A2.vavgubr(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vavgub({{.*}}, {{.*}}):rnd
+; CHECK: = vavgub({{.*}},{{.*}}):rnd
; Vector average words
declare i64 @llvm.hexagon.A2.vavgw(i64, i64)
@@ -770,56 +770,56 @@ define i64 @A2_vavgw(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.A2.vavgw(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vavgw({{.*}}, {{.*}})
+; CHECK: = vavgw({{.*}},{{.*}})
declare i64 @llvm.hexagon.A2.vavgwr(i64, i64)
define i64 @A2_vavgwr(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.A2.vavgwr(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vavgw({{.*}}, {{.*}}):rnd
+; CHECK: = vavgw({{.*}},{{.*}}):rnd
declare i64 @llvm.hexagon.A2.vavgwcr(i64, i64)
define i64 @A2_vavgwcr(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.A2.vavgwcr(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vavgw({{.*}}, {{.*}}):crnd
+; CHECK: = vavgw({{.*}},{{.*}}):crnd
declare i64 @llvm.hexagon.A2.vavguw(i64, i64)
define i64 @A2_vavguw(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.A2.vavguw(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vavguw({{.*}}, {{.*}})
+; CHECK: = vavguw({{.*}},{{.*}})
declare i64 @llvm.hexagon.A2.vavguwr(i64, i64)
define i64 @A2_vavguwr(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.A2.vavguwr(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vavguw({{.*}}, {{.*}}):rnd
+; CHECK: = vavguw({{.*}},{{.*}}):rnd
declare i64 @llvm.hexagon.A2.vnavgw(i64, i64)
define i64 @A2_vnavgw(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.A2.vnavgw(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vnavgw({{.*}}, {{.*}})
+; CHECK: = vnavgw({{.*}},{{.*}})
declare i64 @llvm.hexagon.A2.vnavgwr(i64, i64)
define i64 @A2_vnavgwr(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.A2.vnavgwr(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vnavgw({{.*}}, {{.*}}):rnd
+; CHECK: = vnavgw({{.*}},{{.*}}):rnd
declare i64 @llvm.hexagon.A2.vnavgwcr(i64, i64)
define i64 @A2_vnavgwcr(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.A2.vnavgwcr(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vnavgw({{.*}}, {{.*}}):crnd
+; CHECK: = vnavgw({{.*}},{{.*}}):crnd
; Vector conditional negate
declare i64 @llvm.hexagon.S2.vcnegh(i64, i32)
@@ -827,14 +827,14 @@ define i64 @S2_vcnegh(i64 %a, i32 %b) {
%z = call i64 @llvm.hexagon.S2.vcnegh(i64 %a, i32 %b)
ret i64 %z
}
-; CHECK: = vcnegh({{.*}}, {{.*}})
+; CHECK: = vcnegh({{.*}},{{.*}})
declare i64 @llvm.hexagon.S2.vrcnegh(i64, i64, i32)
define i64 @S2_vrcnegh(i64 %a, i64 %b, i32 %c) {
%z = call i64 @llvm.hexagon.S2.vrcnegh(i64 %a, i64 %b, i32 %c)
ret i64 %z
}
-; CHECK: += vrcnegh({{.*}}, {{.*}})
+; CHECK: += vrcnegh({{.*}},{{.*}})
; Vector maximum bytes
declare i64 @llvm.hexagon.A2.vmaxub(i64, i64)
@@ -842,14 +842,14 @@ define i64 @A2_vmaxub(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.A2.vmaxub(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vmaxub({{.*}}, {{.*}})
+; CHECK: = vmaxub({{.*}},{{.*}})
declare i64 @llvm.hexagon.A2.vmaxb(i64, i64)
define i64 @A2_vmaxb(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.A2.vmaxb(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vmaxb({{.*}}, {{.*}})
+; CHECK: = vmaxb({{.*}},{{.*}})
; Vector maximum halfwords
declare i64 @llvm.hexagon.A2.vmaxh(i64, i64)
@@ -857,14 +857,14 @@ define i64 @A2_vmaxh(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.A2.vmaxh(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vmaxh({{.*}}, {{.*}})
+; CHECK: = vmaxh({{.*}},{{.*}})
declare i64 @llvm.hexagon.A2.vmaxuh(i64, i64)
define i64 @A2_vmaxuh(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.A2.vmaxuh(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vmaxuh({{.*}}, {{.*}})
+; CHECK: = vmaxuh({{.*}},{{.*}})
; Vector reduce maximum halfwords
declare i64 @llvm.hexagon.A4.vrmaxh(i64, i64, i32)
@@ -872,14 +872,14 @@ define i64 @A4_vrmaxh(i64 %a, i64 %b, i3
%z = call i64 @llvm.hexagon.A4.vrmaxh(i64 %a, i64 %b, i32 %c)
ret i64 %z
}
-; CHECK: = vrmaxh({{.*}}, {{.*}})
+; CHECK: = vrmaxh({{.*}},{{.*}})
declare i64 @llvm.hexagon.A4.vrmaxuh(i64, i64, i32)
define i64 @A4_vrmaxuh(i64 %a, i64 %b, i32 %c) {
%z = call i64 @llvm.hexagon.A4.vrmaxuh(i64 %a, i64 %b, i32 %c)
ret i64 %z
}
-; CHECK: = vrmaxuh({{.*}}, {{.*}})
+; CHECK: = vrmaxuh({{.*}},{{.*}})
; Vector reduce maximum words
declare i64 @llvm.hexagon.A4.vrmaxw(i64, i64, i32)
@@ -887,14 +887,14 @@ define i64 @A4_vrmaxw(i64 %a, i64 %b, i3
%z = call i64 @llvm.hexagon.A4.vrmaxw(i64 %a, i64 %b, i32 %c)
ret i64 %z
}
-; CHECK: = vrmaxw({{.*}}, {{.*}})
+; CHECK: = vrmaxw({{.*}},{{.*}})
declare i64 @llvm.hexagon.A4.vrmaxuw(i64, i64, i32)
define i64 @A4_vrmaxuw(i64 %a, i64 %b, i32 %c) {
%z = call i64 @llvm.hexagon.A4.vrmaxuw(i64 %a, i64 %b, i32 %c)
ret i64 %z
}
-; CHECK: vrmaxuw({{.*}}, {{.*}})
+; CHECK: vrmaxuw({{.*}},{{.*}})
; Vector minimum bytes
declare i64 @llvm.hexagon.A2.vminub(i64, i64)
@@ -902,14 +902,14 @@ define i64 @A2_vminub(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.A2.vminub(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vminub({{.*}}, {{.*}})
+; CHECK: = vminub({{.*}},{{.*}})
declare i64 @llvm.hexagon.A2.vminb(i64, i64)
define i64 @A2_vminb(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.A2.vminb(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vminb({{.*}}, {{.*}})
+; CHECK: = vminb({{.*}},{{.*}})
; Vector minimum halfwords
declare i64 @llvm.hexagon.A2.vminh(i64, i64)
@@ -917,14 +917,14 @@ define i64 @A2_vminh(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.A2.vminh(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vminh({{.*}}, {{.*}})
+; CHECK: = vminh({{.*}},{{.*}})
declare i64 @llvm.hexagon.A2.vminuh(i64, i64)
define i64 @A2_vminuh(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.A2.vminuh(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vminuh({{.*}}, {{.*}})
+; CHECK: = vminuh({{.*}},{{.*}})
; Vector reduce minimum halfwords
declare i64 @llvm.hexagon.A4.vrminh(i64, i64, i32)
@@ -932,14 +932,14 @@ define i64 @A4_vrminh(i64 %a, i64 %b, i3
%z = call i64 @llvm.hexagon.A4.vrminh(i64 %a, i64 %b, i32 %c)
ret i64 %z
}
-; CHECK: = vrminh({{.*}}, {{.*}})
+; CHECK: = vrminh({{.*}},{{.*}})
declare i64 @llvm.hexagon.A4.vrminuh(i64, i64, i32)
define i64 @A4_vrminuh(i64 %a, i64 %b, i32 %c) {
%z = call i64 @llvm.hexagon.A4.vrminuh(i64 %a, i64 %b, i32 %c)
ret i64 %z
}
-; CHECK: = vrminuh({{.*}}, {{.*}})
+; CHECK: = vrminuh({{.*}},{{.*}})
; Vector reduce minimum words
declare i64 @llvm.hexagon.A4.vrminw(i64, i64, i32)
@@ -947,14 +947,14 @@ define i64 @A4_vrminw(i64 %a, i64 %b, i3
%z = call i64 @llvm.hexagon.A4.vrminw(i64 %a, i64 %b, i32 %c)
ret i64 %z
}
-; CHECK: = vrminw({{.*}}, {{.*}})
+; CHECK: = vrminw({{.*}},{{.*}})
declare i64 @llvm.hexagon.A4.vrminuw(i64, i64, i32)
define i64 @A4_vrminuw(i64 %a, i64 %b, i32 %c) {
%z = call i64 @llvm.hexagon.A4.vrminuw(i64 %a, i64 %b, i32 %c)
ret i64 %z
}
-; CHECK: = vrminuw({{.*}}, {{.*}})
+; CHECK: = vrminuw({{.*}},{{.*}})
; Vector sum of absolute differences unsigned bytes
declare i64 @llvm.hexagon.A2.vrsadub(i64, i64)
@@ -962,14 +962,14 @@ define i64 @A2_vrsadub(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.A2.vrsadub(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vrsadub({{.*}}, {{.*}})
+; CHECK: = vrsadub({{.*}},{{.*}})
declare i64 @llvm.hexagon.A2.vrsadub.acc(i64, i64, i64)
define i64 @A2_vrsadub_acc(i64 %a, i64 %b, i64 %c) {
%z = call i64 @llvm.hexagon.A2.vrsadub.acc(i64 %a, i64 %b, i64 %c)
ret i64 %z
}
-; CHECK: += vrsadub({{.*}}, {{.*}})
+; CHECK: += vrsadub({{.*}},{{.*}})
; Vector subtract halfwords
declare i64 @llvm.hexagon.A2.vsubh(i64, i64)
@@ -977,21 +977,21 @@ define i64 @A2_vsubh(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.A2.vsubh(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vsubh({{.*}}, {{.*}})
+; CHECK: = vsubh({{.*}},{{.*}})
declare i64 @llvm.hexagon.A2.vsubhs(i64, i64)
define i64 @A2_vsubhs(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.A2.vsubhs(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vsubh({{.*}}, {{.*}}):sat
+; CHECK: = vsubh({{.*}},{{.*}}):sat
declare i64 @llvm.hexagon.A2.vsubuhs(i64, i64)
define i64 @A2_vsubuhs(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.A2.vsubuhs(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vsubuh({{.*}}, {{.*}}):sat
+; CHECK: = vsubuh({{.*}},{{.*}}):sat
; Vector subtract bytes
declare i64 @llvm.hexagon.A2.vsubub(i64, i64)
@@ -999,14 +999,14 @@ define i64 @A2_vsubub(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.A2.vsubub(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vsubub({{.*}}, {{.*}})
+; CHECK: = vsubub({{.*}},{{.*}})
declare i64 @llvm.hexagon.A2.vsububs(i64, i64)
define i64 @A2_vsububs(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.A2.vsububs(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vsubub({{.*}}, {{.*}}):sat
+; CHECK: = vsubub({{.*}},{{.*}}):sat
; Vector subtract words
declare i64 @llvm.hexagon.A2.vsubw(i64, i64)
@@ -1014,11 +1014,11 @@ define i64 @A2_vsubw(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.A2.vsubw(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vsubw({{.*}}, {{.*}})
+; CHECK: = vsubw({{.*}},{{.*}})
declare i64 @llvm.hexagon.A2.vsubws(i64, i64)
define i64 @A2_vsubws(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.A2.vsubws(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vsubw({{.*}}, {{.*}}):sat
+; CHECK: = vsubw({{.*}},{{.*}}):sat
Modified: llvm/trunk/test/CodeGen/Hexagon/intrinsics/xtype_bit.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/intrinsics/xtype_bit.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/intrinsics/xtype_bit.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/intrinsics/xtype_bit.ll Fri Feb 10 09:33:13 2017
@@ -38,14 +38,14 @@ define i32 @S4_clbpaddi(i64 %a) {
%z = call i32 @llvm.hexagon.S4.clbpaddi(i64 %a, i32 0)
ret i32 %z
}
-; CHECK: = add(clb({{.*}}), #0)
+; CHECK: = add(clb({{.*}}),#0)
declare i32 @llvm.hexagon.S4.clbaddi(i32, i32)
define i32 @S4_clbaddi(i32 %a) {
%z = call i32 @llvm.hexagon.S4.clbaddi(i32 %a, i32 0)
ret i32 %z
}
-; CHECK: = add(clb({{.*}}), #0)
+; CHECK: = add(clb({{.*}}),#0)
declare i32 @llvm.hexagon.S2.cl0(i32)
define i32 @S2_cl0(i32 %a) {
@@ -111,56 +111,56 @@ define i64 @S2_extractup(i64 %a) {
%z = call i64 @llvm.hexagon.S2.extractup(i64 %a, i32 0, i32 0)
ret i64 %z
}
-; CHECK: = extractu({{.*}}, #0, #0)
+; CHECK: = extractu({{.*}},#0,#0)
declare i64 @llvm.hexagon.S4.extractp(i64, i32, i32)
define i64 @S2_extractp(i64 %a) {
%z = call i64 @llvm.hexagon.S4.extractp(i64 %a, i32 0, i32 0)
ret i64 %z
}
-; CHECK: = extract({{.*}}, #0, #0)
+; CHECK: = extract({{.*}},#0,#0)
declare i32 @llvm.hexagon.S2.extractu(i32, i32, i32)
define i32 @S2_extractu(i32 %a) {
%z = call i32 @llvm.hexagon.S2.extractu(i32 %a, i32 0, i32 0)
ret i32 %z
}
-; CHECK: = extractu({{.*}}, #0, #0)
+; CHECK: = extractu({{.*}},#0,#0)
declare i32 @llvm.hexagon.S4.extract(i32, i32, i32)
define i32 @S2_extract(i32 %a) {
%z = call i32 @llvm.hexagon.S4.extract(i32 %a, i32 0, i32 0)
ret i32 %z
}
-; CHECK: = extract({{.*}}, #0, #0)
+; CHECK: = extract({{.*}},#0,#0)
declare i64 @llvm.hexagon.S2.extractup.rp(i64, i64)
define i64 @S2_extractup_rp(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.S2.extractup.rp(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = extractu({{.*}}, {{.*}})
+; CHECK: = extractu({{.*}},{{.*}})
declare i64 @llvm.hexagon.S4.extractp.rp(i64, i64)
define i64 @S4_extractp_rp(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.S4.extractp.rp(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = extract({{.*}}, {{.*}})
+; CHECK: = extract({{.*}},{{.*}})
declare i32 @llvm.hexagon.S2.extractu.rp(i32, i64)
define i32 @S2_extractu_rp(i32 %a, i64 %b) {
%z = call i32 @llvm.hexagon.S2.extractu.rp(i32 %a, i64 %b)
ret i32 %z
}
-; CHECK: = extractu({{.*}}, {{.*}})
+; CHECK: = extractu({{.*}},{{.*}})
declare i32 @llvm.hexagon.S4.extract.rp(i32, i64)
define i32 @S4_extract_rp(i32 %a, i64 %b) {
%z = call i32 @llvm.hexagon.S4.extract.rp(i32 %a, i64 %b)
ret i32 %z
}
-; CHECK: = extract({{.*}}, {{.*}})
+; CHECK: = extract({{.*}},{{.*}})
; Insert bitfield
declare i64 @llvm.hexagon.S2.insertp(i64, i64, i32, i32)
@@ -168,28 +168,28 @@ define i64 @S2_insertp(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.S2.insertp(i64 %a, i64 %b, i32 0, i32 0)
ret i64 %z
}
-; CHECK: = insert({{.*}}, #0, #0)
+; CHECK: = insert({{.*}},#0,#0)
declare i32 @llvm.hexagon.S2.insert(i32, i32, i32, i32)
define i32 @S2_insert(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.S2.insert(i32 %a, i32 %b, i32 0, i32 0)
ret i32 %z
}
-; CHECK: = insert({{.*}}, #0, #0)
+; CHECK: = insert({{.*}},#0,#0)
declare i32 @llvm.hexagon.S2.insert.rp(i32, i32, i64)
define i32 @S2_insert_rp(i32 %a, i32 %b, i64 %c) {
%z = call i32 @llvm.hexagon.S2.insert.rp(i32 %a, i32 %b, i64 %c)
ret i32 %z
}
-; CHECK: = insert({{.*}}, {{.*}})
+; CHECK: = insert({{.*}},{{.*}})
declare i64 @llvm.hexagon.S2.insertp.rp(i64, i64, i64)
define i64 @S2_insertp_rp(i64 %a, i64 %b, i64 %c) {
%z = call i64 @llvm.hexagon.S2.insertp.rp(i64 %a, i64 %b, i64 %c)
ret i64 %z
}
-; CHECK: = insert({{.*}}, r5:4)
+; CHECK: = insert({{.*}},r5:4)
; Interleave/deinterleave
declare i64 @llvm.hexagon.S2.deinterleave(i64)
@@ -212,7 +212,7 @@ define i64 @S2_lfsp(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.S2.lfsp(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = lfs({{.*}}, {{.*}})
+; CHECK: = lfs({{.*}},{{.*}})
; Masked parity
declare i32 @llvm.hexagon.S2.parityp(i64, i64)
@@ -220,14 +220,14 @@ define i32 @S2_parityp(i64 %a, i64 %b) {
%z = call i32 @llvm.hexagon.S2.parityp(i64 %a, i64 %b)
ret i32 %z
}
-; CHECK: = parity({{.*}}, {{.*}})
+; CHECK: = parity({{.*}},{{.*}})
declare i32 @llvm.hexagon.S4.parity(i32, i32)
define i32 @S4_parity(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.S4.parity(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = parity({{.*}}, {{.*}})
+; CHECK: = parity({{.*}},{{.*}})
; Bit reverse
declare i64 @llvm.hexagon.S2.brevp(i64)
@@ -250,42 +250,42 @@ define i32 @S2_setbit_i(i32 %a) {
%z = call i32 @llvm.hexagon.S2.setbit.i(i32 %a, i32 0)
ret i32 %z
}
-; CHECK: = setbit({{.*}}, #0)
+; CHECK: = setbit({{.*}},#0)
declare i32 @llvm.hexagon.S2.clrbit.i(i32, i32)
define i32 @S2_clrbit_i(i32 %a) {
%z = call i32 @llvm.hexagon.S2.clrbit.i(i32 %a, i32 0)
ret i32 %z
}
-; CHECK: = clrbit({{.*}}, #0)
+; CHECK: = clrbit({{.*}},#0)
declare i32 @llvm.hexagon.S2.togglebit.i(i32, i32)
define i32 @S2_togglebit_i(i32 %a) {
%z = call i32 @llvm.hexagon.S2.togglebit.i(i32 %a, i32 0)
ret i32 %z
}
-; CHECK: = togglebit({{.*}}, #0)
+; CHECK: = togglebit({{.*}},#0)
declare i32 @llvm.hexagon.S2.setbit.r(i32, i32)
define i32 @S2_setbit_r(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.S2.setbit.r(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = setbit({{.*}}, {{.*}})
+; CHECK: = setbit({{.*}},{{.*}})
declare i32 @llvm.hexagon.S2.clrbit.r(i32, i32)
define i32 @S2_clrbit_r(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.S2.clrbit.r(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = clrbit({{.*}}, {{.*}})
+; CHECK: = clrbit({{.*}},{{.*}})
declare i32 @llvm.hexagon.S2.togglebit.r(i32, i32)
define i32 @S2_togglebit_r(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.S2.togglebit.r(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = togglebit({{.*}}, {{.*}})
+; CHECK: = togglebit({{.*}},{{.*}})
; Split bitfield
declare i64 @llvm.hexagon.A4.bitspliti(i32, i32)
@@ -293,14 +293,14 @@ define i64 @A4_bitspliti(i32 %a) {
%z = call i64 @llvm.hexagon.A4.bitspliti(i32 %a, i32 0)
ret i64 %z
}
-; CHECK: = bitsplit({{.*}}, #0)
+; CHECK: = bitsplit({{.*}},#0)
declare i64 @llvm.hexagon.A4.bitsplit(i32, i32)
define i64 @A4_bitsplit(i32 %a, i32 %b) {
%z = call i64 @llvm.hexagon.A4.bitsplit(i32 %a, i32 %b)
ret i64 %z
}
-; CHECK: = bitsplit({{.*}}, {{.*}})
+; CHECK: = bitsplit({{.*}},{{.*}})
; Table index
declare i32 @llvm.hexagon.S2.tableidxb.goodsyntax(i32, i32, i32, i32)
@@ -308,25 +308,25 @@ define i32 @S2_tableidxb_goodsyntax(i32
%z = call i32 @llvm.hexagon.S2.tableidxb.goodsyntax(i32 %a, i32 %b, i32 0, i32 0)
ret i32 %z
}
-; CHECK: = tableidxb({{.*}}, #0, #0)
+; CHECK: = tableidxb({{.*}},#0,#0)
declare i32 @llvm.hexagon.S2.tableidxh.goodsyntax(i32, i32, i32, i32)
define i32 @S2_tableidxh_goodsyntax(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.S2.tableidxh.goodsyntax(i32 %a, i32 %b, i32 0, i32 0)
ret i32 %z
}
-; CHECK: = tableidxh({{.*}}, #0, #-1)
+; CHECK: = tableidxh({{.*}},#0,#-1)
declare i32 @llvm.hexagon.S2.tableidxw.goodsyntax(i32, i32, i32, i32)
define i32 @S2_tableidxw_goodsyntax(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.S2.tableidxw.goodsyntax(i32 %a, i32 %b, i32 0, i32 0)
ret i32 %z
}
-; CHECK: = tableidxw({{.*}}, #0, #-2)
+; CHECK: = tableidxw({{.*}},#0,#-2)
declare i32 @llvm.hexagon.S2.tableidxd.goodsyntax(i32, i32, i32, i32)
define i32 @S2_tableidxd_goodsyntax(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.S2.tableidxd.goodsyntax(i32 %a, i32 %b, i32 0, i32 0)
ret i32 %z
}
-; CHECK: = tableidxd({{.*}}, #0, #-3)
+; CHECK: = tableidxd({{.*}},#0,#-3)
Modified: llvm/trunk/test/CodeGen/Hexagon/intrinsics/xtype_complex.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/intrinsics/xtype_complex.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/intrinsics/xtype_complex.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/intrinsics/xtype_complex.ll Fri Feb 10 09:33:13 2017
@@ -10,28 +10,28 @@ define i64 @S4_vxaddsubh(i64 %a, i64 %b)
%z = call i64 @llvm.hexagon.S4.vxaddsubh(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vxaddsubh({{.*}}, {{.*}}):sat
+; CHECK: = vxaddsubh({{.*}},{{.*}}):sat
declare i64 @llvm.hexagon.S4.vxsubaddh(i64, i64)
define i64 @S4_vxsubaddh(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.S4.vxsubaddh(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vxsubaddh({{.*}}, {{.*}}):sat
+; CHECK: = vxsubaddh({{.*}},{{.*}}):sat
declare i64 @llvm.hexagon.S4.vxaddsubhr(i64, i64)
define i64 @S4_vxaddsubhr(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.S4.vxaddsubhr(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vxaddsubh({{.*}}, {{.*}}):rnd:>>1:sat
+; CHECK: = vxaddsubh({{.*}},{{.*}}):rnd:>>1:sat
declare i64 @llvm.hexagon.S4.vxsubaddhr(i64, i64)
define i64 @S4_vxsubaddhr(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.S4.vxsubaddhr(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vxsubaddh({{.*}}, {{.*}}):rnd:>>1:sat
+; CHECK: = vxsubaddh({{.*}},{{.*}}):rnd:>>1:sat
; Complex add/sub words
declare i64 @llvm.hexagon.S4.vxaddsubw(i64, i64)
@@ -39,14 +39,14 @@ define i64 @S4_vxaddsubw(i64 %a, i64 %b)
%z = call i64 @llvm.hexagon.S4.vxaddsubw(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vxaddsubw({{.*}}, {{.*}}):sat
+; CHECK: = vxaddsubw({{.*}},{{.*}}):sat
declare i64 @llvm.hexagon.S4.vxsubaddw(i64, i64)
define i64 @S4_vxsubaddw(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.S4.vxsubaddw(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vxsubaddw({{.*}}, {{.*}}):sat
+; CHECK: = vxsubaddw({{.*}},{{.*}}):sat
; Complex multiply
declare i64 @llvm.hexagon.M2.cmpys.s0(i32, i32)
@@ -54,84 +54,84 @@ define i64 @M2_cmpys_s0(i32 %a, i32 %b)
%z = call i64 @llvm.hexagon.M2.cmpys.s0(i32 %a, i32 %b)
ret i64 %z
}
-; CHECK: = cmpy({{.*}}, {{.*}}):sat
+; CHECK: = cmpy({{.*}},{{.*}}):sat
declare i64 @llvm.hexagon.M2.cmpys.s1(i32, i32)
define i64 @M2_cmpys_s1(i32 %a, i32 %b) {
%z = call i64 @llvm.hexagon.M2.cmpys.s1(i32 %a, i32 %b)
ret i64 %z
}
-; CHECK: = cmpy({{.*}}, {{.*}}):<<1:sat
+; CHECK: = cmpy({{.*}},{{.*}}):<<1:sat
declare i64 @llvm.hexagon.M2.cmpysc.s0(i32, i32)
define i64 @M2_cmpysc_s0(i32 %a, i32 %b) {
%z = call i64 @llvm.hexagon.M2.cmpysc.s0(i32 %a, i32 %b)
ret i64 %z
}
-; CHECK: = cmpy({{.*}}, {{.*}}*):sat
+; CHECK: = cmpy({{.*}},{{.*}}*):sat
declare i64 @llvm.hexagon.M2.cmpysc.s1(i32, i32)
define i64 @M2_cmpysc_s1(i32 %a, i32 %b) {
%z = call i64 @llvm.hexagon.M2.cmpysc.s1(i32 %a, i32 %b)
ret i64 %z
}
-; CHECK: = cmpy({{.*}}, {{.*}}*):<<1:sat
+; CHECK: = cmpy({{.*}},{{.*}}*):<<1:sat
declare i64 @llvm.hexagon.M2.cmacs.s0(i64, i32, i32)
define i64 @M2_cmacs_s0(i64 %a, i32 %b, i32 %c) {
%z = call i64 @llvm.hexagon.M2.cmacs.s0(i64 %a, i32 %b, i32 %c)
ret i64 %z
}
-; CHECK: += cmpy({{.*}}, {{.*}}):sat
+; CHECK: += cmpy({{.*}},{{.*}}):sat
declare i64 @llvm.hexagon.M2.cmacs.s1(i64, i32, i32)
define i64 @M2_cmacs_s1(i64 %a, i32 %b, i32 %c) {
%z = call i64 @llvm.hexagon.M2.cmacs.s1(i64 %a, i32 %b, i32 %c)
ret i64 %z
}
-; CHECK: += cmpy({{.*}}, {{.*}}):<<1:sat
+; CHECK: += cmpy({{.*}},{{.*}}):<<1:sat
declare i64 @llvm.hexagon.M2.cnacs.s0(i64, i32, i32)
define i64 @M2_cnacs_s0(i64 %a, i32 %b, i32 %c) {
%z = call i64 @llvm.hexagon.M2.cnacs.s0(i64 %a, i32 %b, i32 %c)
ret i64 %z
}
-; CHECK: -= cmpy({{.*}}, {{.*}}):sat
+; CHECK: -= cmpy({{.*}},{{.*}}):sat
declare i64 @llvm.hexagon.M2.cnacs.s1(i64, i32, i32)
define i64 @M2_cnacs_s1(i64 %a, i32 %b, i32 %c) {
%z = call i64 @llvm.hexagon.M2.cnacs.s1(i64 %a, i32 %b, i32 %c)
ret i64 %z
}
-; CHECK: -= cmpy({{.*}}, {{.*}}):<<1:sat
+; CHECK: -= cmpy({{.*}},{{.*}}):<<1:sat
declare i64 @llvm.hexagon.M2.cmacsc.s0(i64, i32, i32)
define i64 @M2_cmacsc_s0(i64 %a, i32 %b, i32 %c) {
%z = call i64 @llvm.hexagon.M2.cmacsc.s0(i64 %a, i32 %b, i32 %c)
ret i64 %z
}
-; CHECK: += cmpy({{.*}}, {{.*}}*):sat
+; CHECK: += cmpy({{.*}},{{.*}}*):sat
declare i64 @llvm.hexagon.M2.cmacsc.s1(i64, i32, i32)
define i64 @M2_cmacsc_s1(i64 %a, i32 %b, i32 %c) {
%z = call i64 @llvm.hexagon.M2.cmacsc.s1(i64 %a, i32 %b, i32 %c)
ret i64 %z
}
-; CHECK: += cmpy({{.*}}, {{.*}}*):<<1:sat
+; CHECK: += cmpy({{.*}},{{.*}}*):<<1:sat
declare i64 @llvm.hexagon.M2.cnacsc.s0(i64, i32, i32)
define i64 @M2_cnacsc_s0(i64 %a, i32 %b, i32 %c) {
%z = call i64 @llvm.hexagon.M2.cnacsc.s0(i64 %a, i32 %b, i32 %c)
ret i64 %z
}
-; CHECK: -= cmpy({{.*}}, {{.*}}*):sat
+; CHECK: -= cmpy({{.*}},{{.*}}*):sat
declare i64 @llvm.hexagon.M2.cnacsc.s1(i64, i32, i32)
define i64 @M2_cnacsc_s1(i64 %a, i32 %b, i32 %c) {
%z = call i64 @llvm.hexagon.M2.cnacsc.s1(i64 %a, i32 %b, i32 %c)
ret i64 %z
}
-; CHECK: -= cmpy({{.*}}, {{.*}}*):<<1:sat
+; CHECK: -= cmpy({{.*}},{{.*}}*):<<1:sat
; Complex multiply real or imaginary
declare i64 @llvm.hexagon.M2.cmpyi.s0(i32, i32)
@@ -139,28 +139,28 @@ define i64 @M2_cmpyi_s0(i32 %a, i32 %b)
%z = call i64 @llvm.hexagon.M2.cmpyi.s0(i32 %a, i32 %b)
ret i64 %z
}
-; CHECK: = cmpyi({{.*}}, {{.*}})
+; CHECK: = cmpyi({{.*}},{{.*}})
declare i64 @llvm.hexagon.M2.cmpyr.s0(i32, i32)
define i64 @M2_cmpyr_s0(i32 %a, i32 %b) {
%z = call i64 @llvm.hexagon.M2.cmpyr.s0(i32 %a, i32 %b)
ret i64 %z
}
-; CHECK: = cmpyr({{.*}}, {{.*}})
+; CHECK: = cmpyr({{.*}},{{.*}})
declare i64 @llvm.hexagon.M2.cmaci.s0(i64, i32, i32)
define i64 @M2_cmaci_s0(i64 %a, i32 %b, i32 %c) {
%z = call i64 @llvm.hexagon.M2.cmaci.s0(i64 %a, i32 %b, i32 %c)
ret i64 %z
}
-; CHECK: += cmpyi({{.*}}, {{.*}})
+; CHECK: += cmpyi({{.*}},{{.*}})
declare i64 @llvm.hexagon.M2.cmacr.s0(i64, i32, i32)
define i64 @M2_cmacr_s0(i64 %a, i32 %b, i32 %c) {
%z = call i64 @llvm.hexagon.M2.cmacr.s0(i64 %a, i32 %b, i32 %c)
ret i64 %z
}
-; CHECK: += cmpyr({{.*}}, {{.*}})
+; CHECK: += cmpyr({{.*}},{{.*}})
; Complex multiply with round and pack
declare i32 @llvm.hexagon.M2.cmpyrs.s0(i32, i32)
@@ -168,28 +168,28 @@ define i32 @M2_cmpyrs_s0(i32 %a, i32 %b)
%z = call i32 @llvm.hexagon.M2.cmpyrs.s0(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = cmpy({{.*}}, {{.*}}):rnd:sat
+; CHECK: = cmpy({{.*}},{{.*}}):rnd:sat
declare i32 @llvm.hexagon.M2.cmpyrs.s1(i32, i32)
define i32 @M2_cmpyrs_s1(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.M2.cmpyrs.s1(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = cmpy({{.*}}, {{.*}}):<<1:rnd:sat
+; CHECK: = cmpy({{.*}},{{.*}}):<<1:rnd:sat
declare i32 @llvm.hexagon.M2.cmpyrsc.s0(i32, i32)
define i32 @M2_cmpyrsc_s0(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.M2.cmpyrsc.s0(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = cmpy({{.*}}, {{.*}}*):rnd:sat
+; CHECK: = cmpy({{.*}},{{.*}}*):rnd:sat
declare i32 @llvm.hexagon.M2.cmpyrsc.s1(i32, i32)
define i32 @M2_cmpyrsc_s1(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.M2.cmpyrsc.s1(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = cmpy({{.*}}, {{.*}}*):<<1:rnd:sat
+; CHECK: = cmpy({{.*}},{{.*}}*):<<1:rnd:sat
; Complex multiply 32x16
declare i32 @llvm.hexagon.M4.cmpyi.wh(i64, i32)
@@ -197,28 +197,28 @@ define i32 @M4_cmpyi_wh(i64 %a, i32 %b)
%z = call i32 @llvm.hexagon.M4.cmpyi.wh(i64 %a, i32 %b)
ret i32 %z
}
-; CHECK: = cmpyiwh({{.*}}, {{.*}}):<<1:rnd:sat
+; CHECK: = cmpyiwh({{.*}},{{.*}}):<<1:rnd:sat
declare i32 @llvm.hexagon.M4.cmpyi.whc(i64, i32)
define i32 @M4_cmpyi_whc(i64 %a, i32 %b) {
%z = call i32 @llvm.hexagon.M4.cmpyi.whc(i64 %a, i32 %b)
ret i32 %z
}
-; CHECK: = cmpyiwh({{.*}}, {{.*}}*):<<1:rnd:sat
+; CHECK: = cmpyiwh({{.*}},{{.*}}*):<<1:rnd:sat
declare i32 @llvm.hexagon.M4.cmpyr.wh(i64, i32)
define i32 @M4_cmpyr_wh(i64 %a, i32 %b) {
%z = call i32 @llvm.hexagon.M4.cmpyr.wh(i64 %a, i32 %b)
ret i32 %z
}
-; CHECK: = cmpyrwh({{.*}}, {{.*}}):<<1:rnd:sat
+; CHECK: = cmpyrwh({{.*}},{{.*}}):<<1:rnd:sat
declare i32 @llvm.hexagon.M4.cmpyr.whc(i64, i32)
define i32 @M4_cmpyr_whc(i64 %a, i32 %b) {
%z = call i32 @llvm.hexagon.M4.cmpyr.whc(i64 %a, i32 %b)
ret i32 %z
}
-; CHECK: = cmpyrwh({{.*}}, {{.*}}*):<<1:rnd:sat
+; CHECK: = cmpyrwh({{.*}},{{.*}}*):<<1:rnd:sat
; Vector complex multiply real or imaginary
declare i64 @llvm.hexagon.M2.vcmpy.s0.sat.r(i64, i64)
@@ -226,42 +226,42 @@ define i64 @M2_vcmpy_s0_sat_r(i64 %a, i6
%z = call i64 @llvm.hexagon.M2.vcmpy.s0.sat.r(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vcmpyr({{.*}}, {{.*}}):sat
+; CHECK: = vcmpyr({{.*}},{{.*}}):sat
declare i64 @llvm.hexagon.M2.vcmpy.s1.sat.r(i64, i64)
define i64 @M2_vcmpy_s1_sat_r(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.M2.vcmpy.s1.sat.r(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vcmpyr({{.*}}, {{.*}}):<<1:sat
+; CHECK: = vcmpyr({{.*}},{{.*}}):<<1:sat
declare i64 @llvm.hexagon.M2.vcmpy.s0.sat.i(i64, i64)
define i64 @M2_vcmpy_s0_sat_i(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.M2.vcmpy.s0.sat.i(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vcmpyi({{.*}}, {{.*}}):sat
+; CHECK: = vcmpyi({{.*}},{{.*}}):sat
declare i64 @llvm.hexagon.M2.vcmpy.s1.sat.i(i64, i64)
define i64 @M2_vcmpy_s1_sat_i(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.M2.vcmpy.s1.sat.i(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vcmpyi({{.*}}, {{.*}}):<<1:sat
+; CHECK: = vcmpyi({{.*}},{{.*}}):<<1:sat
declare i64 @llvm.hexagon.M2.vcmac.s0.sat.r(i64, i64, i64)
define i64 @M2_vcmac_s0_sat_r(i64 %a, i64 %b, i64 %c) {
%z = call i64 @llvm.hexagon.M2.vcmac.s0.sat.r(i64 %a, i64 %b, i64 %c)
ret i64 %z
}
-; CHECK: += vcmpyr({{.*}}, r5:4):sat
+; CHECK: += vcmpyr({{.*}},r5:4):sat
declare i64 @llvm.hexagon.M2.vcmac.s0.sat.i(i64, i64, i64)
define i64 @M2_vcmac_s0_sat_i(i64 %a, i64 %b, i64 %c) {
%z = call i64 @llvm.hexagon.M2.vcmac.s0.sat.i(i64 %a, i64 %b, i64 %c)
ret i64 %z
}
-; CHECK: += vcmpyi({{.*}}, r5:4):sat
+; CHECK: += vcmpyi({{.*}},r5:4):sat
; Vector complex conjugate
declare i64 @llvm.hexagon.A2.vconj(i64)
@@ -277,7 +277,7 @@ define i64 @S2_vcrotate(i64 %a, i32 %b)
%z = call i64 @llvm.hexagon.S2.vcrotate(i64 %a, i32 %b)
ret i64 %z
}
-; CHECK: = vcrotate({{.*}}, {{.*}})
+; CHECK: = vcrotate({{.*}},{{.*}})
; Vector reduce complex multiply real or imaginary
declare i64 @llvm.hexagon.M2.vrcmpyi.s0(i64, i64)
@@ -285,56 +285,56 @@ define i64 @M2_vrcmpyi_s0(i64 %a, i64 %b
%z = call i64 @llvm.hexagon.M2.vrcmpyi.s0(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vrcmpyi({{.*}}, {{.*}})
+; CHECK: = vrcmpyi({{.*}},{{.*}})
declare i64 @llvm.hexagon.M2.vrcmpyr.s0(i64, i64)
define i64 @M2_vrcmpyr_s0(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.M2.vrcmpyr.s0(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vrcmpyr({{.*}}, {{.*}})
+; CHECK: = vrcmpyr({{.*}},{{.*}})
declare i64 @llvm.hexagon.M2.vrcmpyi.s0c(i64, i64)
define i64 @M2_vrcmpyi_s0c(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.M2.vrcmpyi.s0c(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vrcmpyi({{.*}}, {{.*}}*)
+; CHECK: = vrcmpyi({{.*}},{{.*}}*)
declare i64 @llvm.hexagon.M2.vrcmpyr.s0c(i64, i64)
define i64 @M2_vrcmpyr_s0c(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.M2.vrcmpyr.s0c(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vrcmpyr({{.*}}, {{.*}}*)
+; CHECK: = vrcmpyr({{.*}},{{.*}}*)
declare i64 @llvm.hexagon.M2.vrcmaci.s0(i64, i64, i64)
define i64 @M2_vrcmaci_s0(i64 %a, i64 %b, i64 %c) {
%z = call i64 @llvm.hexagon.M2.vrcmaci.s0(i64 %a, i64 %b, i64 %c)
ret i64 %z
}
-; CHECK: += vrcmpyi({{.*}}, r5:4)
+; CHECK: += vrcmpyi({{.*}},r5:4)
declare i64 @llvm.hexagon.M2.vrcmacr.s0(i64, i64, i64)
define i64 @M2_vrcmacr_s0(i64 %a, i64 %b, i64 %c) {
%z = call i64 @llvm.hexagon.M2.vrcmacr.s0(i64 %a, i64 %b, i64 %c)
ret i64 %z
}
-; CHECK: += vrcmpyr({{.*}}, r5:4)
+; CHECK: += vrcmpyr({{.*}},r5:4)
declare i64 @llvm.hexagon.M2.vrcmaci.s0c(i64, i64, i64)
define i64 @M2_vrcmaci_s0c(i64 %a, i64 %b, i64 %c) {
%z = call i64 @llvm.hexagon.M2.vrcmaci.s0c(i64 %a, i64 %b, i64 %c)
ret i64 %z
}
-; CHECK: += vrcmpyi({{.*}}, r5:4*)
+; CHECK: += vrcmpyi({{.*}},r5:4*)
declare i64 @llvm.hexagon.M2.vrcmacr.s0c(i64, i64, i64)
define i64 @M2_vrcmacr_s0c(i64 %a, i64 %b, i64 %c) {
%z = call i64 @llvm.hexagon.M2.vrcmacr.s0c(i64 %a, i64 %b, i64 %c)
ret i64 %z
}
-; CHECK: += vrcmpyr({{.*}}, r5:4*)
+; CHECK: += vrcmpyr({{.*}},r5:4*)
; Vector reduce complex rotate
declare i64 @llvm.hexagon.S4.vrcrotate(i64, i32, i32)
@@ -342,11 +342,11 @@ define i64 @S4_vrcrotate(i64 %a, i32 %b)
%z = call i64 @llvm.hexagon.S4.vrcrotate(i64 %a, i32 %b, i32 0)
ret i64 %z
}
-; CHECK: = vrcrotate({{.*}}, {{.*}}, #0)
+; CHECK: = vrcrotate({{.*}},{{.*}},#0)
declare i64 @llvm.hexagon.S4.vrcrotate.acc(i64, i64, i32, i32)
define i64 @S4_vrcrotate_acc(i64 %a, i64 %b, i32 %c) {
%z = call i64 @llvm.hexagon.S4.vrcrotate.acc(i64 %a, i64 %b, i32 %c, i32 0)
ret i64 %z
}
-; CHECK: += vrcrotate({{.*}}, {{.*}}, #0)
+; CHECK: += vrcrotate({{.*}},{{.*}},#0)
Modified: llvm/trunk/test/CodeGen/Hexagon/intrinsics/xtype_fp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/intrinsics/xtype_fp.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/intrinsics/xtype_fp.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/intrinsics/xtype_fp.ll Fri Feb 10 09:33:13 2017
@@ -11,7 +11,7 @@ define float @F2_sfadd(float %a, float %
%z = call float @llvm.hexagon.F2.sfadd(float %a, float %b)
ret float %z
}
-; CHECK: = sfadd({{.*}}, {{.*}})
+; CHECK: = sfadd({{.*}},{{.*}})
; Classify floating-point value
declare i32 @llvm.hexagon.F2.sfclass(float, i32)
@@ -19,14 +19,14 @@ define i32 @F2_sfclass(float %a) {
%z = call i32 @llvm.hexagon.F2.sfclass(float %a, i32 0)
ret i32 %z
}
-; CHECK: = sfclass({{.*}}, #0)
+; CHECK: = sfclass({{.*}},#0)
declare i32 @llvm.hexagon.F2.dfclass(double, i32)
define i32 @F2_dfclass(double %a) {
%z = call i32 @llvm.hexagon.F2.dfclass(double %a, i32 0)
ret i32 %z
}
-; CHECK: = dfclass({{.*}}, #0)
+; CHECK: = dfclass({{.*}},#0)
; Compare floating-point value
declare i32 @llvm.hexagon.F2.sfcmpge(float, float)
@@ -34,56 +34,56 @@ define i32 @F2_sfcmpge(float %a, float %
%z = call i32 @llvm.hexagon.F2.sfcmpge(float %a, float %b)
ret i32 %z
}
-; CHECK: = sfcmp.ge({{.*}}, {{.*}})
+; CHECK: = sfcmp.ge({{.*}},{{.*}})
declare i32 @llvm.hexagon.F2.sfcmpuo(float, float)
define i32 @F2_sfcmpuo(float %a, float %b) {
%z = call i32 @llvm.hexagon.F2.sfcmpuo(float %a, float %b)
ret i32 %z
}
-; CHECK: = sfcmp.uo({{.*}}, {{.*}})
+; CHECK: = sfcmp.uo({{.*}},{{.*}})
declare i32 @llvm.hexagon.F2.sfcmpeq(float, float)
define i32 @F2_sfcmpeq(float %a, float %b) {
%z = call i32 @llvm.hexagon.F2.sfcmpeq(float %a, float %b)
ret i32 %z
}
-; CHECK: = sfcmp.eq({{.*}}, {{.*}})
+; CHECK: = sfcmp.eq({{.*}},{{.*}})
declare i32 @llvm.hexagon.F2.sfcmpgt(float, float)
define i32 @F2_sfcmpgt(float %a, float %b) {
%z = call i32 @llvm.hexagon.F2.sfcmpgt(float %a, float %b)
ret i32 %z
}
-; CHECK: = sfcmp.gt({{.*}}, {{.*}})
+; CHECK: = sfcmp.gt({{.*}},{{.*}})
declare i32 @llvm.hexagon.F2.dfcmpge(double, double)
define i32 @F2_dfcmpge(double %a, double %b) {
%z = call i32 @llvm.hexagon.F2.dfcmpge(double %a, double %b)
ret i32 %z
}
-; CHECK: = dfcmp.ge({{.*}}, {{.*}})
+; CHECK: = dfcmp.ge({{.*}},{{.*}})
declare i32 @llvm.hexagon.F2.dfcmpuo(double, double)
define i32 @F2_dfcmpuo(double %a, double %b) {
%z = call i32 @llvm.hexagon.F2.dfcmpuo(double %a, double %b)
ret i32 %z
}
-; CHECK: = dfcmp.uo({{.*}}, {{.*}})
+; CHECK: = dfcmp.uo({{.*}},{{.*}})
declare i32 @llvm.hexagon.F2.dfcmpeq(double, double)
define i32 @F2_dfcmpeq(double %a, double %b) {
%z = call i32 @llvm.hexagon.F2.dfcmpeq(double %a, double %b)
ret i32 %z
}
-; CHECK: = dfcmp.eq({{.*}}, {{.*}})
+; CHECK: = dfcmp.eq({{.*}},{{.*}})
declare i32 @llvm.hexagon.F2.dfcmpgt(double, double)
define i32 @F2_dfcmpgt(double %a, double %b) {
%z = call i32 @llvm.hexagon.F2.dfcmpgt(double %a, double %b)
ret i32 %z
}
-; CHECK: = dfcmp.gt({{.*}}, {{.*}})
+; CHECK: = dfcmp.gt({{.*}},{{.*}})
; Convert floating-point value to other format
declare double @llvm.hexagon.F2.conv.sf2df(float)
@@ -283,14 +283,14 @@ define float @F2_sffixupn(float %a, floa
%z = call float @llvm.hexagon.F2.sffixupn(float %a, float %b)
ret float %z
}
-; CHECK: = sffixupn({{.*}}, {{.*}})
+; CHECK: = sffixupn({{.*}},{{.*}})
declare float @llvm.hexagon.F2.sffixupd(float, float)
define float @F2_sffixupd(float %a, float %b) {
%z = call float @llvm.hexagon.F2.sffixupd(float %a, float %b)
ret float %z
}
-; CHECK: = sffixupd({{.*}}, {{.*}})
+; CHECK: = sffixupd({{.*}},{{.*}})
; Floating point fused multiply-add
declare float @llvm.hexagon.F2.sffma(float, float, float)
@@ -298,14 +298,14 @@ define float @F2_sffma(float %a, float %
%z = call float @llvm.hexagon.F2.sffma(float %a, float %b, float %c)
ret float %z
}
-; CHECK: += sfmpy({{.*}}, {{.*}})
+; CHECK: += sfmpy({{.*}},{{.*}})
declare float @llvm.hexagon.F2.sffms(float, float, float)
define float @F2_sffms(float %a, float %b, float %c) {
%z = call float @llvm.hexagon.F2.sffms(float %a, float %b, float %c)
ret float %z
}
-; CHECK: -= sfmpy({{.*}}, {{.*}})
+; CHECK: -= sfmpy({{.*}},{{.*}})
; Floating point fused multiply-add with scaling
declare float @llvm.hexagon.F2.sffma.sc(float, float, float, i32)
@@ -313,7 +313,7 @@ define float @F2_sffma_sc(float %a, floa
%z = call float @llvm.hexagon.F2.sffma.sc(float %a, float %b, float %c, i32 %d)
ret float %z
}
-; CHECK: += sfmpy({{.*}}, {{.*}}, {{.*}}):scale
+; CHECK: += sfmpy({{.*}},{{.*}},{{.*}}):scale
; Floating point fused multiply-add for library routines
declare float @llvm.hexagon.F2.sffma.lib(float, float, float)
@@ -321,14 +321,14 @@ define float @F2_sffma_lib(float %a, flo
%z = call float @llvm.hexagon.F2.sffma.lib(float %a, float %b, float %c)
ret float %z
}
-; CHECK: += sfmpy({{.*}}, {{.*}}):lib
+; CHECK: += sfmpy({{.*}},{{.*}}):lib
declare float @llvm.hexagon.F2.sffms.lib(float, float, float)
define float @F2_sffms_lib(float %a, float %b, float %c) {
%z = call float @llvm.hexagon.F2.sffms.lib(float %a, float %b, float %c)
ret float %z
}
-; CHECK: -= sfmpy({{.*}}, {{.*}}):lib
+; CHECK: -= sfmpy({{.*}},{{.*}}):lib
; Create floating-point constant
declare float @llvm.hexagon.F2.sfimm.p(i32)
@@ -365,7 +365,7 @@ define float @F2_sfmax(float %a, float %
%z = call float @llvm.hexagon.F2.sfmax(float %a, float %b)
ret float %z
}
-; CHECK: = sfmax({{.*}}, {{.*}})
+; CHECK: = sfmax({{.*}},{{.*}})
; Floating point minimum
declare float @llvm.hexagon.F2.sfmin(float, float)
@@ -373,7 +373,7 @@ define float @F2_sfmin(float %a, float %
%z = call float @llvm.hexagon.F2.sfmin(float %a, float %b)
ret float %z
}
-; CHECK: = sfmin({{.*}}, {{.*}})
+; CHECK: = sfmin({{.*}},{{.*}})
; Floating point multiply
declare float @llvm.hexagon.F2.sfmpy(float, float)
@@ -381,7 +381,7 @@ define float @F2_sfmpy(float %a, float %
%z = call float @llvm.hexagon.F2.sfmpy(float %a, float %b)
ret float %z
}
-; CHECK: = sfmpy({{.*}}, {{.*}})
+; CHECK: = sfmpy({{.*}},{{.*}})
; Floating point subtraction
declare float @llvm.hexagon.F2.sfsub(float, float)
@@ -389,4 +389,4 @@ define float @F2_sfsub(float %a, float %
%z = call float @llvm.hexagon.F2.sfsub(float %a, float %b)
ret float %z
}
-; CHECK: = sfsub({{.*}}, {{.*}})
+; CHECK: = sfsub({{.*}},{{.*}})
Modified: llvm/trunk/test/CodeGen/Hexagon/intrinsics/xtype_mpy.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/intrinsics/xtype_mpy.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/intrinsics/xtype_mpy.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/intrinsics/xtype_mpy.ll Fri Feb 10 09:33:13 2017
@@ -11,35 +11,35 @@ define i32 @M4_mpyrr_addi(i32 %a, i32 %b
%z = call i32 @llvm.hexagon.M4.mpyrr.addi(i32 0, i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = add(#0, mpyi({{.*}}, {{.*}}))
+; CHECK: = add(#0,mpyi({{.*}},{{.*}}))
declare i32 @llvm.hexagon.M4.mpyri.addi(i32, i32, i32)
define i32 @M4_mpyri_addi(i32 %a) {
%z = call i32 @llvm.hexagon.M4.mpyri.addi(i32 0, i32 %a, i32 0)
ret i32 %z
}
-; CHECK: = add(#0, mpyi({{.*}}, #0))
+; CHECK: = add(#0,mpyi({{.*}},#0))
declare i32 @llvm.hexagon.M4.mpyri.addr.u2(i32, i32, i32)
define i32 @M4_mpyri_addr_u2(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.M4.mpyri.addr.u2(i32 %a, i32 0, i32 %b)
ret i32 %z
}
-; CHECK: = add({{.*}}, mpyi(#0, {{.*}}))
+; CHECK: = add({{.*}},mpyi(#0,{{.*}}))
declare i32 @llvm.hexagon.M4.mpyri.addr(i32, i32, i32)
define i32 @M4_mpyri_addr(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.M4.mpyri.addr(i32 %a, i32 %b, i32 0)
ret i32 %z
}
-; CHECK: = add({{.*}}, mpyi({{.*}}, #0))
+; CHECK: = add({{.*}},mpyi({{.*}},#0))
declare i32 @llvm.hexagon.M4.mpyrr.addr(i32, i32, i32)
define i32 @M4_mpyrr_addr(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M4.mpyrr.addr(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: = add({{.*}}, mpyi({{.*}}, {{.*}}))
+; CHECK: = add({{.*}},mpyi({{.*}},{{.*}}))
; Vector multiply word by signed half (32x16)
declare i64 @llvm.hexagon.M2.mmpyl.s0(i64, i64)
@@ -47,56 +47,56 @@ define i64 @M2_mmpyl_s0(i64 %a, i64 %b)
%z = call i64 @llvm.hexagon.M2.mmpyl.s0(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vmpyweh({{.*}}, {{.*}}):sat
+; CHECK: = vmpyweh({{.*}},{{.*}}):sat
declare i64 @llvm.hexagon.M2.mmpyl.s1(i64, i64)
define i64 @M2_mmpyl_s1(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.M2.mmpyl.s1(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vmpyweh({{.*}}, {{.*}}):<<1:sat
+; CHECK: = vmpyweh({{.*}},{{.*}}):<<1:sat
declare i64 @llvm.hexagon.M2.mmpyh.s0(i64, i64)
define i64 @M2_mmpyh_s0(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.M2.mmpyh.s0(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vmpywoh({{.*}}, {{.*}}):sat
+; CHECK: = vmpywoh({{.*}},{{.*}}):sat
declare i64 @llvm.hexagon.M2.mmpyh.s1(i64, i64)
define i64 @M2_mmpyh_s1(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.M2.mmpyh.s1(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vmpywoh({{.*}}, {{.*}}):<<1:sat
+; CHECK: = vmpywoh({{.*}},{{.*}}):<<1:sat
declare i64 @llvm.hexagon.M2.mmpyl.rs0(i64, i64)
define i64 @M2_mmpyl_rs0(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.M2.mmpyl.rs0(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vmpyweh({{.*}}, {{.*}}):rnd:sat
+; CHECK: = vmpyweh({{.*}},{{.*}}):rnd:sat
declare i64 @llvm.hexagon.M2.mmpyl.rs1(i64, i64)
define i64 @M2_mmpyl_rs1(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.M2.mmpyl.rs1(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vmpyweh({{.*}}, {{.*}}):<<1:rnd:sat
+; CHECK: = vmpyweh({{.*}},{{.*}}):<<1:rnd:sat
declare i64 @llvm.hexagon.M2.mmpyh.rs0(i64, i64)
define i64 @M2_mmpyh_rs0(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.M2.mmpyh.rs0(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vmpywoh({{.*}}, {{.*}}):rnd:sat
+; CHECK: = vmpywoh({{.*}},{{.*}}):rnd:sat
declare i64 @llvm.hexagon.M2.mmpyh.rs1(i64, i64)
define i64 @M2_mmpyh_rs1(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.M2.mmpyh.rs1(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vmpywoh({{.*}}, {{.*}}):<<1:rnd:sat
+; CHECK: = vmpywoh({{.*}},{{.*}}):<<1:rnd:sat
; Vector multiply word by unsigned half (32x16)
declare i64 @llvm.hexagon.M2.mmpyul.s0(i64, i64)
@@ -104,56 +104,56 @@ define i64 @M2_mmpyul_s0(i64 %a, i64 %b)
%z = call i64 @llvm.hexagon.M2.mmpyul.s0(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vmpyweuh({{.*}}, {{.*}}):sat
+; CHECK: = vmpyweuh({{.*}},{{.*}}):sat
declare i64 @llvm.hexagon.M2.mmpyul.s1(i64, i64)
define i64 @M2_mmpyul_s1(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.M2.mmpyul.s1(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vmpyweuh({{.*}}, {{.*}}):<<1:sat
+; CHECK: = vmpyweuh({{.*}},{{.*}}):<<1:sat
declare i64 @llvm.hexagon.M2.mmpyuh.s0(i64, i64)
define i64 @M2_mmpyuh_s0(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.M2.mmpyuh.s0(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vmpywouh({{.*}}, {{.*}}):sat
+; CHECK: = vmpywouh({{.*}},{{.*}}):sat
declare i64 @llvm.hexagon.M2.mmpyuh.s1(i64, i64)
define i64 @M2_mmpyuh_s1(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.M2.mmpyuh.s1(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vmpywouh({{.*}}, {{.*}}):<<1:sat
+; CHECK: = vmpywouh({{.*}},{{.*}}):<<1:sat
declare i64 @llvm.hexagon.M2.mmpyul.rs0(i64, i64)
define i64 @M2_mmpyul_rs0(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.M2.mmpyul.rs0(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vmpyweuh({{.*}}, {{.*}}):rnd:sat
+; CHECK: = vmpyweuh({{.*}},{{.*}}):rnd:sat
declare i64 @llvm.hexagon.M2.mmpyul.rs1(i64, i64)
define i64 @M2_mmpyul_rs1(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.M2.mmpyul.rs1(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vmpyweuh({{.*}}, {{.*}}):<<1:rnd:sat
+; CHECK: = vmpyweuh({{.*}},{{.*}}):<<1:rnd:sat
declare i64 @llvm.hexagon.M2.mmpyuh.rs0(i64, i64)
define i64 @M2_mmpyuh_rs0(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.M2.mmpyuh.rs0(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vmpywouh({{.*}}, {{.*}}):rnd:sat
+; CHECK: = vmpywouh({{.*}},{{.*}}):rnd:sat
declare i64 @llvm.hexagon.M2.mmpyuh.rs1(i64, i64)
define i64 @M2_mmpyuh_rs1(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.M2.mmpyuh.rs1(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vmpywouh({{.*}}, {{.*}}):<<1:rnd:sat
+; CHECK: = vmpywouh({{.*}},{{.*}}):<<1:rnd:sat
; Multiply signed halfwords
declare i64 @llvm.hexagon.M2.mpyd.ll.s0(i32, i32)
@@ -161,616 +161,616 @@ define i64 @M2_mpyd_ll_s0(i32 %a, i32 %b
%z = call i64 @llvm.hexagon.M2.mpyd.ll.s0(i32 %a, i32 %b)
ret i64 %z
}
-; CHECK: = mpy({{.*}}.l, {{.*}}.l)
+; CHECK: = mpy({{.*}}.l,{{.*}}.l)
declare i64 @llvm.hexagon.M2.mpyd.ll.s1(i32, i32)
define i64 @M2_mpyd_ll_s1(i32 %a, i32 %b) {
%z = call i64 @llvm.hexagon.M2.mpyd.ll.s1(i32 %a, i32 %b)
ret i64 %z
}
-; CHECK: = mpy({{.*}}.l, {{.*}}.l):<<1
+; CHECK: = mpy({{.*}}.l,{{.*}}.l):<<1
declare i64 @llvm.hexagon.M2.mpyd.lh.s0(i32, i32)
define i64 @M2_mpyd_lh_s0(i32 %a, i32 %b) {
%z = call i64 @llvm.hexagon.M2.mpyd.lh.s0(i32 %a, i32 %b)
ret i64 %z
}
-; CHECK: = mpy({{.*}}.l, {{.*}}.h)
+; CHECK: = mpy({{.*}}.l,{{.*}}.h)
declare i64 @llvm.hexagon.M2.mpyd.lh.s1(i32, i32)
define i64 @M2_mpyd_lh_s1(i32 %a, i32 %b) {
%z = call i64 @llvm.hexagon.M2.mpyd.lh.s1(i32 %a, i32 %b)
ret i64 %z
}
-; CHECK: = mpy({{.*}}.l, {{.*}}.h):<<1
+; CHECK: = mpy({{.*}}.l,{{.*}}.h):<<1
declare i64 @llvm.hexagon.M2.mpyd.hl.s0(i32, i32)
define i64 @M2_mpyd_hl_s0(i32 %a, i32 %b) {
%z = call i64 @llvm.hexagon.M2.mpyd.hl.s0(i32 %a, i32 %b)
ret i64 %z
}
-; CHECK: = mpy({{.*}}.h, {{.*}}.l)
+; CHECK: = mpy({{.*}}.h,{{.*}}.l)
declare i64 @llvm.hexagon.M2.mpyd.hl.s1(i32, i32)
define i64 @M2_mpyd_hl_s1(i32 %a, i32 %b) {
%z = call i64 @llvm.hexagon.M2.mpyd.hl.s1(i32 %a, i32 %b)
ret i64 %z
}
-; CHECK: = mpy({{.*}}.h, {{.*}}.l):<<1
+; CHECK: = mpy({{.*}}.h,{{.*}}.l):<<1
declare i64 @llvm.hexagon.M2.mpyd.hh.s0(i32, i32)
define i64 @M2_mpyd_hh_s0(i32 %a, i32 %b) {
%z = call i64 @llvm.hexagon.M2.mpyd.hh.s0(i32 %a, i32 %b)
ret i64 %z
}
-; CHECK: = mpy({{.*}}.h, {{.*}}.h)
+; CHECK: = mpy({{.*}}.h,{{.*}}.h)
declare i64 @llvm.hexagon.M2.mpyd.hh.s1(i32, i32)
define i64 @M2_mpyd_hh_s1(i32 %a, i32 %b) {
%z = call i64 @llvm.hexagon.M2.mpyd.hh.s1(i32 %a, i32 %b)
ret i64 %z
}
-; CHECK: = mpy({{.*}}.h, {{.*}}.h):<<1
+; CHECK: = mpy({{.*}}.h,{{.*}}.h):<<1
declare i64 @llvm.hexagon.M2.mpyd.rnd.ll.s0(i32, i32)
define i64 @M2_mpyd_rnd_ll_s0(i32 %a, i32 %b) {
%z = call i64 @llvm.hexagon.M2.mpyd.rnd.ll.s0(i32 %a, i32 %b)
ret i64 %z
}
-; CHECK: = mpy({{.*}}.l, {{.*}}.l):rnd
+; CHECK: = mpy({{.*}}.l,{{.*}}.l):rnd
declare i64 @llvm.hexagon.M2.mpyd.rnd.ll.s1(i32, i32)
define i64 @M2_mpyd_rnd_ll_s1(i32 %a, i32 %b) {
%z = call i64 @llvm.hexagon.M2.mpyd.rnd.ll.s1(i32 %a, i32 %b)
ret i64 %z
}
-; CHECK: = mpy({{.*}}.l, {{.*}}.l):<<1:rnd
+; CHECK: = mpy({{.*}}.l,{{.*}}.l):<<1:rnd
declare i64 @llvm.hexagon.M2.mpyd.rnd.lh.s0(i32, i32)
define i64 @M2_mpyd_rnd_lh_s0(i32 %a, i32 %b) {
%z = call i64 @llvm.hexagon.M2.mpyd.rnd.lh.s0(i32 %a, i32 %b)
ret i64 %z
}
-; CHECK: = mpy({{.*}}.l, {{.*}}.h):rnd
+; CHECK: = mpy({{.*}}.l,{{.*}}.h):rnd
declare i64 @llvm.hexagon.M2.mpyd.rnd.lh.s1(i32, i32)
define i64 @M2_mpyd_rnd_lh_s1(i32 %a, i32 %b) {
%z = call i64 @llvm.hexagon.M2.mpyd.rnd.lh.s1(i32 %a, i32 %b)
ret i64 %z
}
-; CHECK: = mpy({{.*}}.l, {{.*}}.h):<<1:rnd
+; CHECK: = mpy({{.*}}.l,{{.*}}.h):<<1:rnd
declare i64 @llvm.hexagon.M2.mpyd.rnd.hl.s0(i32, i32)
define i64 @M2_mpyd_rnd_hl_s0(i32 %a, i32 %b) {
%z = call i64 @llvm.hexagon.M2.mpyd.rnd.hl.s0(i32 %a, i32 %b)
ret i64 %z
}
-; CHECK: = mpy({{.*}}.h, {{.*}}.l):rnd
+; CHECK: = mpy({{.*}}.h,{{.*}}.l):rnd
declare i64 @llvm.hexagon.M2.mpyd.rnd.hl.s1(i32, i32)
define i64 @M2_mpyd_rnd_hl_s1(i32 %a, i32 %b) {
%z = call i64 @llvm.hexagon.M2.mpyd.rnd.hl.s1(i32 %a, i32 %b)
ret i64 %z
}
-; CHECK: = mpy({{.*}}.h, {{.*}}.l):<<1:rnd
+; CHECK: = mpy({{.*}}.h,{{.*}}.l):<<1:rnd
declare i64 @llvm.hexagon.M2.mpyd.rnd.hh.s0(i32, i32)
define i64 @M2_mpyd_rnd_hh_s0(i32 %a, i32 %b) {
%z = call i64 @llvm.hexagon.M2.mpyd.rnd.hh.s0(i32 %a, i32 %b)
ret i64 %z
}
-; CHECK: = mpy({{.*}}.h, {{.*}}.h):rnd
+; CHECK: = mpy({{.*}}.h,{{.*}}.h):rnd
declare i64 @llvm.hexagon.M2.mpyd.rnd.hh.s1(i32, i32)
define i64 @M2_mpyd_rnd_hh_s1(i32 %a, i32 %b) {
%z = call i64 @llvm.hexagon.M2.mpyd.rnd.hh.s1(i32 %a, i32 %b)
ret i64 %z
}
-; CHECK: = mpy({{.*}}.h, {{.*}}.h):<<1:rnd
+; CHECK: = mpy({{.*}}.h,{{.*}}.h):<<1:rnd
declare i64 @llvm.hexagon.M2.mpyd.acc.ll.s0(i64, i32, i32)
define i64 @M2_mpyd_acc_ll_s0(i64 %a, i32 %b, i32 %c) {
%z = call i64 @llvm.hexagon.M2.mpyd.acc.ll.s0(i64 %a, i32 %b, i32 %c)
ret i64 %z
}
-; CHECK: += mpy({{.*}}.l, {{.*}}.l)
+; CHECK: += mpy({{.*}}.l,{{.*}}.l)
declare i64 @llvm.hexagon.M2.mpyd.acc.ll.s1(i64, i32, i32)
define i64 @M2_mpyd_acc_ll_s1(i64 %a, i32 %b, i32 %c) {
%z = call i64 @llvm.hexagon.M2.mpyd.acc.ll.s1(i64 %a, i32 %b, i32 %c)
ret i64 %z
}
-; CHECK: += mpy({{.*}}.l, {{.*}}.l):<<1
+; CHECK: += mpy({{.*}}.l,{{.*}}.l):<<1
declare i64 @llvm.hexagon.M2.mpyd.acc.lh.s0(i64, i32, i32)
define i64 @M2_mpyd_acc_lh_s0(i64 %a, i32 %b, i32 %c) {
%z = call i64 @llvm.hexagon.M2.mpyd.acc.lh.s0(i64 %a, i32 %b, i32 %c)
ret i64 %z
}
-; CHECK: += mpy({{.*}}.l, {{.*}}.h)
+; CHECK: += mpy({{.*}}.l,{{.*}}.h)
declare i64 @llvm.hexagon.M2.mpyd.acc.lh.s1(i64, i32, i32)
define i64 @M2_mpyd_acc_lh_s1(i64 %a, i32 %b, i32 %c) {
%z = call i64 @llvm.hexagon.M2.mpyd.acc.lh.s1(i64 %a, i32 %b, i32 %c)
ret i64 %z
}
-; CHECK: += mpy({{.*}}.l, {{.*}}.h):<<1
+; CHECK: += mpy({{.*}}.l,{{.*}}.h):<<1
declare i64 @llvm.hexagon.M2.mpyd.acc.hl.s0(i64, i32, i32)
define i64 @M2_mpyd_acc_hl_s0(i64 %a, i32 %b, i32 %c) {
%z = call i64 @llvm.hexagon.M2.mpyd.acc.hl.s0(i64 %a, i32 %b, i32 %c)
ret i64 %z
}
-; CHECK: += mpy({{.*}}.h, {{.*}}.l)
+; CHECK: += mpy({{.*}}.h,{{.*}}.l)
declare i64 @llvm.hexagon.M2.mpyd.acc.hl.s1(i64, i32, i32)
define i64 @M2_mpyd_acc_hl_s1(i64 %a, i32 %b, i32 %c) {
%z = call i64 @llvm.hexagon.M2.mpyd.acc.hl.s1(i64 %a, i32 %b, i32 %c)
ret i64 %z
}
-; CHECK: += mpy({{.*}}.h, {{.*}}.l):<<1
+; CHECK: += mpy({{.*}}.h,{{.*}}.l):<<1
declare i64 @llvm.hexagon.M2.mpyd.acc.hh.s0(i64, i32, i32)
define i64 @M2_mpyd_acc_hh_s0(i64 %a, i32 %b, i32 %c) {
%z = call i64 @llvm.hexagon.M2.mpyd.acc.hh.s0(i64 %a, i32 %b, i32 %c)
ret i64 %z
}
-; CHECK: += mpy({{.*}}.h, {{.*}}.h)
+; CHECK: += mpy({{.*}}.h,{{.*}}.h)
declare i64 @llvm.hexagon.M2.mpyd.acc.hh.s1(i64, i32, i32)
define i64 @M2_mpyd_acc_hh_s1(i64 %a, i32 %b, i32 %c) {
%z = call i64 @llvm.hexagon.M2.mpyd.acc.hh.s1(i64 %a, i32 %b, i32 %c)
ret i64 %z
}
-; CHECK: += mpy({{.*}}.h, {{.*}}.h):<<1
+; CHECK: += mpy({{.*}}.h,{{.*}}.h):<<1
declare i64 @llvm.hexagon.M2.mpyd.nac.ll.s0(i64, i32, i32)
define i64 @M2_mpyd_nac_ll_s0(i64 %a, i32 %b, i32 %c) {
%z = call i64 @llvm.hexagon.M2.mpyd.nac.ll.s0(i64 %a, i32 %b, i32 %c)
ret i64 %z
}
-; CHECK: -= mpy({{.*}}.l, {{.*}}.l)
+; CHECK: -= mpy({{.*}}.l,{{.*}}.l)
declare i64 @llvm.hexagon.M2.mpyd.nac.ll.s1(i64, i32, i32)
define i64 @M2_mpyd_nac_ll_s1(i64 %a, i32 %b, i32 %c) {
%z = call i64 @llvm.hexagon.M2.mpyd.nac.ll.s1(i64 %a, i32 %b, i32 %c)
ret i64 %z
}
-; CHECK: -= mpy({{.*}}.l, {{.*}}.l):<<1
+; CHECK: -= mpy({{.*}}.l,{{.*}}.l):<<1
declare i64 @llvm.hexagon.M2.mpyd.nac.lh.s0(i64, i32, i32)
define i64 @M2_mpyd_nac_lh_s0(i64 %a, i32 %b, i32 %c) {
%z = call i64 @llvm.hexagon.M2.mpyd.nac.lh.s0(i64 %a, i32 %b, i32 %c)
ret i64 %z
}
-; CHECK: -= mpy({{.*}}.l, {{.*}}.h)
+; CHECK: -= mpy({{.*}}.l,{{.*}}.h)
declare i64 @llvm.hexagon.M2.mpyd.nac.lh.s1(i64, i32, i32)
define i64 @M2_mpyd_nac_lh_s1(i64 %a, i32 %b, i32 %c) {
%z = call i64 @llvm.hexagon.M2.mpyd.nac.lh.s1(i64 %a, i32 %b, i32 %c)
ret i64 %z
}
-; CHECK: -= mpy({{.*}}.l, {{.*}}.h):<<1
+; CHECK: -= mpy({{.*}}.l,{{.*}}.h):<<1
declare i64 @llvm.hexagon.M2.mpyd.nac.hl.s0(i64, i32, i32)
define i64 @M2_mpyd_nac_hl_s0(i64 %a, i32 %b, i32 %c) {
%z = call i64 @llvm.hexagon.M2.mpyd.nac.hl.s0(i64 %a, i32 %b, i32 %c)
ret i64 %z
}
-; CHECK: -= mpy({{.*}}.h, {{.*}}.l)
+; CHECK: -= mpy({{.*}}.h,{{.*}}.l)
declare i64 @llvm.hexagon.M2.mpyd.nac.hl.s1(i64, i32, i32)
define i64 @M2_mpyd_nac_hl_s1(i64 %a, i32 %b, i32 %c) {
%z = call i64 @llvm.hexagon.M2.mpyd.nac.hl.s1(i64 %a, i32 %b, i32 %c)
ret i64 %z
}
-; CHECK: -= mpy({{.*}}.h, {{.*}}.l):<<1
+; CHECK: -= mpy({{.*}}.h,{{.*}}.l):<<1
declare i64 @llvm.hexagon.M2.mpyd.nac.hh.s0(i64, i32, i32)
define i64 @M2_mpyd_nac_hh_s0(i64 %a, i32 %b, i32 %c) {
%z = call i64 @llvm.hexagon.M2.mpyd.nac.hh.s0(i64 %a, i32 %b, i32 %c)
ret i64 %z
}
-; CHECK: -= mpy({{.*}}.h, {{.*}}.h)
+; CHECK: -= mpy({{.*}}.h,{{.*}}.h)
declare i64 @llvm.hexagon.M2.mpyd.nac.hh.s1(i64, i32, i32)
define i64 @M2_mpyd_nac_hh_s1(i64 %a, i32 %b, i32 %c) {
%z = call i64 @llvm.hexagon.M2.mpyd.nac.hh.s1(i64 %a, i32 %b, i32 %c)
ret i64 %z
}
-; CHECK: -= mpy({{.*}}.h, {{.*}}.h):<<1
+; CHECK: -= mpy({{.*}}.h,{{.*}}.h):<<1
declare i32 @llvm.hexagon.M2.mpy.ll.s0(i32, i32)
define i32 @M2_mpy_ll_s0(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.M2.mpy.ll.s0(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = mpy({{.*}}.l, {{.*}}.l)
+; CHECK: = mpy({{.*}}.l,{{.*}}.l)
declare i32 @llvm.hexagon.M2.mpy.ll.s1(i32, i32)
define i32 @M2_mpy_ll_s1(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.M2.mpy.ll.s1(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = mpy({{.*}}.l, {{.*}}.l):<<1
+; CHECK: = mpy({{.*}}.l,{{.*}}.l):<<1
declare i32 @llvm.hexagon.M2.mpy.lh.s0(i32, i32)
define i32 @M2_mpy_lh_s0(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.M2.mpy.lh.s0(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = mpy({{.*}}.l, {{.*}}.h)
+; CHECK: = mpy({{.*}}.l,{{.*}}.h)
declare i32 @llvm.hexagon.M2.mpy.lh.s1(i32, i32)
define i32 @M2_mpy_lh_s1(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.M2.mpy.lh.s1(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = mpy({{.*}}.l, {{.*}}.h):<<1
+; CHECK: = mpy({{.*}}.l,{{.*}}.h):<<1
declare i32 @llvm.hexagon.M2.mpy.hl.s0(i32, i32)
define i32 @M2_mpy_hl_s0(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.M2.mpy.hl.s0(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = mpy({{.*}}.h, {{.*}}.l)
+; CHECK: = mpy({{.*}}.h,{{.*}}.l)
declare i32 @llvm.hexagon.M2.mpy.hl.s1(i32, i32)
define i32 @M2_mpy_hl_s1(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.M2.mpy.hl.s1(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = mpy({{.*}}.h, {{.*}}.l):<<1
+; CHECK: = mpy({{.*}}.h,{{.*}}.l):<<1
declare i32 @llvm.hexagon.M2.mpy.hh.s0(i32, i32)
define i32 @M2_mpy_hh_s0(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.M2.mpy.hh.s0(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = mpy({{.*}}.h, {{.*}}.h)
+; CHECK: = mpy({{.*}}.h,{{.*}}.h)
declare i32 @llvm.hexagon.M2.mpy.hh.s1(i32, i32)
define i32 @M2_mpy_hh_s1(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.M2.mpy.hh.s1(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = mpy({{.*}}.h, {{.*}}.h):<<1
+; CHECK: = mpy({{.*}}.h,{{.*}}.h):<<1
declare i32 @llvm.hexagon.M2.mpy.sat.ll.s0(i32, i32)
define i32 @M2_mpy_sat_ll_s0(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.M2.mpy.sat.ll.s0(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = mpy({{.*}}.l, {{.*}}.l):sat
+; CHECK: = mpy({{.*}}.l,{{.*}}.l):sat
declare i32 @llvm.hexagon.M2.mpy.sat.ll.s1(i32, i32)
define i32 @M2_mpy_sat_ll_s1(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.M2.mpy.sat.ll.s1(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = mpy({{.*}}.l, {{.*}}.l):<<1:sat
+; CHECK: = mpy({{.*}}.l,{{.*}}.l):<<1:sat
declare i32 @llvm.hexagon.M2.mpy.sat.lh.s0(i32, i32)
define i32 @M2_mpy_sat_lh_s0(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.M2.mpy.sat.lh.s0(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = mpy({{.*}}.l, {{.*}}.h):sat
+; CHECK: = mpy({{.*}}.l,{{.*}}.h):sat
declare i32 @llvm.hexagon.M2.mpy.sat.lh.s1(i32, i32)
define i32 @M2_mpy_sat_lh_s1(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.M2.mpy.sat.lh.s1(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = mpy({{.*}}.l, {{.*}}.h):<<1:sat
+; CHECK: = mpy({{.*}}.l,{{.*}}.h):<<1:sat
declare i32 @llvm.hexagon.M2.mpy.sat.hl.s0(i32, i32)
define i32 @M2_mpy_sat_hl_s0(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.M2.mpy.sat.hl.s0(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = mpy({{.*}}.h, {{.*}}.l):sat
+; CHECK: = mpy({{.*}}.h,{{.*}}.l):sat
declare i32 @llvm.hexagon.M2.mpy.sat.hl.s1(i32, i32)
define i32 @M2_mpy_sat_hl_s1(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.M2.mpy.sat.hl.s1(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = mpy({{.*}}.h, {{.*}}.l):<<1:sat
+; CHECK: = mpy({{.*}}.h,{{.*}}.l):<<1:sat
declare i32 @llvm.hexagon.M2.mpy.sat.hh.s0(i32, i32)
define i32 @M2_mpy_sat_hh_s0(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.M2.mpy.sat.hh.s0(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = mpy({{.*}}.h, {{.*}}.h):sat
+; CHECK: = mpy({{.*}}.h,{{.*}}.h):sat
declare i32 @llvm.hexagon.M2.mpy.sat.hh.s1(i32, i32)
define i32 @M2_mpy_sat_hh_s1(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.M2.mpy.sat.hh.s1(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = mpy({{.*}}.h, {{.*}}.h):<<1:sat
+; CHECK: = mpy({{.*}}.h,{{.*}}.h):<<1:sat
declare i32 @llvm.hexagon.M2.mpy.sat.rnd.ll.s0(i32, i32)
define i32 @M2_mpy_sat_rnd_ll_s0(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.M2.mpy.sat.rnd.ll.s0(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = mpy({{.*}}.l, {{.*}}.l):rnd:sat
+; CHECK: = mpy({{.*}}.l,{{.*}}.l):rnd:sat
declare i32 @llvm.hexagon.M2.mpy.sat.rnd.ll.s1(i32, i32)
define i32 @M2_mpy_sat_rnd_ll_s1(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.M2.mpy.sat.rnd.ll.s1(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = mpy({{.*}}.l, {{.*}}.l):<<1:rnd:sat
+; CHECK: = mpy({{.*}}.l,{{.*}}.l):<<1:rnd:sat
declare i32 @llvm.hexagon.M2.mpy.sat.rnd.lh.s0(i32, i32)
define i32 @M2_mpy_sat_rnd_lh_s0(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.M2.mpy.sat.rnd.lh.s0(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = mpy({{.*}}.l, {{.*}}.h):rnd:sat
+; CHECK: = mpy({{.*}}.l,{{.*}}.h):rnd:sat
declare i32 @llvm.hexagon.M2.mpy.sat.rnd.lh.s1(i32, i32)
define i32 @M2_mpy_sat_rnd_lh_s1(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.M2.mpy.sat.rnd.lh.s1(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = mpy({{.*}}.l, {{.*}}.h):<<1:rnd:sat
+; CHECK: = mpy({{.*}}.l,{{.*}}.h):<<1:rnd:sat
declare i32 @llvm.hexagon.M2.mpy.sat.rnd.hl.s0(i32, i32)
define i32 @M2_mpy_sat_rnd_hl_s0(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.M2.mpy.sat.rnd.hl.s0(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = mpy({{.*}}.h, {{.*}}.l):rnd:sat
+; CHECK: = mpy({{.*}}.h,{{.*}}.l):rnd:sat
declare i32 @llvm.hexagon.M2.mpy.sat.rnd.hl.s1(i32, i32)
define i32 @M2_mpy_sat_rnd_hl_s1(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.M2.mpy.sat.rnd.hl.s1(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = mpy({{.*}}.h, {{.*}}.l):<<1:rnd:sat
+; CHECK: = mpy({{.*}}.h,{{.*}}.l):<<1:rnd:sat
declare i32 @llvm.hexagon.M2.mpy.sat.rnd.hh.s0(i32, i32)
define i32 @M2_mpy_sat_rnd_hh_s0(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.M2.mpy.sat.rnd.hh.s0(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = mpy({{.*}}.h, {{.*}}.h):rnd:sat
+; CHECK: = mpy({{.*}}.h,{{.*}}.h):rnd:sat
declare i32 @llvm.hexagon.M2.mpy.sat.rnd.hh.s1(i32, i32)
define i32 @M2_mpy_sat_rnd_hh_s1(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.M2.mpy.sat.rnd.hh.s1(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = mpy({{.*}}.h, {{.*}}.h):<<1:rnd:sat
+; CHECK: = mpy({{.*}}.h,{{.*}}.h):<<1:rnd:sat
declare i32 @llvm.hexagon.M2.mpy.acc.ll.s0(i32, i32, i32)
define i32 @M2_mpy_acc_ll_s0(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M2.mpy.acc.ll.s0(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: += mpy({{.*}}.l, {{.*}}.l)
+; CHECK: += mpy({{.*}}.l,{{.*}}.l)
declare i32 @llvm.hexagon.M2.mpy.acc.ll.s1(i32, i32, i32)
define i32 @M2_mpy_acc_ll_s1(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M2.mpy.acc.ll.s1(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: += mpy({{.*}}.l, {{.*}}.l):<<1
+; CHECK: += mpy({{.*}}.l,{{.*}}.l):<<1
declare i32 @llvm.hexagon.M2.mpy.acc.lh.s0(i32, i32, i32)
define i32 @M2_mpy_acc_lh_s0(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M2.mpy.acc.lh.s0(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: += mpy({{.*}}.l, {{.*}}.h)
+; CHECK: += mpy({{.*}}.l,{{.*}}.h)
declare i32 @llvm.hexagon.M2.mpy.acc.lh.s1(i32, i32, i32)
define i32 @M2_mpy_acc_lh_s1(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M2.mpy.acc.lh.s1(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: += mpy({{.*}}.l, {{.*}}.h):<<1
+; CHECK: += mpy({{.*}}.l,{{.*}}.h):<<1
declare i32 @llvm.hexagon.M2.mpy.acc.hl.s0(i32, i32, i32)
define i32 @M2_mpy_acc_hl_s0(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M2.mpy.acc.hl.s0(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: += mpy({{.*}}.h, {{.*}}.l)
+; CHECK: += mpy({{.*}}.h,{{.*}}.l)
declare i32 @llvm.hexagon.M2.mpy.acc.hl.s1(i32, i32, i32)
define i32 @M2_mpy_acc_hl_s1(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M2.mpy.acc.hl.s1(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: += mpy({{.*}}.h, {{.*}}.l):<<1
+; CHECK: += mpy({{.*}}.h,{{.*}}.l):<<1
declare i32 @llvm.hexagon.M2.mpy.acc.hh.s0(i32, i32, i32)
define i32 @M2_mpy_acc_hh_s0(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M2.mpy.acc.hh.s0(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: += mpy({{.*}}.h, {{.*}}.h)
+; CHECK: += mpy({{.*}}.h,{{.*}}.h)
declare i32 @llvm.hexagon.M2.mpy.acc.hh.s1(i32, i32, i32)
define i32 @M2_mpy_acc_hh_s1(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M2.mpy.acc.hh.s1(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: += mpy({{.*}}.h, {{.*}}.h):<<1
+; CHECK: += mpy({{.*}}.h,{{.*}}.h):<<1
declare i32 @llvm.hexagon.M2.mpy.acc.sat.ll.s0(i32, i32, i32)
define i32 @M2_mpy_acc_sat_ll_s0(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M2.mpy.acc.sat.ll.s0(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: += mpy({{.*}}.l, {{.*}}.l):sat
+; CHECK: += mpy({{.*}}.l,{{.*}}.l):sat
declare i32 @llvm.hexagon.M2.mpy.acc.sat.ll.s1(i32, i32, i32)
define i32 @M2_mpy_acc_sat_ll_s1(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M2.mpy.acc.sat.ll.s1(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: += mpy({{.*}}.l, {{.*}}.l):<<1:sat
+; CHECK: += mpy({{.*}}.l,{{.*}}.l):<<1:sat
declare i32 @llvm.hexagon.M2.mpy.acc.sat.lh.s0(i32, i32, i32)
define i32 @M2_mpy_acc_sat_lh_s0(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M2.mpy.acc.sat.lh.s0(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: += mpy({{.*}}.l, {{.*}}.h):sat
+; CHECK: += mpy({{.*}}.l,{{.*}}.h):sat
declare i32 @llvm.hexagon.M2.mpy.acc.sat.lh.s1(i32, i32, i32)
define i32 @M2_mpy_acc_sat_lh_s1(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M2.mpy.acc.sat.lh.s1(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: += mpy({{.*}}.l, {{.*}}.h):<<1:sat
+; CHECK: += mpy({{.*}}.l,{{.*}}.h):<<1:sat
declare i32 @llvm.hexagon.M2.mpy.acc.sat.hl.s0(i32, i32, i32)
define i32 @M2_mpy_acc_sat_hl_s0(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M2.mpy.acc.sat.hl.s0(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: += mpy({{.*}}.h, {{.*}}.l):sat
+; CHECK: += mpy({{.*}}.h,{{.*}}.l):sat
declare i32 @llvm.hexagon.M2.mpy.acc.sat.hl.s1(i32, i32, i32)
define i32 @M2_mpy_acc_sat_hl_s1(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M2.mpy.acc.sat.hl.s1(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: += mpy({{.*}}.h, {{.*}}.l):<<1:sat
+; CHECK: += mpy({{.*}}.h,{{.*}}.l):<<1:sat
declare i32 @llvm.hexagon.M2.mpy.acc.sat.hh.s0(i32, i32, i32)
define i32 @M2_mpy_acc_sat_hh_s0(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M2.mpy.acc.sat.hh.s0(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: += mpy({{.*}}.h, {{.*}}.h):sat
+; CHECK: += mpy({{.*}}.h,{{.*}}.h):sat
declare i32 @llvm.hexagon.M2.mpy.acc.sat.hh.s1(i32, i32, i32)
define i32 @M2_mpy_acc_sat_hh_s1(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M2.mpy.acc.sat.hh.s1(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: += mpy({{.*}}.h, {{.*}}.h):<<1:sat
+; CHECK: += mpy({{.*}}.h,{{.*}}.h):<<1:sat
declare i32 @llvm.hexagon.M2.mpy.nac.ll.s0(i32, i32, i32)
define i32 @M2_mpy_nac_ll_s0(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M2.mpy.nac.ll.s0(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: -= mpy({{.*}}.l, {{.*}}.l)
+; CHECK: -= mpy({{.*}}.l,{{.*}}.l)
declare i32 @llvm.hexagon.M2.mpy.nac.ll.s1(i32, i32, i32)
define i32 @M2_mpy_nac_ll_s1(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M2.mpy.nac.ll.s1(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: -= mpy({{.*}}.l, {{.*}}.l):<<1
+; CHECK: -= mpy({{.*}}.l,{{.*}}.l):<<1
declare i32 @llvm.hexagon.M2.mpy.nac.lh.s0(i32, i32, i32)
define i32 @M2_mpy_nac_lh_s0(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M2.mpy.nac.lh.s0(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: -= mpy({{.*}}.l, {{.*}}.h)
+; CHECK: -= mpy({{.*}}.l,{{.*}}.h)
declare i32 @llvm.hexagon.M2.mpy.nac.lh.s1(i32, i32, i32)
define i32 @M2_mpy_nac_lh_s1(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M2.mpy.nac.lh.s1(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: -= mpy({{.*}}.l, {{.*}}.h):<<1
+; CHECK: -= mpy({{.*}}.l,{{.*}}.h):<<1
declare i32 @llvm.hexagon.M2.mpy.nac.hl.s0(i32, i32, i32)
define i32 @M2_mpy_nac_hl_s0(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M2.mpy.nac.hl.s0(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: -= mpy({{.*}}.h, {{.*}}.l)
+; CHECK: -= mpy({{.*}}.h,{{.*}}.l)
declare i32 @llvm.hexagon.M2.mpy.nac.hl.s1(i32, i32, i32)
define i32 @M2_mpy_nac_hl_s1(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M2.mpy.nac.hl.s1(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: -= mpy({{.*}}.h, {{.*}}.l):<<1
+; CHECK: -= mpy({{.*}}.h,{{.*}}.l):<<1
declare i32 @llvm.hexagon.M2.mpy.nac.hh.s0(i32, i32, i32)
define i32 @M2_mpy_nac_hh_s0(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M2.mpy.nac.hh.s0(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: -= mpy({{.*}}.h, {{.*}}.h)
+; CHECK: -= mpy({{.*}}.h,{{.*}}.h)
declare i32 @llvm.hexagon.M2.mpy.nac.hh.s1(i32, i32, i32)
define i32 @M2_mpy_nac_hh_s1(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M2.mpy.nac.hh.s1(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: -= mpy({{.*}}.h, {{.*}}.h):<<1
+; CHECK: -= mpy({{.*}}.h,{{.*}}.h):<<1
declare i32 @llvm.hexagon.M2.mpy.nac.sat.ll.s0(i32, i32, i32)
define i32 @M2_mpy_nac_sat_ll_s0(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M2.mpy.nac.sat.ll.s0(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: -= mpy({{.*}}.l, {{.*}}.l):sat
+; CHECK: -= mpy({{.*}}.l,{{.*}}.l):sat
declare i32 @llvm.hexagon.M2.mpy.nac.sat.ll.s1(i32, i32, i32)
define i32 @M2_mpy_nac_sat_ll_s1(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M2.mpy.nac.sat.ll.s1(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: -= mpy({{.*}}.l, {{.*}}.l):<<1:sat
+; CHECK: -= mpy({{.*}}.l,{{.*}}.l):<<1:sat
declare i32 @llvm.hexagon.M2.mpy.nac.sat.lh.s0(i32, i32, i32)
define i32 @M2_mpy_nac_sat_lh_s0(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M2.mpy.nac.sat.lh.s0(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: -= mpy({{.*}}.l, {{.*}}.h):sat
+; CHECK: -= mpy({{.*}}.l,{{.*}}.h):sat
declare i32 @llvm.hexagon.M2.mpy.nac.sat.lh.s1(i32, i32, i32)
define i32 @M2_mpy_nac_sat_lh_s1(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M2.mpy.nac.sat.lh.s1(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: -= mpy({{.*}}.l, {{.*}}.h):<<1:sat
+; CHECK: -= mpy({{.*}}.l,{{.*}}.h):<<1:sat
declare i32 @llvm.hexagon.M2.mpy.nac.sat.hl.s0(i32, i32, i32)
define i32 @M2_mpy_nac_sat_hl_s0(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M2.mpy.nac.sat.hl.s0(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: -= mpy({{.*}}.h, {{.*}}.l):sat
+; CHECK: -= mpy({{.*}}.h,{{.*}}.l):sat
declare i32 @llvm.hexagon.M2.mpy.nac.sat.hl.s1(i32, i32, i32)
define i32 @M2_mpy_nac_sat_hl_s1(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M2.mpy.nac.sat.hl.s1(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: -= mpy({{.*}}.h, {{.*}}.l):<<1:sat
+; CHECK: -= mpy({{.*}}.h,{{.*}}.l):<<1:sat
declare i32 @llvm.hexagon.M2.mpy.nac.sat.hh.s0(i32, i32, i32)
define i32 @M2_mpy_nac_sat_hh_s0(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M2.mpy.nac.sat.hh.s0(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: -= mpy({{.*}}.h, {{.*}}.h):sat
+; CHECK: -= mpy({{.*}}.h,{{.*}}.h):sat
declare i32 @llvm.hexagon.M2.mpy.nac.sat.hh.s1(i32, i32, i32)
define i32 @M2_mpy_nac_sat_hh_s1(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M2.mpy.nac.sat.hh.s1(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: -= mpy({{.*}}.h, {{.*}}.h):<<1:sat
+; CHECK: -= mpy({{.*}}.h,{{.*}}.h):<<1:sat
; Multiply unsigned halfwords
declare i64 @llvm.hexagon.M2.mpyud.ll.s0(i32, i32)
@@ -778,336 +778,336 @@ define i64 @M2_mpyud_ll_s0(i32 %a, i32 %
%z = call i64 @llvm.hexagon.M2.mpyud.ll.s0(i32 %a, i32 %b)
ret i64 %z
}
-; CHECK: = mpyu({{.*}}.l, {{.*}}.l)
+; CHECK: = mpyu({{.*}}.l,{{.*}}.l)
declare i64 @llvm.hexagon.M2.mpyud.ll.s1(i32, i32)
define i64 @M2_mpyud_ll_s1(i32 %a, i32 %b) {
%z = call i64 @llvm.hexagon.M2.mpyud.ll.s1(i32 %a, i32 %b)
ret i64 %z
}
-; CHECK: = mpyu({{.*}}.l, {{.*}}.l):<<1
+; CHECK: = mpyu({{.*}}.l,{{.*}}.l):<<1
declare i64 @llvm.hexagon.M2.mpyud.lh.s0(i32, i32)
define i64 @M2_mpyud_lh_s0(i32 %a, i32 %b) {
%z = call i64 @llvm.hexagon.M2.mpyud.lh.s0(i32 %a, i32 %b)
ret i64 %z
}
-; CHECK: = mpyu({{.*}}.l, {{.*}}.h)
+; CHECK: = mpyu({{.*}}.l,{{.*}}.h)
declare i64 @llvm.hexagon.M2.mpyud.lh.s1(i32, i32)
define i64 @M2_mpyud_lh_s1(i32 %a, i32 %b) {
%z = call i64 @llvm.hexagon.M2.mpyud.lh.s1(i32 %a, i32 %b)
ret i64 %z
}
-; CHECK: = mpyu({{.*}}.l, {{.*}}.h):<<1
+; CHECK: = mpyu({{.*}}.l,{{.*}}.h):<<1
declare i64 @llvm.hexagon.M2.mpyud.hl.s0(i32, i32)
define i64 @M2_mpyud_hl_s0(i32 %a, i32 %b) {
%z = call i64 @llvm.hexagon.M2.mpyud.hl.s0(i32 %a, i32 %b)
ret i64 %z
}
-; CHECK: = mpyu({{.*}}.h, {{.*}}.l)
+; CHECK: = mpyu({{.*}}.h,{{.*}}.l)
declare i64 @llvm.hexagon.M2.mpyud.hl.s1(i32, i32)
define i64 @M2_mpyud_hl_s1(i32 %a, i32 %b) {
%z = call i64 @llvm.hexagon.M2.mpyud.hl.s1(i32 %a, i32 %b)
ret i64 %z
}
-; CHECK: = mpyu({{.*}}.h, {{.*}}.l):<<1
+; CHECK: = mpyu({{.*}}.h,{{.*}}.l):<<1
declare i64 @llvm.hexagon.M2.mpyud.hh.s0(i32, i32)
define i64 @M2_mpyud_hh_s0(i32 %a, i32 %b) {
%z = call i64 @llvm.hexagon.M2.mpyud.hh.s0(i32 %a, i32 %b)
ret i64 %z
}
-; CHECK: = mpyu({{.*}}.h, {{.*}}.h)
+; CHECK: = mpyu({{.*}}.h,{{.*}}.h)
declare i64 @llvm.hexagon.M2.mpyud.hh.s1(i32, i32)
define i64 @M2_mpyud_hh_s1(i32 %a, i32 %b) {
%z = call i64 @llvm.hexagon.M2.mpyud.hh.s1(i32 %a, i32 %b)
ret i64 %z
}
-; CHECK: = mpyu({{.*}}.h, {{.*}}.h):<<1
+; CHECK: = mpyu({{.*}}.h,{{.*}}.h):<<1
declare i64 @llvm.hexagon.M2.mpyud.acc.ll.s0(i64, i32, i32)
define i64 @M2_mpyud_acc_ll_s0(i64 %a, i32 %b, i32 %c) {
%z = call i64 @llvm.hexagon.M2.mpyud.acc.ll.s0(i64 %a, i32 %b, i32 %c)
ret i64 %z
}
-; CHECK: += mpyu({{.*}}.l, {{.*}}.l)
+; CHECK: += mpyu({{.*}}.l,{{.*}}.l)
declare i64 @llvm.hexagon.M2.mpyud.acc.ll.s1(i64, i32, i32)
define i64 @M2_mpyud_acc_ll_s1(i64 %a, i32 %b, i32 %c) {
%z = call i64 @llvm.hexagon.M2.mpyud.acc.ll.s1(i64 %a, i32 %b, i32 %c)
ret i64 %z
}
-; CHECK: += mpyu({{.*}}.l, {{.*}}.l):<<1
+; CHECK: += mpyu({{.*}}.l,{{.*}}.l):<<1
declare i64 @llvm.hexagon.M2.mpyud.acc.lh.s0(i64, i32, i32)
define i64 @M2_mpyud_acc_lh_s0(i64 %a, i32 %b, i32 %c) {
%z = call i64 @llvm.hexagon.M2.mpyud.acc.lh.s0(i64 %a, i32 %b, i32 %c)
ret i64 %z
}
-; CHECK: += mpyu({{.*}}.l, {{.*}}.h)
+; CHECK: += mpyu({{.*}}.l,{{.*}}.h)
declare i64 @llvm.hexagon.M2.mpyud.acc.lh.s1(i64, i32, i32)
define i64 @M2_mpyud_acc_lh_s1(i64 %a, i32 %b, i32 %c) {
%z = call i64 @llvm.hexagon.M2.mpyud.acc.lh.s1(i64 %a, i32 %b, i32 %c)
ret i64 %z
}
-; CHECK: += mpyu({{.*}}.l, {{.*}}.h):<<1
+; CHECK: += mpyu({{.*}}.l,{{.*}}.h):<<1
declare i64 @llvm.hexagon.M2.mpyud.acc.hl.s0(i64, i32, i32)
define i64 @M2_mpyud_acc_hl_s0(i64 %a, i32 %b, i32 %c) {
%z = call i64 @llvm.hexagon.M2.mpyud.acc.hl.s0(i64 %a, i32 %b, i32 %c)
ret i64 %z
}
-; CHECK: += mpyu({{.*}}.h, {{.*}}.l)
+; CHECK: += mpyu({{.*}}.h,{{.*}}.l)
declare i64 @llvm.hexagon.M2.mpyud.acc.hl.s1(i64, i32, i32)
define i64 @M2_mpyud_acc_hl_s1(i64 %a, i32 %b, i32 %c) {
%z = call i64 @llvm.hexagon.M2.mpyud.acc.hl.s1(i64 %a, i32 %b, i32 %c)
ret i64 %z
}
-; CHECK: += mpyu({{.*}}.h, {{.*}}.l):<<1
+; CHECK: += mpyu({{.*}}.h,{{.*}}.l):<<1
declare i64 @llvm.hexagon.M2.mpyud.acc.hh.s0(i64, i32, i32)
define i64 @M2_mpyud_acc_hh_s0(i64 %a, i32 %b, i32 %c) {
%z = call i64 @llvm.hexagon.M2.mpyud.acc.hh.s0(i64 %a, i32 %b, i32 %c)
ret i64 %z
}
-; CHECK: += mpyu({{.*}}.h, {{.*}}.h)
+; CHECK: += mpyu({{.*}}.h,{{.*}}.h)
declare i64 @llvm.hexagon.M2.mpyud.acc.hh.s1(i64, i32, i32)
define i64 @M2_mpyud_acc_hh_s1(i64 %a, i32 %b, i32 %c) {
%z = call i64 @llvm.hexagon.M2.mpyud.acc.hh.s1(i64 %a, i32 %b, i32 %c)
ret i64 %z
}
-; CHECK: += mpyu({{.*}}.h, {{.*}}.h):<<1
+; CHECK: += mpyu({{.*}}.h,{{.*}}.h):<<1
declare i64 @llvm.hexagon.M2.mpyud.nac.ll.s0(i64, i32, i32)
define i64 @M2_mpyud_nac_ll_s0(i64 %a, i32 %b, i32 %c) {
%z = call i64 @llvm.hexagon.M2.mpyud.nac.ll.s0(i64 %a, i32 %b, i32 %c)
ret i64 %z
}
-; CHECK: -= mpyu({{.*}}.l, {{.*}}.l)
+; CHECK: -= mpyu({{.*}}.l,{{.*}}.l)
declare i64 @llvm.hexagon.M2.mpyud.nac.ll.s1(i64, i32, i32)
define i64 @M2_mpyud_nac_ll_s1(i64 %a, i32 %b, i32 %c) {
%z = call i64 @llvm.hexagon.M2.mpyud.nac.ll.s1(i64 %a, i32 %b, i32 %c)
ret i64 %z
}
-; CHECK: -= mpyu({{.*}}.l, {{.*}}.l):<<1
+; CHECK: -= mpyu({{.*}}.l,{{.*}}.l):<<1
declare i64 @llvm.hexagon.M2.mpyud.nac.lh.s0(i64, i32, i32)
define i64 @M2_mpyud_nac_lh_s0(i64 %a, i32 %b, i32 %c) {
%z = call i64 @llvm.hexagon.M2.mpyud.nac.lh.s0(i64 %a, i32 %b, i32 %c)
ret i64 %z
}
-; CHECK: -= mpyu({{.*}}.l, {{.*}}.h)
+; CHECK: -= mpyu({{.*}}.l,{{.*}}.h)
declare i64 @llvm.hexagon.M2.mpyud.nac.lh.s1(i64, i32, i32)
define i64 @M2_mpyud_nac_lh_s1(i64 %a, i32 %b, i32 %c) {
%z = call i64 @llvm.hexagon.M2.mpyud.nac.lh.s1(i64 %a, i32 %b, i32 %c)
ret i64 %z
}
-; CHECK: -= mpyu({{.*}}.l, {{.*}}.h):<<1
+; CHECK: -= mpyu({{.*}}.l,{{.*}}.h):<<1
declare i64 @llvm.hexagon.M2.mpyud.nac.hl.s0(i64, i32, i32)
define i64 @M2_mpyud_nac_hl_s0(i64 %a, i32 %b, i32 %c) {
%z = call i64 @llvm.hexagon.M2.mpyud.nac.hl.s0(i64 %a, i32 %b, i32 %c)
ret i64 %z
}
-; CHECK: -= mpyu({{.*}}.h, {{.*}}.l)
+; CHECK: -= mpyu({{.*}}.h,{{.*}}.l)
declare i64 @llvm.hexagon.M2.mpyud.nac.hl.s1(i64, i32, i32)
define i64 @M2_mpyud_nac_hl_s1(i64 %a, i32 %b, i32 %c) {
%z = call i64 @llvm.hexagon.M2.mpyud.nac.hl.s1(i64 %a, i32 %b, i32 %c)
ret i64 %z
}
-; CHECK: -= mpyu({{.*}}.h, {{.*}}.l):<<1
+; CHECK: -= mpyu({{.*}}.h,{{.*}}.l):<<1
declare i64 @llvm.hexagon.M2.mpyud.nac.hh.s0(i64, i32, i32)
define i64 @M2_mpyud_nac_hh_s0(i64 %a, i32 %b, i32 %c) {
%z = call i64 @llvm.hexagon.M2.mpyud.nac.hh.s0(i64 %a, i32 %b, i32 %c)
ret i64 %z
}
-; CHECK: -= mpyu({{.*}}.h, {{.*}}.h)
+; CHECK: -= mpyu({{.*}}.h,{{.*}}.h)
declare i64 @llvm.hexagon.M2.mpyud.nac.hh.s1(i64, i32, i32)
define i64 @M2_mpyud_nac_hh_s1(i64 %a, i32 %b, i32 %c) {
%z = call i64 @llvm.hexagon.M2.mpyud.nac.hh.s1(i64 %a, i32 %b, i32 %c)
ret i64 %z
}
-; CHECK: -= mpyu({{.*}}.h, {{.*}}.h):<<1
+; CHECK: -= mpyu({{.*}}.h,{{.*}}.h):<<1
declare i32 @llvm.hexagon.M2.mpyu.ll.s0(i32, i32)
define i32 @M2_mpyu_ll_s0(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.M2.mpyu.ll.s0(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = mpyu({{.*}}.l, {{.*}}.l)
+; CHECK: = mpyu({{.*}}.l,{{.*}}.l)
declare i32 @llvm.hexagon.M2.mpyu.ll.s1(i32, i32)
define i32 @M2_mpyu_ll_s1(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.M2.mpyu.ll.s1(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = mpyu({{.*}}.l, {{.*}}.l):<<1
+; CHECK: = mpyu({{.*}}.l,{{.*}}.l):<<1
declare i32 @llvm.hexagon.M2.mpyu.lh.s0(i32, i32)
define i32 @M2_mpyu_lh_s0(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.M2.mpyu.lh.s0(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = mpyu({{.*}}.l, {{.*}}.h)
+; CHECK: = mpyu({{.*}}.l,{{.*}}.h)
declare i32 @llvm.hexagon.M2.mpyu.lh.s1(i32, i32)
define i32 @M2_mpyu_lh_s1(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.M2.mpyu.lh.s1(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = mpyu({{.*}}.l, {{.*}}.h):<<1
+; CHECK: = mpyu({{.*}}.l,{{.*}}.h):<<1
declare i32 @llvm.hexagon.M2.mpyu.hl.s0(i32, i32)
define i32 @M2_mpyu_hl_s0(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.M2.mpyu.hl.s0(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = mpyu({{.*}}.h, {{.*}}.l)
+; CHECK: = mpyu({{.*}}.h,{{.*}}.l)
declare i32 @llvm.hexagon.M2.mpyu.hl.s1(i32, i32)
define i32 @M2_mpyu_hl_s1(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.M2.mpyu.hl.s1(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = mpyu({{.*}}.h, {{.*}}.l):<<1
+; CHECK: = mpyu({{.*}}.h,{{.*}}.l):<<1
declare i32 @llvm.hexagon.M2.mpyu.hh.s0(i32, i32)
define i32 @M2_mpyu_hh_s0(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.M2.mpyu.hh.s0(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = mpyu({{.*}}.h, {{.*}}.h)
+; CHECK: = mpyu({{.*}}.h,{{.*}}.h)
declare i32 @llvm.hexagon.M2.mpyu.hh.s1(i32, i32)
define i32 @M2_mpyu_hh_s1(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.M2.mpyu.hh.s1(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = mpyu({{.*}}.h, {{.*}}.h):<<1
+; CHECK: = mpyu({{.*}}.h,{{.*}}.h):<<1
declare i32 @llvm.hexagon.M2.mpyu.acc.ll.s0(i32, i32, i32)
define i32 @M2_mpyu_acc_ll_s0(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M2.mpyu.acc.ll.s0(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: += mpyu({{.*}}.l, {{.*}}.l)
+; CHECK: += mpyu({{.*}}.l,{{.*}}.l)
declare i32 @llvm.hexagon.M2.mpyu.acc.ll.s1(i32, i32, i32)
define i32 @M2_mpyu_acc_ll_s1(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M2.mpyu.acc.ll.s1(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: += mpyu({{.*}}.l, {{.*}}.l):<<1
+; CHECK: += mpyu({{.*}}.l,{{.*}}.l):<<1
declare i32 @llvm.hexagon.M2.mpyu.acc.lh.s0(i32, i32, i32)
define i32 @M2_mpyu_acc_lh_s0(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M2.mpyu.acc.lh.s0(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: += mpyu({{.*}}.l, {{.*}}.h)
+; CHECK: += mpyu({{.*}}.l,{{.*}}.h)
declare i32 @llvm.hexagon.M2.mpyu.acc.lh.s1(i32, i32, i32)
define i32 @M2_mpyu_acc_lh_s1(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M2.mpyu.acc.lh.s1(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: += mpyu({{.*}}.l, {{.*}}.h):<<1
+; CHECK: += mpyu({{.*}}.l,{{.*}}.h):<<1
declare i32 @llvm.hexagon.M2.mpyu.acc.hl.s0(i32, i32, i32)
define i32 @M2_mpyu_acc_hl_s0(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M2.mpyu.acc.hl.s0(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: += mpyu({{.*}}.h, {{.*}}.l)
+; CHECK: += mpyu({{.*}}.h,{{.*}}.l)
declare i32 @llvm.hexagon.M2.mpyu.acc.hl.s1(i32, i32, i32)
define i32 @M2_mpyu_acc_hl_s1(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M2.mpyu.acc.hl.s1(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: += mpyu({{.*}}.h, {{.*}}.l):<<1
+; CHECK: += mpyu({{.*}}.h,{{.*}}.l):<<1
declare i32 @llvm.hexagon.M2.mpyu.acc.hh.s0(i32, i32, i32)
define i32 @M2_mpyu_acc_hh_s0(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M2.mpyu.acc.hh.s0(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: += mpyu({{.*}}.h, {{.*}}.h)
+; CHECK: += mpyu({{.*}}.h,{{.*}}.h)
declare i32 @llvm.hexagon.M2.mpyu.acc.hh.s1(i32, i32, i32)
define i32 @M2_mpyu_acc_hh_s1(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M2.mpyu.acc.hh.s1(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: += mpyu({{.*}}.h, {{.*}}.h):<<1
+; CHECK: += mpyu({{.*}}.h,{{.*}}.h):<<1
declare i32 @llvm.hexagon.M2.mpyu.nac.ll.s0(i32, i32, i32)
define i32 @M2_mpyu_nac_ll_s0(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M2.mpyu.nac.ll.s0(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: -= mpyu({{.*}}.l, {{.*}}.l)
+; CHECK: -= mpyu({{.*}}.l,{{.*}}.l)
declare i32 @llvm.hexagon.M2.mpyu.nac.ll.s1(i32, i32, i32)
define i32 @M2_mpyu_nac_ll_s1(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M2.mpyu.nac.ll.s1(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: -= mpyu({{.*}}.l, {{.*}}.l):<<1
+; CHECK: -= mpyu({{.*}}.l,{{.*}}.l):<<1
declare i32 @llvm.hexagon.M2.mpyu.nac.lh.s0(i32, i32, i32)
define i32 @M2_mpyu_nac_lh_s0(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M2.mpyu.nac.lh.s0(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: -= mpyu({{.*}}.l, {{.*}}.h)
+; CHECK: -= mpyu({{.*}}.l,{{.*}}.h)
declare i32 @llvm.hexagon.M2.mpyu.nac.lh.s1(i32, i32, i32)
define i32 @M2_mpyu_nac_lh_s1(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M2.mpyu.nac.lh.s1(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: -= mpyu({{.*}}.l, {{.*}}.h):<<1
+; CHECK: -= mpyu({{.*}}.l,{{.*}}.h):<<1
declare i32 @llvm.hexagon.M2.mpyu.nac.hl.s0(i32, i32, i32)
define i32 @M2_mpyu_nac_hl_s0(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M2.mpyu.nac.hl.s0(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: -= mpyu({{.*}}.h, {{.*}}.l)
+; CHECK: -= mpyu({{.*}}.h,{{.*}}.l)
declare i32 @llvm.hexagon.M2.mpyu.nac.hl.s1(i32, i32, i32)
define i32 @M2_mpyu_nac_hl_s1(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M2.mpyu.nac.hl.s1(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: -= mpyu({{.*}}.h, {{.*}}.l):<<1
+; CHECK: -= mpyu({{.*}}.h,{{.*}}.l):<<1
declare i32 @llvm.hexagon.M2.mpyu.nac.hh.s0(i32, i32, i32)
define i32 @M2_mpyu_nac_hh_s0(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M2.mpyu.nac.hh.s0(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: -= mpyu({{.*}}.h, {{.*}}.h)
+; CHECK: -= mpyu({{.*}}.h,{{.*}}.h)
declare i32 @llvm.hexagon.M2.mpyu.nac.hh.s1(i32, i32, i32)
define i32 @M2_mpyu_nac_hh_s1(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M2.mpyu.nac.hh.s1(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: -= mpyu({{.*}}.h, {{.*}}.h):<<1
+; CHECK: -= mpyu({{.*}}.h,{{.*}}.h):<<1
; Polynomial multiply words
declare i64 @llvm.hexagon.M4.pmpyw(i32, i32)
@@ -1115,14 +1115,14 @@ define i64 @M4_pmpyw(i32 %a, i32 %b) {
%z = call i64 @llvm.hexagon.M4.pmpyw(i32 %a, i32 %b)
ret i64 %z
}
-; CHECK: = pmpyw({{.*}}, {{.*}})
+; CHECK: = pmpyw({{.*}},{{.*}})
declare i64 @llvm.hexagon.M4.pmpyw.acc(i64, i32, i32)
define i64 @M4_pmpyw_acc(i64 %a, i32 %b, i32 %c) {
%z = call i64 @llvm.hexagon.M4.pmpyw.acc(i64 %a, i32 %b, i32 %c)
ret i64 %z
}
-; CHECK: ^= pmpyw({{.*}}, {{.*}})
+; CHECK: ^= pmpyw({{.*}},{{.*}})
; Vector reduce multiply word by signed half
declare i64 @llvm.hexagon.M4.vrmpyoh.s0(i64, i64)
@@ -1130,56 +1130,56 @@ define i64 @M4_vrmpyoh_s0(i64 %a, i64 %b
%z = call i64 @llvm.hexagon.M4.vrmpyoh.s0(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vrmpywoh({{.*}}, {{.*}})
+; CHECK: = vrmpywoh({{.*}},{{.*}})
declare i64 @llvm.hexagon.M4.vrmpyoh.s1(i64, i64)
define i64 @M4_vrmpyoh_s1(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.M4.vrmpyoh.s1(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vrmpywoh({{.*}}, {{.*}}):<<1
+; CHECK: = vrmpywoh({{.*}},{{.*}}):<<1
declare i64 @llvm.hexagon.M4.vrmpyeh.s0(i64, i64)
define i64 @M4_vrmpyeh_s0(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.M4.vrmpyeh.s0(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vrmpyweh({{.*}}, {{.*}})
+; CHECK: = vrmpyweh({{.*}},{{.*}})
declare i64 @llvm.hexagon.M4.vrmpyeh.s1(i64, i64)
define i64 @M4_vrmpyeh_s1(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.M4.vrmpyeh.s1(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vrmpyweh({{.*}}, {{.*}}):<<1
+; CHECK: = vrmpyweh({{.*}},{{.*}}):<<1
declare i64 @llvm.hexagon.M4.vrmpyoh.acc.s0(i64, i64, i64)
define i64 @M4_vrmpyoh_acc_s0(i64 %a, i64 %b, i64 %c) {
%z = call i64 @llvm.hexagon.M4.vrmpyoh.acc.s0(i64 %a, i64 %b, i64 %c)
ret i64 %z
}
-; CHECK: += vrmpywoh({{.*}}, r5:4)
+; CHECK: += vrmpywoh({{.*}},r5:4)
declare i64 @llvm.hexagon.M4.vrmpyoh.acc.s1(i64, i64, i64)
define i64 @M4_vrmpyoh_acc_s1(i64 %a, i64 %b, i64 %c) {
%z = call i64 @llvm.hexagon.M4.vrmpyoh.acc.s1(i64 %a, i64 %b, i64 %c)
ret i64 %z
}
-; CHECK: += vrmpywoh({{.*}}, r5:4):<<1
+; CHECK: += vrmpywoh({{.*}},r5:4):<<1
declare i64 @llvm.hexagon.M4.vrmpyeh.acc.s0(i64, i64, i64)
define i64 @M4_vrmpyeh_acc_s0(i64 %a, i64 %b, i64 %c) {
%z = call i64 @llvm.hexagon.M4.vrmpyeh.acc.s0(i64 %a, i64 %b, i64 %c)
ret i64 %z
}
-; CHECK: += vrmpyweh({{.*}}, r5:4)
+; CHECK: += vrmpyweh({{.*}},r5:4)
declare i64 @llvm.hexagon.M4.vrmpyeh.acc.s1(i64, i64, i64)
define i64 @M4_vrmpyeh_acc_s1(i64 %a, i64 %b, i64 %c) {
%z = call i64 @llvm.hexagon.M4.vrmpyeh.acc.s1(i64 %a, i64 %b, i64 %c)
ret i64 %z
}
-; CHECK: += vrmpyweh({{.*}}, r5:4):<<1
+; CHECK: += vrmpyweh({{.*}},r5:4):<<1
; Multiply and use upper result
declare i32 @llvm.hexagon.M2.dpmpyss.rnd.s0(i32, i32)
@@ -1187,84 +1187,84 @@ define i32 @M2_dpmpyss_rnd_s0(i32 %a, i3
%z = call i32 @llvm.hexagon.M2.dpmpyss.rnd.s0(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = mpy({{.*}}, {{.*}}):rnd
+; CHECK: = mpy({{.*}},{{.*}}):rnd
declare i32 @llvm.hexagon.M2.mpyu.up(i32, i32)
define i32 @M2_mpyu_up(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.M2.mpyu.up(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = mpyu({{.*}}, {{.*}})
+; CHECK: = mpyu({{.*}},{{.*}})
declare i32 @llvm.hexagon.M2.mpysu.up(i32, i32)
define i32 @M2_mpysu_up(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.M2.mpysu.up(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = mpysu({{.*}}, {{.*}})
+; CHECK: = mpysu({{.*}},{{.*}})
declare i32 @llvm.hexagon.M2.hmmpyh.s1(i32, i32)
define i32 @M2_hmmpyh_s1(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.M2.hmmpyh.s1(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = mpy({{.*}}, {{.*}}.h):<<1:sat
+; CHECK: = mpy({{.*}},{{.*}}.h):<<1:sat
declare i32 @llvm.hexagon.M2.hmmpyl.s1(i32, i32)
define i32 @M2_hmmpyl_s1(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.M2.hmmpyl.s1(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = mpy({{.*}}, {{.*}}.l):<<1:sat
+; CHECK: = mpy({{.*}},{{.*}}.l):<<1:sat
declare i32 @llvm.hexagon.M2.hmmpyh.rs1(i32, i32)
define i32 @M2_hmmpyh_rs1(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.M2.hmmpyh.rs1(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = mpy({{.*}}, {{.*}}.h):<<1:rnd:sat
+; CHECK: = mpy({{.*}},{{.*}}.h):<<1:rnd:sat
declare i32 @llvm.hexagon.M2.mpy.up.s1.sat(i32, i32)
define i32 @M2_mpy_up_s1_sat(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.M2.mpy.up.s1.sat(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = mpy({{.*}}, {{.*}}):<<1:sat
+; CHECK: = mpy({{.*}},{{.*}}):<<1:sat
declare i32 @llvm.hexagon.M2.hmmpyl.rs1(i32, i32)
define i32 @M2_hmmpyl_rs1(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.M2.hmmpyl.rs1(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = mpy({{.*}}, {{.*}}.l):<<1:rnd:sat
+; CHECK: = mpy({{.*}},{{.*}}.l):<<1:rnd:sat
declare i32 @llvm.hexagon.M2.mpy.up(i32, i32)
define i32 @M2_mpy_up(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.M2.mpy.up(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = mpy({{.*}}, {{.*}})
+; CHECK: = mpy({{.*}},{{.*}})
declare i32 @llvm.hexagon.M2.mpy.up.s1(i32, i32)
define i32 @M2_mpy_up_s1(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.M2.mpy.up.s1(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = mpy({{.*}}, {{.*}}):<<1
+; CHECK: = mpy({{.*}},{{.*}}):<<1
declare i32 @llvm.hexagon.M4.mac.up.s1.sat(i32, i32, i32)
define i32 @M4_mac_up_s1_sat(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M4.mac.up.s1.sat(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: += mpy({{.*}}, {{.*}}):<<1:sat
+; CHECK: += mpy({{.*}},{{.*}}):<<1:sat
declare i32 @llvm.hexagon.M4.nac.up.s1.sat(i32, i32, i32)
define i32 @M4_nac_up_s1_sat(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.M4.nac.up.s1.sat(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: -= mpy({{.*}}, {{.*}}):<<1:sat
+; CHECK: -= mpy({{.*}},{{.*}}):<<1:sat
; Multiply and use full result
declare i64 @llvm.hexagon.M2.dpmpyss.s0(i32, i32)
@@ -1272,42 +1272,42 @@ define i64 @M2_dpmpyss_s0(i32 %a, i32 %b
%z = call i64 @llvm.hexagon.M2.dpmpyss.s0(i32 %a, i32 %b)
ret i64 %z
}
-; CHECK: = mpy({{.*}}, {{.*}})
+; CHECK: = mpy({{.*}},{{.*}})
declare i64 @llvm.hexagon.M2.dpmpyuu.s0(i32, i32)
define i64 @M2_dpmpyuu_s0(i32 %a, i32 %b) {
%z = call i64 @llvm.hexagon.M2.dpmpyuu.s0(i32 %a, i32 %b)
ret i64 %z
}
-; CHECK: = mpyu({{.*}}, {{.*}})
+; CHECK: = mpyu({{.*}},{{.*}})
declare i64 @llvm.hexagon.M2.dpmpyss.acc.s0(i64, i32, i32)
define i64 @M2_dpmpyss_acc_s0(i64 %a, i32 %b, i32 %c) {
%z = call i64 @llvm.hexagon.M2.dpmpyss.acc.s0(i64 %a, i32 %b, i32 %c)
ret i64 %z
}
-; CHECK: += mpy({{.*}}, {{.*}})
+; CHECK: += mpy({{.*}},{{.*}})
declare i64 @llvm.hexagon.M2.dpmpyss.nac.s0(i64, i32, i32)
define i64 @M2_dpmpyss_nac_s0(i64 %a, i32 %b, i32 %c) {
%z = call i64 @llvm.hexagon.M2.dpmpyss.nac.s0(i64 %a, i32 %b, i32 %c)
ret i64 %z
}
-; CHECK: -= mpy({{.*}}, {{.*}})
+; CHECK: -= mpy({{.*}},{{.*}})
declare i64 @llvm.hexagon.M2.dpmpyuu.acc.s0(i64, i32, i32)
define i64 @M2_dpmpyuu_acc_s0(i64 %a, i32 %b, i32 %c) {
%z = call i64 @llvm.hexagon.M2.dpmpyuu.acc.s0(i64 %a, i32 %b, i32 %c)
ret i64 %z
}
-; CHECK: += mpyu({{.*}}, {{.*}})
+; CHECK: += mpyu({{.*}},{{.*}})
declare i64 @llvm.hexagon.M2.dpmpyuu.nac.s0(i64, i32, i32)
define i64 @M2_dpmpyuu_nac_s0(i64 %a, i32 %b, i32 %c) {
%z = call i64 @llvm.hexagon.M2.dpmpyuu.nac.s0(i64 %a, i32 %b, i32 %c)
ret i64 %z
}
-; CHECK: -= mpyu({{.*}}, {{.*}})
+; CHECK: -= mpyu({{.*}},{{.*}})
; Vector dual multiply
declare i64 @llvm.hexagon.M2.vdmpys.s0(i64, i64)
@@ -1315,14 +1315,14 @@ define i64 @M2_vdmpys_s0(i64 %a, i64 %b)
%z = call i64 @llvm.hexagon.M2.vdmpys.s0(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vdmpy({{.*}}, {{.*}}):sat
+; CHECK: = vdmpy({{.*}},{{.*}}):sat
declare i64 @llvm.hexagon.M2.vdmpys.s1(i64, i64)
define i64 @M2_vdmpys_s1(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.M2.vdmpys.s1(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vdmpy({{.*}}, {{.*}}):<<1:sat
+; CHECK: = vdmpy({{.*}},{{.*}}):<<1:sat
; Vector reduce multiply bytes
declare i64 @llvm.hexagon.M5.vrmpybuu(i64, i64)
@@ -1330,28 +1330,28 @@ define i64 @M5_vrmpybuu(i64 %a, i64 %b)
%z = call i64 @llvm.hexagon.M5.vrmpybuu(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vrmpybu({{.*}}, {{.*}})
+; CHECK: = vrmpybu({{.*}},{{.*}})
declare i64 @llvm.hexagon.M5.vrmpybsu(i64, i64)
define i64 @M5_vrmpybsu(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.M5.vrmpybsu(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vrmpybsu({{.*}}, {{.*}})
+; CHECK: = vrmpybsu({{.*}},{{.*}})
declare i64 @llvm.hexagon.M5.vrmacbuu(i64, i64, i64)
define i64 @M5_vrmacbuu(i64 %a, i64 %b, i64 %c) {
%z = call i64 @llvm.hexagon.M5.vrmacbuu(i64 %a, i64 %b, i64 %c)
ret i64 %z
}
-; CHECK: += vrmpybu({{.*}}, r5:4)
+; CHECK: += vrmpybu({{.*}},r5:4)
declare i64 @llvm.hexagon.M5.vrmacbsu(i64, i64, i64)
define i64 @M5_vrmacbsu(i64 %a, i64 %b, i64 %c) {
%z = call i64 @llvm.hexagon.M5.vrmacbsu(i64 %a, i64 %b, i64 %c)
ret i64 %z
}
-; CHECK: += vrmpybsu({{.*}}, r5:4)
+; CHECK: += vrmpybsu({{.*}},r5:4)
; Vector dual multiply signed by unsigned bytes
declare i64 @llvm.hexagon.M5.vdmpybsu(i64, i64)
@@ -1359,14 +1359,14 @@ define i64 @M5_vdmpybsu(i64 %a, i64 %b)
%z = call i64 @llvm.hexagon.M5.vdmpybsu(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vdmpybsu({{.*}}, {{.*}}):sat
+; CHECK: = vdmpybsu({{.*}},{{.*}}):sat
declare i64 @llvm.hexagon.M5.vdmacbsu(i64, i64, i64)
define i64 @M5_vdmacbsu(i64 %a, i64 %b, i64 %c) {
%z = call i64 @llvm.hexagon.M5.vdmacbsu(i64 %a, i64 %b, i64 %c)
ret i64 %z
}
-; CHECK: += vdmpybsu({{.*}}, r5:4):sat
+; CHECK: += vdmpybsu({{.*}},r5:4):sat
; Vector multiply even halfwords
declare i64 @llvm.hexagon.M2.vmpy2es.s0(i64, i64)
@@ -1374,35 +1374,35 @@ define i64 @M2_vmpy2es_s0(i64 %a, i64 %b
%z = call i64 @llvm.hexagon.M2.vmpy2es.s0(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vmpyeh({{.*}}, {{.*}}):sat
+; CHECK: = vmpyeh({{.*}},{{.*}}):sat
declare i64 @llvm.hexagon.M2.vmpy2es.s1(i64, i64)
define i64 @M2_vmpy2es_s1(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.M2.vmpy2es.s1(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vmpyeh({{.*}}, {{.*}}):<<1:sat
+; CHECK: = vmpyeh({{.*}},{{.*}}):<<1:sat
declare i64 @llvm.hexagon.M2.vmac2es(i64, i64, i64)
define i64 @M2_vmac2es(i64 %a, i64 %b, i64 %c) {
%z = call i64 @llvm.hexagon.M2.vmac2es(i64 %a, i64 %b, i64 %c)
ret i64 %z
}
-; CHECK: += vmpyeh({{.*}}, r5:4)
+; CHECK: += vmpyeh({{.*}},r5:4)
declare i64 @llvm.hexagon.M2.vmac2es.s0(i64, i64, i64)
define i64 @M2_vmac2es_s0(i64 %a, i64 %b, i64 %c) {
%z = call i64 @llvm.hexagon.M2.vmac2es.s0(i64 %a, i64 %b, i64 %c)
ret i64 %z
}
-; CHECK: += vmpyeh({{.*}}, r5:4):sat
+; CHECK: += vmpyeh({{.*}},r5:4):sat
declare i64 @llvm.hexagon.M2.vmac2es.s1(i64, i64, i64)
define i64 @M2_vmac2es_s1(i64 %a, i64 %b, i64 %c) {
%z = call i64 @llvm.hexagon.M2.vmac2es.s1(i64 %a, i64 %b, i64 %c)
ret i64 %z
}
-; CHECK: += vmpyeh({{.*}}, r5:4):<<1:sat
+; CHECK: += vmpyeh({{.*}},r5:4):<<1:sat
; Vector multiply halfwords
declare i64 @llvm.hexagon.M2.vmpy2s.s0(i32, i32)
@@ -1410,35 +1410,35 @@ define i64 @M2_vmpy2s_s0(i32 %a, i32 %b)
%z = call i64 @llvm.hexagon.M2.vmpy2s.s0(i32 %a, i32 %b)
ret i64 %z
}
-; CHECK: = vmpyh({{.*}}, {{.*}}):sat
+; CHECK: = vmpyh({{.*}},{{.*}}):sat
declare i64 @llvm.hexagon.M2.vmpy2s.s1(i32, i32)
define i64 @M2_vmpy2s_s1(i32 %a, i32 %b) {
%z = call i64 @llvm.hexagon.M2.vmpy2s.s1(i32 %a, i32 %b)
ret i64 %z
}
-; CHECK: = vmpyh({{.*}}, {{.*}}):<<1:sat
+; CHECK: = vmpyh({{.*}},{{.*}}):<<1:sat
declare i64 @llvm.hexagon.M2.vmac2(i64, i32, i32)
define i64 @M2_vmac2(i64 %a, i32 %b, i32 %c) {
%z = call i64 @llvm.hexagon.M2.vmac2(i64 %a, i32 %b, i32 %c)
ret i64 %z
}
-; CHECK: += vmpyh({{.*}}, {{.*}})
+; CHECK: += vmpyh({{.*}},{{.*}})
declare i64 @llvm.hexagon.M2.vmac2s.s0(i64, i32, i32)
define i64 @M2_vmac2s_s0(i64 %a, i32 %b, i32 %c) {
%z = call i64 @llvm.hexagon.M2.vmac2s.s0(i64 %a, i32 %b, i32 %c)
ret i64 %z
}
-; CHECK: += vmpyh({{.*}}, {{.*}}):sat
+; CHECK: += vmpyh({{.*}},{{.*}}):sat
declare i64 @llvm.hexagon.M2.vmac2s.s1(i64, i32, i32)
define i64 @M2_vmac2s_s1(i64 %a, i32 %b, i32 %c) {
%z = call i64 @llvm.hexagon.M2.vmac2s.s1(i64 %a, i32 %b, i32 %c)
ret i64 %z
}
-; CHECK: += vmpyh({{.*}}, {{.*}}):<<1:sat
+; CHECK: += vmpyh({{.*}},{{.*}}):<<1:sat
; Vector multiply halfwords signed by unsigned
declare i64 @llvm.hexagon.M2.vmpy2su.s0(i32, i32)
@@ -1446,28 +1446,28 @@ define i64 @M2_vmpy2su_s0(i32 %a, i32 %b
%z = call i64 @llvm.hexagon.M2.vmpy2su.s0(i32 %a, i32 %b)
ret i64 %z
}
-; CHECK: = vmpyhsu({{.*}}, {{.*}}):sat
+; CHECK: = vmpyhsu({{.*}},{{.*}}):sat
declare i64 @llvm.hexagon.M2.vmpy2su.s1(i32, i32)
define i64 @M2_vmpy2su_s1(i32 %a, i32 %b) {
%z = call i64 @llvm.hexagon.M2.vmpy2su.s1(i32 %a, i32 %b)
ret i64 %z
}
-; CHECK: = vmpyhsu({{.*}}, {{.*}}):<<1:sat
+; CHECK: = vmpyhsu({{.*}},{{.*}}):<<1:sat
declare i64 @llvm.hexagon.M2.vmac2su.s0(i64, i32, i32)
define i64 @M2_vmac2su_s0(i64 %a, i32 %b, i32 %c) {
%z = call i64 @llvm.hexagon.M2.vmac2su.s0(i64 %a, i32 %b, i32 %c)
ret i64 %z
}
-; CHECK: += vmpyhsu({{.*}}, {{.*}}):sat
+; CHECK: += vmpyhsu({{.*}},{{.*}}):sat
declare i64 @llvm.hexagon.M2.vmac2su.s1(i64, i32, i32)
define i64 @M2_vmac2su_s1(i64 %a, i32 %b, i32 %c) {
%z = call i64 @llvm.hexagon.M2.vmac2su.s1(i64 %a, i32 %b, i32 %c)
ret i64 %z
}
-; CHECK: += vmpyhsu({{.*}}, {{.*}}):<<1:sat
+; CHECK: += vmpyhsu({{.*}},{{.*}}):<<1:sat
; Vector reduce multiply halfwords
declare i64 @llvm.hexagon.M2.vrmpy.s0(i64, i64)
@@ -1475,14 +1475,14 @@ define i64 @M2_vrmpy_s0(i64 %a, i64 %b)
%z = call i64 @llvm.hexagon.M2.vrmpy.s0(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vrmpyh({{.*}}, {{.*}})
+; CHECK: = vrmpyh({{.*}},{{.*}})
declare i64 @llvm.hexagon.M2.vrmac.s0(i64, i64, i64)
define i64 @M2_vrmac_s0(i64 %a, i64 %b, i64 %c) {
%z = call i64 @llvm.hexagon.M2.vrmac.s0(i64 %a, i64 %b, i64 %c)
ret i64 %z
}
-; CHECK: += vrmpyh({{.*}}, r5:4)
+; CHECK: += vrmpyh({{.*}},r5:4)
; Vector multiply bytes
declare i64 @llvm.hexagon.M5.vmpybsu(i32, i32)
@@ -1490,28 +1490,28 @@ define i64 @M2_vmpybsu(i32 %a, i32 %b) {
%z = call i64 @llvm.hexagon.M5.vmpybsu(i32 %a, i32 %b)
ret i64 %z
}
-; CHECK: = vmpybsu({{.*}}, {{.*}})
+; CHECK: = vmpybsu({{.*}},{{.*}})
declare i64 @llvm.hexagon.M5.vmpybuu(i32, i32)
define i64 @M2_vmpybuu(i32 %a, i32 %b) {
%z = call i64 @llvm.hexagon.M5.vmpybuu(i32 %a, i32 %b)
ret i64 %z
}
-; CHECK: = vmpybu({{.*}}, {{.*}})
+; CHECK: = vmpybu({{.*}},{{.*}})
declare i64 @llvm.hexagon.M5.vmacbuu(i64, i32, i32)
define i64 @M2_vmacbuu(i64 %a, i32 %b, i32 %c) {
%z = call i64 @llvm.hexagon.M5.vmacbuu(i64 %a, i32 %b, i32 %c)
ret i64 %z
}
-; CHECK: += vmpybu({{.*}}, {{.*}})
+; CHECK: += vmpybu({{.*}},{{.*}})
declare i64 @llvm.hexagon.M5.vmacbsu(i64, i32, i32)
define i64 @M2_vmacbsu(i64 %a, i32 %b, i32 %c) {
%z = call i64 @llvm.hexagon.M5.vmacbsu(i64 %a, i32 %b, i32 %c)
ret i64 %z
}
-; CHECK: += vmpybsu({{.*}}, {{.*}})
+; CHECK: += vmpybsu({{.*}},{{.*}})
; Vector polynomial multiply halfwords
declare i64 @llvm.hexagon.M4.vpmpyh(i32, i32)
@@ -1519,11 +1519,11 @@ define i64 @M4_vpmpyh(i32 %a, i32 %b) {
%z = call i64 @llvm.hexagon.M4.vpmpyh(i32 %a, i32 %b)
ret i64 %z
}
-; CHECK: = vpmpyh({{.*}}, {{.*}})
+; CHECK: = vpmpyh({{.*}},{{.*}})
declare i64 @llvm.hexagon.M4.vpmpyh.acc(i64, i32, i32)
define i64 @M4_vpmpyh_acc(i64 %a, i32 %b, i32 %c) {
%z = call i64 @llvm.hexagon.M4.vpmpyh.acc(i64 %a, i32 %b, i32 %c)
ret i64 %z
}
-; CHECK: ^= vpmpyh({{.*}}, {{.*}})
+; CHECK: ^= vpmpyh({{.*}},{{.*}})
Modified: llvm/trunk/test/CodeGen/Hexagon/intrinsics/xtype_perm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/intrinsics/xtype_perm.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/intrinsics/xtype_perm.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/intrinsics/xtype_perm.ll Fri Feb 10 09:33:13 2017
@@ -141,28 +141,28 @@ define i64 @S2_shuffeb(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.S2.shuffeb(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = shuffeb({{.*}}, {{.*}})
+; CHECK: = shuffeb({{.*}},{{.*}})
declare i64 @llvm.hexagon.S2.shuffob(i64, i64)
define i64 @S2_shuffob(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.S2.shuffob(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = shuffob({{.*}}, {{.*}})
+; CHECK: = shuffob({{.*}},{{.*}})
declare i64 @llvm.hexagon.S2.shuffeh(i64, i64)
define i64 @S2_shuffeh(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.S2.shuffeh(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = shuffeh({{.*}}, {{.*}})
+; CHECK: = shuffeh({{.*}},{{.*}})
declare i64 @llvm.hexagon.S2.shuffoh(i64, i64)
define i64 @S2_shuffoh(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.S2.shuffoh(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = shuffoh({{.*}}, {{.*}})
+; CHECK: = shuffoh({{.*}},{{.*}})
; Vector splat bytes
declare i32 @llvm.hexagon.S2.vsplatrb(i32)
@@ -186,14 +186,14 @@ define i64 @S2_vspliceib(i64 %a, i64 %b)
%z = call i64 @llvm.hexagon.S2.vspliceib(i64 %a, i64 %b, i32 0)
ret i64 %z
}
-; CHECK: = vspliceb({{.*}}, {{.*}}, #0)
+; CHECK: = vspliceb({{.*}},{{.*}},#0)
declare i64 @llvm.hexagon.S2.vsplicerb(i64, i64, i32)
define i64 @S2_vsplicerb(i64 %a, i64 %b, i32 %c) {
%z = call i64 @llvm.hexagon.S2.vsplicerb(i64 %a, i64 %b, i32 %c)
ret i64 %z
}
-; CHECK: = vspliceb({{.*}}, {{.*}}, {{.*}})
+; CHECK: = vspliceb({{.*}},{{.*}},{{.*}})
; Vector sign extend
declare i64 @llvm.hexagon.S2.vsxtbh(i32)
@@ -230,14 +230,14 @@ define i64 @S2_vtrunowh(i64 %a, i64 %b)
%z = call i64 @llvm.hexagon.S2.vtrunowh(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vtrunowh({{.*}}, {{.*}})
+; CHECK: = vtrunowh({{.*}},{{.*}})
declare i64 @llvm.hexagon.S2.vtrunewh(i64, i64)
define i64 @S2_vtrunewh(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.S2.vtrunewh(i64 %a, i64 %b)
ret i64 %z
}
-; CHECK: = vtrunewh({{.*}}, {{.*}})
+; CHECK: = vtrunewh({{.*}},{{.*}})
; Vector zero extend
declare i64 @llvm.hexagon.S2.vzxtbh(i32)
Modified: llvm/trunk/test/CodeGen/Hexagon/intrinsics/xtype_pred.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/intrinsics/xtype_pred.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/intrinsics/xtype_pred.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/intrinsics/xtype_pred.ll Fri Feb 10 09:33:13 2017
@@ -10,42 +10,42 @@ define i32 @A4_cmpbgt(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.A4.cmpbgt(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = cmpb.gt({{.*}}, {{.*}})
+; CHECK: = cmpb.gt({{.*}},{{.*}})
declare i32 @llvm.hexagon.A4.cmpbeq(i32, i32)
define i32 @A4_cmpbeq(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.A4.cmpbeq(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = cmpb.eq({{.*}}, {{.*}})
+; CHECK: = cmpb.eq({{.*}},{{.*}})
declare i32 @llvm.hexagon.A4.cmpbgtu(i32, i32)
define i32 @A4_cmpbgtu(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.A4.cmpbgtu(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = cmpb.gtu({{.*}}, {{.*}})
+; CHECK: = cmpb.gtu({{.*}},{{.*}})
declare i32 @llvm.hexagon.A4.cmpbgti(i32, i32)
define i32 @A4_cmpbgti(i32 %a) {
%z = call i32 @llvm.hexagon.A4.cmpbgti(i32 %a, i32 0)
ret i32 %z
}
-; CHECK: = cmpb.gt({{.*}}, #0)
+; CHECK: = cmpb.gt({{.*}},#0)
declare i32 @llvm.hexagon.A4.cmpbeqi(i32, i32)
define i32 @A4_cmpbeqi(i32 %a) {
%z = call i32 @llvm.hexagon.A4.cmpbeqi(i32 %a, i32 0)
ret i32 %z
}
-; CHECK: = cmpb.eq({{.*}}, #0)
+; CHECK: = cmpb.eq({{.*}},#0)
declare i32 @llvm.hexagon.A4.cmpbgtui(i32, i32)
define i32 @A4_cmpbgtui(i32 %a) {
%z = call i32 @llvm.hexagon.A4.cmpbgtui(i32 %a, i32 0)
ret i32 %z
}
-; CHECK: = cmpb.gtu({{.*}}, #0)
+; CHECK: = cmpb.gtu({{.*}},#0)
; Compare half
declare i32 @llvm.hexagon.A4.cmphgt(i32, i32)
@@ -53,42 +53,42 @@ define i32 @A4_cmphgt(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.A4.cmphgt(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = cmph.gt({{.*}}, {{.*}})
+; CHECK: = cmph.gt({{.*}},{{.*}})
declare i32 @llvm.hexagon.A4.cmpheq(i32, i32)
define i32 @A4_cmpheq(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.A4.cmpheq(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = cmph.eq({{.*}}, {{.*}})
+; CHECK: = cmph.eq({{.*}},{{.*}})
declare i32 @llvm.hexagon.A4.cmphgtu(i32, i32)
define i32 @A4_cmphgtu(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.A4.cmphgtu(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = cmph.gtu({{.*}}, {{.*}})
+; CHECK: = cmph.gtu({{.*}},{{.*}})
declare i32 @llvm.hexagon.A4.cmphgti(i32, i32)
define i32 @A4_cmphgti(i32 %a) {
%z = call i32 @llvm.hexagon.A4.cmphgti(i32 %a, i32 0)
ret i32 %z
}
-; CHECK: = cmph.gt({{.*}}, #0)
+; CHECK: = cmph.gt({{.*}},#0)
declare i32 @llvm.hexagon.A4.cmpheqi(i32, i32)
define i32 @A4_cmpheqi(i32 %a) {
%z = call i32 @llvm.hexagon.A4.cmpheqi(i32 %a, i32 0)
ret i32 %z
}
-; CHECK: = cmph.eq({{.*}}, #0)
+; CHECK: = cmph.eq({{.*}},#0)
declare i32 @llvm.hexagon.A4.cmphgtui(i32, i32)
define i32 @A4_cmphgtui(i32 %a) {
%z = call i32 @llvm.hexagon.A4.cmphgtui(i32 %a, i32 0)
ret i32 %z
}
-; CHECK: = cmph.gtu({{.*}}, #0)
+; CHECK: = cmph.gtu({{.*}},#0)
; Compare doublewords
declare i32 @llvm.hexagon.C2.cmpgtp(i64, i64)
@@ -96,21 +96,21 @@ define i32 @C2_cmpgtp(i64 %a, i64 %b) {
%z = call i32 @llvm.hexagon.C2.cmpgtp(i64 %a, i64 %b)
ret i32 %z
}
-; CHECK: = cmp.gt({{.*}}, {{.*}})
+; CHECK: = cmp.gt({{.*}},{{.*}})
declare i32 @llvm.hexagon.C2.cmpeqp(i64, i64)
define i32 @C2_cmpeqp(i64 %a, i64 %b) {
%z = call i32 @llvm.hexagon.C2.cmpeqp(i64 %a, i64 %b)
ret i32 %z
}
-; CHECK: = cmp.eq({{.*}}, {{.*}})
+; CHECK: = cmp.eq({{.*}},{{.*}})
declare i32 @llvm.hexagon.C2.cmpgtup(i64, i64)
define i32 @C2_cmpgtup(i64 %a, i64 %b) {
%z = call i32 @llvm.hexagon.C2.cmpgtup(i64 %a, i64 %b)
ret i32 %z
}
-; CHECK: = cmp.gtu({{.*}}, {{.*}})
+; CHECK: = cmp.gtu({{.*}},{{.*}})
; Compare bitmask
declare i32 @llvm.hexagon.C2.bitsclri(i32, i32)
@@ -118,42 +118,42 @@ define i32 @C2_bitsclri(i32 %a) {
%z = call i32 @llvm.hexagon.C2.bitsclri(i32 %a, i32 0)
ret i32 %z
}
-; CHECK: = bitsclr({{.*}}, #0)
+; CHECK: = bitsclr({{.*}},#0)
declare i32 @llvm.hexagon.C4.nbitsclri(i32, i32)
define i32 @C4_nbitsclri(i32 %a) {
%z = call i32 @llvm.hexagon.C4.nbitsclri(i32 %a, i32 0)
ret i32 %z
}
-; CHECK: = !bitsclr({{.*}}, #0)
+; CHECK: = !bitsclr({{.*}},#0)
declare i32 @llvm.hexagon.C2.bitsset(i32, i32)
define i32 @C2_bitsset(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.C2.bitsset(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = bitsset({{.*}}, {{.*}})
+; CHECK: = bitsset({{.*}},{{.*}})
declare i32 @llvm.hexagon.C4.nbitsset(i32, i32)
define i32 @C4_nbitsset(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.C4.nbitsset(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = !bitsset({{.*}}, {{.*}})
+; CHECK: = !bitsset({{.*}},{{.*}})
declare i32 @llvm.hexagon.C2.bitsclr(i32, i32)
define i32 @C2_bitsclr(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.C2.bitsclr(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = bitsclr({{.*}}, {{.*}})
+; CHECK: = bitsclr({{.*}},{{.*}})
declare i32 @llvm.hexagon.C4.nbitsclr(i32, i32)
define i32 @C4_nbitsclr(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.C4.nbitsclr(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = !bitsclr({{.*}}, {{.*}})
+; CHECK: = !bitsclr({{.*}},{{.*}})
; Mask generate from predicate
declare i64 @llvm.hexagon.C2.mask(i32)
@@ -169,7 +169,7 @@ define i32 @A4_tlbmatch(i64 %a, i32 %b)
%z = call i32 @llvm.hexagon.A4.tlbmatch(i64 %a, i32 %b)
ret i32 %z
}
-; CHECK: = tlbmatch({{.*}}, {{.*}})
+; CHECK: = tlbmatch({{.*}},{{.*}})
; Test bit
declare i32 @llvm.hexagon.S2.tstbit.i(i32, i32)
@@ -177,28 +177,28 @@ define i32 @S2_tstbit_i(i32 %a) {
%z = call i32 @llvm.hexagon.S2.tstbit.i(i32 %a, i32 0)
ret i32 %z
}
-; CHECK: = tstbit({{.*}}, #0)
+; CHECK: = tstbit({{.*}},#0)
declare i32 @llvm.hexagon.S4.ntstbit.i(i32, i32)
define i32 @S4_ntstbit_i(i32 %a) {
%z = call i32 @llvm.hexagon.S4.ntstbit.i(i32 %a, i32 0)
ret i32 %z
}
-; CHECK: = !tstbit({{.*}}, #0)
+; CHECK: = !tstbit({{.*}},#0)
declare i32 @llvm.hexagon.S2.tstbit.r(i32, i32)
define i32 @S2_tstbit_r(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.S2.tstbit.r(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = tstbit({{.*}}, {{.*}})
+; CHECK: = tstbit({{.*}},{{.*}})
declare i32 @llvm.hexagon.S4.ntstbit.r(i32, i32)
define i32 @S4_ntstbit_r(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.S4.ntstbit.r(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = !tstbit({{.*}}, {{.*}})
+; CHECK: = !tstbit({{.*}},{{.*}})
; Vector compare halfwords
declare i32 @llvm.hexagon.A2.vcmpheq(i64, i64)
@@ -206,42 +206,42 @@ define i32 @A2_vcmpheq(i64 %a, i64 %b) {
%z = call i32 @llvm.hexagon.A2.vcmpheq(i64 %a, i64 %b)
ret i32 %z
}
-; CHECK: = vcmph.eq({{.*}}, {{.*}})
+; CHECK: = vcmph.eq({{.*}},{{.*}})
declare i32 @llvm.hexagon.A2.vcmphgt(i64, i64)
define i32 @A2_vcmphgt(i64 %a, i64 %b) {
%z = call i32 @llvm.hexagon.A2.vcmphgt(i64 %a, i64 %b)
ret i32 %z
}
-; CHECK: = vcmph.gt({{.*}}, {{.*}})
+; CHECK: = vcmph.gt({{.*}},{{.*}})
declare i32 @llvm.hexagon.A2.vcmphgtu(i64, i64)
define i32 @A2_vcmphgtu(i64 %a, i64 %b) {
%z = call i32 @llvm.hexagon.A2.vcmphgtu(i64 %a, i64 %b)
ret i32 %z
}
-; CHECK: = vcmph.gtu({{.*}}, {{.*}})
+; CHECK: = vcmph.gtu({{.*}},{{.*}})
declare i32 @llvm.hexagon.A4.vcmpheqi(i64, i32)
define i32 @A4_vcmpheqi(i64 %a) {
%z = call i32 @llvm.hexagon.A4.vcmpheqi(i64 %a, i32 0)
ret i32 %z
}
-; CHECK: = vcmph.eq({{.*}}, #0)
+; CHECK: = vcmph.eq({{.*}},#0)
declare i32 @llvm.hexagon.A4.vcmphgti(i64, i32)
define i32 @A4_vcmphgti(i64 %a) {
%z = call i32 @llvm.hexagon.A4.vcmphgti(i64 %a, i32 0)
ret i32 %z
}
-; CHECK: = vcmph.gt({{.*}}, #0)
+; CHECK: = vcmph.gt({{.*}},#0)
declare i32 @llvm.hexagon.A4.vcmphgtui(i64, i32)
define i32 @A4_vcmphgtui(i64 %a) {
%z = call i32 @llvm.hexagon.A4.vcmphgtui(i64 %a, i32 0)
ret i32 %z
}
-; CHECK: = vcmph.gtu({{.*}}, #0)
+; CHECK: = vcmph.gtu({{.*}},#0)
; Vector compare bytes for any match
declare i32 @llvm.hexagon.A4.vcmpbeq.any(i64, i64)
@@ -249,7 +249,7 @@ define i32 @A4_vcmpbeq_any(i64 %a, i64 %
%z = call i32 @llvm.hexagon.A4.vcmpbeq.any(i64 %a, i64 %b)
ret i32 %z
}
-; CHECK: = any8(vcmpb.eq({{.*}}, {{.*}}))
+; CHECK: = any8(vcmpb.eq({{.*}},{{.*}}))
; Vector compare bytes
declare i32 @llvm.hexagon.A2.vcmpbeq(i64, i64)
@@ -257,42 +257,42 @@ define i32 @A2_vcmpbeq(i64 %a, i64 %b) {
%z = call i32 @llvm.hexagon.A2.vcmpbeq(i64 %a, i64 %b)
ret i32 %z
}
-; CHECK: = vcmpb.eq({{.*}}, {{.*}})
+; CHECK: = vcmpb.eq({{.*}},{{.*}})
declare i32 @llvm.hexagon.A2.vcmpbgtu(i64, i64)
define i32 @A2_vcmpbgtu(i64 %a, i64 %b) {
%z = call i32 @llvm.hexagon.A2.vcmpbgtu(i64 %a, i64 %b)
ret i32 %z
}
-; CHECK: = vcmpb.gtu({{.*}}, {{.*}})
+; CHECK: = vcmpb.gtu({{.*}},{{.*}})
declare i32 @llvm.hexagon.A4.vcmpbgt(i64, i64)
define i32 @A4_vcmpbgt(i64 %a, i64 %b) {
%z = call i32 @llvm.hexagon.A4.vcmpbgt(i64 %a, i64 %b)
ret i32 %z
}
-; CHECK: = vcmpb.gt({{.*}}, {{.*}})
+; CHECK: = vcmpb.gt({{.*}},{{.*}})
declare i32 @llvm.hexagon.A4.vcmpbeqi(i64, i32)
define i32 @A4_vcmpbeqi(i64 %a) {
%z = call i32 @llvm.hexagon.A4.vcmpbeqi(i64 %a, i32 0)
ret i32 %z
}
-; CHECK: = vcmpb.eq({{.*}}, #0)
+; CHECK: = vcmpb.eq({{.*}},#0)
declare i32 @llvm.hexagon.A4.vcmpbgti(i64, i32)
define i32 @A4_vcmpbgti(i64 %a) {
%z = call i32 @llvm.hexagon.A4.vcmpbgti(i64 %a, i32 0)
ret i32 %z
}
-; CHECK: = vcmpb.gt({{.*}}, #0)
+; CHECK: = vcmpb.gt({{.*}},#0)
declare i32 @llvm.hexagon.A4.vcmpbgtui(i64, i32)
define i32 @A4_vcmpbgtui(i64 %a) {
%z = call i32 @llvm.hexagon.A4.vcmpbgtui(i64 %a, i32 0)
ret i32 %z
}
-; CHECK: = vcmpb.gtu({{.*}}, #0)
+; CHECK: = vcmpb.gtu({{.*}},#0)
; Vector compare words
declare i32 @llvm.hexagon.A2.vcmpweq(i64, i64)
@@ -300,42 +300,42 @@ define i32 @A2_vcmpweq(i64 %a, i64 %b) {
%z = call i32 @llvm.hexagon.A2.vcmpweq(i64 %a, i64 %b)
ret i32 %z
}
-; CHECK: = vcmpw.eq({{.*}}, {{.*}})
+; CHECK: = vcmpw.eq({{.*}},{{.*}})
declare i32 @llvm.hexagon.A2.vcmpwgt(i64, i64)
define i32 @A2_vcmpwgt(i64 %a, i64 %b) {
%z = call i32 @llvm.hexagon.A2.vcmpwgt(i64 %a, i64 %b)
ret i32 %z
}
-; CHECK: = vcmpw.gt({{.*}}, {{.*}})
+; CHECK: = vcmpw.gt({{.*}},{{.*}})
declare i32 @llvm.hexagon.A2.vcmpwgtu(i64, i64)
define i32 @A2_vcmpwgtu(i64 %a, i64 %b) {
%z = call i32 @llvm.hexagon.A2.vcmpwgtu(i64 %a, i64 %b)
ret i32 %z
}
-; CHECK: = vcmpw.gtu({{.*}}, {{.*}})
+; CHECK: = vcmpw.gtu({{.*}},{{.*}})
declare i32 @llvm.hexagon.A4.vcmpweqi(i64, i32)
define i32 @A4_vcmpweqi(i64 %a) {
%z = call i32 @llvm.hexagon.A4.vcmpweqi(i64 %a, i32 0)
ret i32 %z
}
-; CHECK: = vcmpw.eq({{.*}}, #0)
+; CHECK: = vcmpw.eq({{.*}},#0)
declare i32 @llvm.hexagon.A4.vcmpwgti(i64, i32)
define i32 @A4_vcmpwgti(i64 %a) {
%z = call i32 @llvm.hexagon.A4.vcmpwgti(i64 %a, i32 0)
ret i32 %z
}
-; CHECK: = vcmpw.gt({{.*}}, #0)
+; CHECK: = vcmpw.gt({{.*}},#0)
declare i32 @llvm.hexagon.A4.vcmpwgtui(i64, i32)
define i32 @A4_vcmpwgtui(i64 %a) {
%z = call i32 @llvm.hexagon.A4.vcmpwgtui(i64 %a, i32 0)
ret i32 %z
}
-; CHECK: = vcmpw.gtu({{.*}}, #0)
+; CHECK: = vcmpw.gtu({{.*}},#0)
; Viterbi pack even and odd predicate bitsclr
declare i32 @llvm.hexagon.C2.vitpack(i32, i32)
@@ -343,7 +343,7 @@ define i32 @C2_vitpack(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.C2.vitpack(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = vitpack({{.*}}, {{.*}})
+; CHECK: = vitpack({{.*}},{{.*}})
; Vector mux
declare i64 @llvm.hexagon.C2.vmux(i32, i64, i64)
@@ -351,4 +351,4 @@ define i64 @C2_vmux(i32 %a, i64 %b, i64
%z = call i64 @llvm.hexagon.C2.vmux(i32 %a, i64 %b, i64 %c)
ret i64 %z
}
-; CHECK: = vmux({{.*}}, {{.*}}, {{.*}})
+; CHECK: = vmux({{.*}},{{.*}},{{.*}})
Modified: llvm/trunk/test/CodeGen/Hexagon/intrinsics/xtype_shift.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/intrinsics/xtype_shift.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/intrinsics/xtype_shift.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/intrinsics/xtype_shift.ll Fri Feb 10 09:33:13 2017
@@ -10,42 +10,42 @@ define i64 @S2_asr_i_p(i64 %a) {
%z = call i64 @llvm.hexagon.S2.asr.i.p(i64 %a, i32 0)
ret i64 %z
}
-; CHECK: = asr({{.*}}, #0)
+; CHECK: = asr({{.*}},#0)
declare i64 @llvm.hexagon.S2.lsr.i.p(i64, i32)
define i64 @S2_lsr_i_p(i64 %a) {
%z = call i64 @llvm.hexagon.S2.lsr.i.p(i64 %a, i32 0)
ret i64 %z
}
-; CHECK: = lsr({{.*}}, #0)
+; CHECK: = lsr({{.*}},#0)
declare i64 @llvm.hexagon.S2.asl.i.p(i64, i32)
define i64 @S2_asl_i_p(i64 %a) {
%z = call i64 @llvm.hexagon.S2.asl.i.p(i64 %a, i32 0)
ret i64 %z
}
-; CHECK: = asl({{.*}}, #0)
+; CHECK: = asl({{.*}},#0)
declare i32 @llvm.hexagon.S2.asr.i.r(i32, i32)
define i32 @S2_asr_i_r(i32 %a) {
%z = call i32 @llvm.hexagon.S2.asr.i.r(i32 %a, i32 0)
ret i32 %z
}
-; CHECK: = asr({{.*}}, #0)
+; CHECK: = asr({{.*}},#0)
declare i32 @llvm.hexagon.S2.lsr.i.r(i32, i32)
define i32 @S2_lsr_i_r(i32 %a) {
%z = call i32 @llvm.hexagon.S2.lsr.i.r(i32 %a, i32 0)
ret i32 %z
}
-; CHECK: = lsr({{.*}}, #0)
+; CHECK: = lsr({{.*}},#0)
declare i32 @llvm.hexagon.S2.asl.i.r(i32, i32)
define i32 @S2_asl_i_r(i32 %a) {
%z = call i32 @llvm.hexagon.S2.asl.i.r(i32 %a, i32 0)
ret i32 %z
}
-; CHECK: = asl({{.*}}, #0)
+; CHECK: = asl({{.*}},#0)
; Shift by immediate and accumulate
declare i64 @llvm.hexagon.S2.asr.i.p.nac(i64, i64, i32)
@@ -53,84 +53,84 @@ define i64 @S2_asr_i_p_nac(i64 %a, i64 %
%z = call i64 @llvm.hexagon.S2.asr.i.p.nac(i64 %a, i64 %b, i32 0)
ret i64 %z
}
-; CHECK: -= asr({{.*}}, #0)
+; CHECK: -= asr({{.*}},#0)
declare i64 @llvm.hexagon.S2.lsr.i.p.nac(i64, i64, i32)
define i64 @S2_lsr_i_p_nac(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.S2.lsr.i.p.nac(i64 %a, i64 %b, i32 0)
ret i64 %z
}
-; CHECK: -= lsr({{.*}}, #0)
+; CHECK: -= lsr({{.*}},#0)
declare i64 @llvm.hexagon.S2.asl.i.p.nac(i64, i64, i32)
define i64 @S2_asl_i_p_nac(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.S2.asl.i.p.nac(i64 %a, i64 %b, i32 0)
ret i64 %z
}
-; CHECK: -= asl({{.*}}, #0)
+; CHECK: -= asl({{.*}},#0)
declare i64 @llvm.hexagon.S2.asr.i.p.acc(i64, i64, i32)
define i64 @S2_asr_i_p_acc(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.S2.asr.i.p.acc(i64 %a, i64 %b, i32 0)
ret i64 %z
}
-; CHECK: += asr({{.*}}, #0)
+; CHECK: += asr({{.*}},#0)
declare i64 @llvm.hexagon.S2.lsr.i.p.acc(i64, i64, i32)
define i64 @S2_lsr_i_p_acc(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.S2.lsr.i.p.acc(i64 %a, i64 %b, i32 0)
ret i64 %z
}
-; CHECK: += lsr({{.*}}, #0)
+; CHECK: += lsr({{.*}},#0)
declare i64 @llvm.hexagon.S2.asl.i.p.acc(i64, i64, i32)
define i64 @S2_asl_i_p_acc(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.S2.asl.i.p.acc(i64 %a, i64 %b, i32 0)
ret i64 %z
}
-; CHECK: += asl({{.*}}, #0)
+; CHECK: += asl({{.*}},#0)
declare i32 @llvm.hexagon.S2.asr.i.r.nac(i32, i32, i32)
define i32 @S2_asr_i_r_nac(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.S2.asr.i.r.nac(i32 %a, i32 %b, i32 0)
ret i32 %z
}
-; CHECK: -= asr({{.*}}, #0)
+; CHECK: -= asr({{.*}},#0)
declare i32 @llvm.hexagon.S2.lsr.i.r.nac(i32, i32, i32)
define i32 @S2_lsr_i_r_nac(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.S2.lsr.i.r.nac(i32 %a, i32 %b, i32 0)
ret i32 %z
}
-; CHECK: -= lsr({{.*}}, #0)
+; CHECK: -= lsr({{.*}},#0)
declare i32 @llvm.hexagon.S2.asl.i.r.nac(i32, i32, i32)
define i32 @S2_asl_i_r_nac(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.S2.asl.i.r.nac(i32 %a, i32 %b, i32 0)
ret i32 %z
}
-; CHECK: -= asl({{.*}}, #0)
+; CHECK: -= asl({{.*}},#0)
declare i32 @llvm.hexagon.S2.asr.i.r.acc(i32, i32, i32)
define i32 @S2_asr_i_r_acc(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.S2.asr.i.r.acc(i32 %a, i32 %b, i32 0)
ret i32 %z
}
-; CHECK: += asr({{.*}}, #0)
+; CHECK: += asr({{.*}},#0)
declare i32 @llvm.hexagon.S2.lsr.i.r.acc(i32, i32, i32)
define i32 @S2_lsr_i_r_acc(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.S2.lsr.i.r.acc(i32 %a, i32 %b, i32 0)
ret i32 %z
}
-; CHECK: += lsr({{.*}}, #0)
+; CHECK: += lsr({{.*}},#0)
declare i32 @llvm.hexagon.S2.asl.i.r.acc(i32, i32, i32)
define i32 @S2_asl_i_r_acc(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.S2.asl.i.r.acc(i32 %a, i32 %b, i32 0)
ret i32 %z
}
-; CHECK: += asl({{.*}}, #0)
+; CHECK: += asl({{.*}},#0)
; Shift by immediate and add
declare i32 @llvm.hexagon.S4.addi.asl.ri(i32, i32, i32)
@@ -138,35 +138,35 @@ define i32 @S4_addi_asl_ri(i32 %a) {
%z = call i32 @llvm.hexagon.S4.addi.asl.ri(i32 0, i32 %a, i32 0)
ret i32 %z
}
-; CHECK: = add(#0, asl({{.*}}, #0))
+; CHECK: = add(#0,asl({{.*}},#0))
declare i32 @llvm.hexagon.S4.subi.asl.ri(i32, i32, i32)
define i32 @S4_subi_asl_ri(i32 %a) {
%z = call i32 @llvm.hexagon.S4.subi.asl.ri(i32 0, i32 %a, i32 0)
ret i32 %z
}
-; CHECK: = sub(#0, asl({{.*}}, #0))
+; CHECK: = sub(#0,asl({{.*}},#0))
declare i32 @llvm.hexagon.S4.addi.lsr.ri(i32, i32, i32)
define i32 @S4_addi_lsr_ri(i32 %a) {
%z = call i32 @llvm.hexagon.S4.addi.lsr.ri(i32 0, i32 %a, i32 0)
ret i32 %z
}
-; CHECK: = add(#0, lsr({{.*}}, #0))
+; CHECK: = add(#0,lsr({{.*}},#0))
declare i32 @llvm.hexagon.S4.subi.lsr.ri(i32, i32, i32)
define i32 @S4_subi_lsr_ri(i32 %a) {
%z = call i32 @llvm.hexagon.S4.subi.lsr.ri(i32 0, i32 %a, i32 0)
ret i32 %z
}
-; CHECK: = sub(#0, lsr({{.*}}, #0))
+; CHECK: = sub(#0,lsr({{.*}},#0))
declare i32 @llvm.hexagon.S2.addasl.rrri(i32, i32, i32)
define i32 @S2_addasl_rrri(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.S2.addasl.rrri(i32 %a, i32 %b, i32 0)
ret i32 %z
}
-; CHECK: = addasl({{.*}}, {{.*}}, #0)
+; CHECK: = addasl({{.*}},{{.*}},#0)
; Shift by immediate and logical
declare i64 @llvm.hexagon.S2.asr.i.p.and(i64, i64, i32)
@@ -174,140 +174,140 @@ define i64 @S2_asr_i_p_and(i64 %a, i64 %
%z = call i64 @llvm.hexagon.S2.asr.i.p.and(i64 %a, i64 %b, i32 0)
ret i64 %z
}
-; CHECK: &= asr({{.*}}, #0)
+; CHECK: &= asr({{.*}},#0)
declare i64 @llvm.hexagon.S2.lsr.i.p.and(i64, i64, i32)
define i64 @S2_lsr_i_p_and(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.S2.lsr.i.p.and(i64 %a, i64 %b, i32 0)
ret i64 %z
}
-; CHECK: {{.*}} &= lsr({{.*}}, #0)
+; CHECK: {{.*}} &= lsr({{.*}},#0)
declare i64 @llvm.hexagon.S2.asl.i.p.and(i64, i64, i32)
define i64 @S2_asl_i_p_and(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.S2.asl.i.p.and(i64 %a, i64 %b, i32 0)
ret i64 %z
}
-; CHECK: &= asl({{.*}}, #0)
+; CHECK: &= asl({{.*}},#0)
declare i64 @llvm.hexagon.S2.asr.i.p.or(i64, i64, i32)
define i64 @S2_asr_i_p_or(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.S2.asr.i.p.or(i64 %a, i64 %b, i32 0)
ret i64 %z
}
-; CHECK: |= asr({{.*}}, #0)
+; CHECK: |= asr({{.*}},#0)
declare i64 @llvm.hexagon.S2.lsr.i.p.or(i64, i64, i32)
define i64 @S2_lsr_i_p_or(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.S2.lsr.i.p.or(i64 %a, i64 %b, i32 0)
ret i64 %z
}
-; CHECK: |= lsr({{.*}}, #0)
+; CHECK: |= lsr({{.*}},#0)
declare i64 @llvm.hexagon.S2.asl.i.p.or(i64, i64, i32)
define i64 @S2_asl_i_p_or(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.S2.asl.i.p.or(i64 %a, i64 %b, i32 0)
ret i64 %z
}
-; CHECK: |= asl({{.*}}, #0)
+; CHECK: |= asl({{.*}},#0)
declare i64 @llvm.hexagon.S2.lsr.i.p.xacc(i64, i64, i32)
define i64 @S2_lsr_i_p_xacc(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.S2.lsr.i.p.xacc(i64 %a, i64 %b, i32 0)
ret i64 %z
}
-; CHECK: ^= lsr({{.*}}, #0)
+; CHECK: ^= lsr({{.*}},#0)
declare i64 @llvm.hexagon.S2.asl.i.p.xacc(i64, i64, i32)
define i64 @S2_asl_i_p_xacc(i64 %a, i64 %b) {
%z = call i64 @llvm.hexagon.S2.asl.i.p.xacc(i64 %a, i64 %b, i32 0)
ret i64 %z
}
-; CHECK: ^= asl({{.*}}, #0)
+; CHECK: ^= asl({{.*}},#0)
declare i32 @llvm.hexagon.S2.asr.i.r.and(i32, i32, i32)
define i32 @S2_asr_i_r_and(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.S2.asr.i.r.and(i32 %a, i32 %b, i32 0)
ret i32 %z
}
-; CHECK: &= asr({{.*}}, #0)
+; CHECK: &= asr({{.*}},#0)
declare i32 @llvm.hexagon.S2.lsr.i.r.and(i32, i32, i32)
define i32 @S2_lsr_i_r_and(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.S2.lsr.i.r.and(i32 %a, i32 %b, i32 0)
ret i32 %z
}
-; CHECK: &= lsr({{.*}}, #0)
+; CHECK: &= lsr({{.*}},#0)
declare i32 @llvm.hexagon.S2.asl.i.r.and(i32, i32, i32)
define i32 @S2_asl_i_r_and(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.S2.asl.i.r.and(i32 %a, i32 %b, i32 0)
ret i32 %z
}
-; CHECK: &= asl({{.*}}, #0)
+; CHECK: &= asl({{.*}},#0)
declare i32 @llvm.hexagon.S2.asr.i.r.or(i32, i32, i32)
define i32 @S2_asr_i_r_or(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.S2.asr.i.r.or(i32 %a, i32 %b, i32 0)
ret i32 %z
}
-; CHECK: |= asr({{.*}}, #0)
+; CHECK: |= asr({{.*}},#0)
declare i32 @llvm.hexagon.S2.lsr.i.r.or(i32, i32, i32)
define i32 @S2_lsr_i_r_or(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.S2.lsr.i.r.or(i32 %a, i32 %b, i32 0)
ret i32 %z
}
-; CHECK: |= lsr({{.*}}, #0)
+; CHECK: |= lsr({{.*}},#0)
declare i32 @llvm.hexagon.S2.asl.i.r.or(i32, i32, i32)
define i32 @S2_asl_i_r_or(i32%a, i32 %b) {
%z = call i32 @llvm.hexagon.S2.asl.i.r.or(i32 %a, i32 %b, i32 0)
ret i32 %z
}
-; CHECK: |= asl({{.*}}, #0)
+; CHECK: |= asl({{.*}},#0)
declare i32 @llvm.hexagon.S2.lsr.i.r.xacc(i32, i32, i32)
define i32 @S2_lsr_i_r_xacc(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.S2.lsr.i.r.xacc(i32%a, i32 %b, i32 0)
ret i32 %z
}
-; CHECK: ^= lsr({{.*}}, #0)
+; CHECK: ^= lsr({{.*}},#0)
declare i32 @llvm.hexagon.S2.asl.i.r.xacc(i32, i32, i32)
define i32 @S2_asl_i_r_xacc(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.S2.asl.i.r.xacc(i32 %a, i32 %b, i32 0)
ret i32 %z
}
-; CHECK: ^= asl({{.*}}, #0)
+; CHECK: ^= asl({{.*}},#0)
declare i32 @llvm.hexagon.S4.andi.asl.ri(i32, i32, i32)
define i32 @S4_andi_asl_ri(i32 %a) {
%z = call i32 @llvm.hexagon.S4.andi.asl.ri(i32 0, i32 %a, i32 0)
ret i32 %z
}
-; CHECK: = and(#0, asl({{.*}}, #0))
+; CHECK: = and(#0,asl({{.*}},#0))
declare i32 @llvm.hexagon.S4.ori.asl.ri(i32, i32, i32)
define i32 @S4_ori_asl_ri(i32 %a) {
%z = call i32 @llvm.hexagon.S4.ori.asl.ri(i32 0, i32 %a, i32 0)
ret i32 %z
}
-; CHECK: = or(#0, asl({{.*}}, #0))
+; CHECK: = or(#0,asl({{.*}},#0))
declare i32 @llvm.hexagon.S4.andi.lsr.ri(i32, i32, i32)
define i32 @S4_andi_lsr_ri(i32 %a) {
%z = call i32 @llvm.hexagon.S4.andi.lsr.ri(i32 0, i32 %a, i32 0)
ret i32 %z
}
-; CHECK: = and(#0, lsr({{.*}}, #0))
+; CHECK: = and(#0,lsr({{.*}},#0))
declare i32 @llvm.hexagon.S4.ori.lsr.ri(i32, i32, i32)
define i32 @S4_ori_lsr_ri(i32 %a) {
%z = call i32 @llvm.hexagon.S4.ori.lsr.ri(i32 0, i32 %a, i32 0)
ret i32 %z
}
-; CHECK: = or(#0, lsr({{.*}}, #0))
+; CHECK: = or(#0,lsr({{.*}},#0))
; Shift right by immediate with rounding
declare i64 @llvm.hexagon.S2.asr.i.p.rnd(i64, i32)
@@ -315,14 +315,14 @@ define i64 @S2_asr_i_p_rnd(i64 %a) {
%z = call i64 @llvm.hexagon.S2.asr.i.p.rnd(i64 %a, i32 0)
ret i64 %z
}
-; CHECK: = asr({{.*}}, #0):rnd
+; CHECK: = asr({{.*}},#0):rnd
declare i32 @llvm.hexagon.S2.asr.i.r.rnd(i32, i32)
define i32 @S2_asr_i_r_rnd(i32 %a) {
%z = call i32 @llvm.hexagon.S2.asr.i.r.rnd(i32 %a, i32 0)
ret i32 %z
}
-; CHECK: = asr({{.*}}, #0):rnd
+; CHECK: = asr({{.*}},#0):rnd
; Shift left by immediate with saturation
declare i32 @llvm.hexagon.S2.asl.i.r.sat(i32, i32)
@@ -330,7 +330,7 @@ define i32 @S2_asl_i_r_sat(i32 %a) {
%z = call i32 @llvm.hexagon.S2.asl.i.r.sat(i32 %a, i32 0)
ret i32 %z
}
-; CHECK: = asl({{.*}}, #0):sat
+; CHECK: = asl({{.*}},#0):sat
; Shift by register
declare i64 @llvm.hexagon.S2.asr.r.p(i64, i32)
@@ -338,63 +338,63 @@ define i64 @S2_asr_r_p(i64 %a, i32 %b) {
%z = call i64 @llvm.hexagon.S2.asr.r.p(i64 %a, i32 %b)
ret i64 %z
}
-; CHECK: = asr({{.*}}, {{.*}})
+; CHECK: = asr({{.*}},{{.*}})
declare i64 @llvm.hexagon.S2.lsr.r.p(i64, i32)
define i64 @S2_lsr_r_p(i64 %a, i32 %b) {
%z = call i64 @llvm.hexagon.S2.lsr.r.p(i64 %a, i32 %b)
ret i64 %z
}
-; CHECK: = lsr({{.*}}, {{.*}})
+; CHECK: = lsr({{.*}},{{.*}})
declare i64 @llvm.hexagon.S2.asl.r.p(i64, i32)
define i64 @S2_asl_r_p(i64 %a, i32 %b) {
%z = call i64 @llvm.hexagon.S2.asl.r.p(i64 %a, i32 %b)
ret i64 %z
}
-; CHECK: = asl({{.*}}, {{.*}})
+; CHECK: = asl({{.*}},{{.*}})
declare i64 @llvm.hexagon.S2.lsl.r.p(i64, i32)
define i64 @S2_lsl_r_p(i64 %a, i32 %b) {
%z = call i64 @llvm.hexagon.S2.lsl.r.p(i64 %a, i32 %b)
ret i64 %z
}
-; CHECK: = lsl({{.*}}, {{.*}})
+; CHECK: = lsl({{.*}},{{.*}})
declare i32 @llvm.hexagon.S2.asr.r.r(i32, i32)
define i32 @S2_asr_r_r(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.S2.asr.r.r(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = asr({{.*}}, {{.*}})
+; CHECK: = asr({{.*}},{{.*}})
declare i32 @llvm.hexagon.S2.lsr.r.r(i32, i32)
define i32 @S2_lsr_r_r(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.S2.lsr.r.r(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = lsr({{.*}}, {{.*}})
+; CHECK: = lsr({{.*}},{{.*}})
declare i32 @llvm.hexagon.S2.asl.r.r(i32, i32)
define i32 @S2_asl_r_r(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.S2.asl.r.r(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = asl({{.*}}, {{.*}})
+; CHECK: = asl({{.*}},{{.*}})
declare i32 @llvm.hexagon.S2.lsl.r.r(i32, i32)
define i32 @S2_lsl_r_r(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.S2.lsl.r.r(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = lsl({{.*}}, {{.*}})
+; CHECK: = lsl({{.*}},{{.*}})
declare i32 @llvm.hexagon.S4.lsli(i32, i32)
define i32 @S4_lsli(i32 %a) {
%z = call i32 @llvm.hexagon.S4.lsli(i32 0, i32 %a)
ret i32 %z
}
-; CHECK: = lsl(#0, {{.*}})
+; CHECK: = lsl(#0,{{.*}})
; Shift by register and accumulate
declare i64 @llvm.hexagon.S2.asr.r.p.nac(i64, i64, i32)
@@ -402,112 +402,112 @@ define i64 @S2_asr_r_p_nac(i64 %a, i64 %
%z = call i64 @llvm.hexagon.S2.asr.r.p.nac(i64 %a, i64 %b, i32 %c)
ret i64 %z
}
-; CHECK: -= asr({{.*}}, r4)
+; CHECK: -= asr({{.*}},r4)
declare i64 @llvm.hexagon.S2.lsr.r.p.nac(i64, i64, i32)
define i64 @S2_lsr_r_p_nac(i64 %a, i64 %b, i32 %c) {
%z = call i64 @llvm.hexagon.S2.lsr.r.p.nac(i64 %a, i64 %b, i32 %c)
ret i64 %z
}
-; CHECK: -= lsr({{.*}}, r4)
+; CHECK: -= lsr({{.*}},r4)
declare i64 @llvm.hexagon.S2.asl.r.p.nac(i64, i64, i32)
define i64 @S2_asl_r_p_nac(i64 %a, i64 %b, i32 %c) {
%z = call i64 @llvm.hexagon.S2.asl.r.p.nac(i64 %a, i64 %b, i32 %c)
ret i64 %z
}
-; CHECK: -= asl({{.*}}, r4)
+; CHECK: -= asl({{.*}},r4)
declare i64 @llvm.hexagon.S2.lsl.r.p.nac(i64, i64, i32)
define i64 @S2_lsl_r_p_nac(i64 %a, i64 %b, i32 %c) {
%z = call i64 @llvm.hexagon.S2.lsl.r.p.nac(i64 %a, i64 %b, i32 %c)
ret i64 %z
}
-; CHECK: -= lsl({{.*}}, r4)
+; CHECK: -= lsl({{.*}},r4)
declare i64 @llvm.hexagon.S2.asr.r.p.acc(i64, i64, i32)
define i64 @S2_asr_r_p_acc(i64 %a, i64 %b, i32 %c) {
%z = call i64 @llvm.hexagon.S2.asr.r.p.acc(i64 %a, i64 %b, i32 %c)
ret i64 %z
}
-; CHECK: += asr({{.*}}, r4)
+; CHECK: += asr({{.*}},r4)
declare i64 @llvm.hexagon.S2.lsr.r.p.acc(i64, i64, i32)
define i64 @S2_lsr_r_p_acc(i64 %a, i64 %b, i32 %c) {
%z = call i64 @llvm.hexagon.S2.lsr.r.p.acc(i64 %a, i64 %b, i32 %c)
ret i64 %z
}
-; CHECK: += lsr({{.*}}, r4)
+; CHECK: += lsr({{.*}},r4)
declare i64 @llvm.hexagon.S2.asl.r.p.acc(i64, i64, i32)
define i64 @S2_asl_r_p_acc(i64 %a, i64 %b, i32 %c) {
%z = call i64 @llvm.hexagon.S2.asl.r.p.acc(i64 %a, i64 %b, i32 %c)
ret i64 %z
}
-; CHECK: += asl({{.*}}, r4)
+; CHECK: += asl({{.*}},r4)
declare i64 @llvm.hexagon.S2.lsl.r.p.acc(i64, i64, i32)
define i64 @S2_lsl_r_p_acc(i64 %a, i64 %b, i32 %c) {
%z = call i64 @llvm.hexagon.S2.lsl.r.p.acc(i64 %a, i64 %b, i32 %c)
ret i64 %z
}
-; CHECK: += lsl({{.*}}, r4)
+; CHECK: += lsl({{.*}},r4)
declare i32 @llvm.hexagon.S2.asr.r.r.nac(i32, i32, i32)
define i32 @S2_asr_r_r_nac(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.S2.asr.r.r.nac(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: -= asr({{.*}}, {{.*}})
+; CHECK: -= asr({{.*}},{{.*}})
declare i32 @llvm.hexagon.S2.lsr.r.r.nac(i32, i32, i32)
define i32 @S2_lsr_r_r_nac(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.S2.lsr.r.r.nac(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: -= lsr({{.*}}, {{.*}})
+; CHECK: -= lsr({{.*}},{{.*}})
declare i32 @llvm.hexagon.S2.asl.r.r.nac(i32, i32, i32)
define i32 @S2_asl_r_r_nac(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.S2.asl.r.r.nac(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: -= asl({{.*}}, {{.*}})
+; CHECK: -= asl({{.*}},{{.*}})
declare i32 @llvm.hexagon.S2.lsl.r.r.nac(i32, i32, i32)
define i32 @S2_lsl_r_r_nac(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.S2.lsl.r.r.nac(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: -= lsl({{.*}}, {{.*}})
+; CHECK: -= lsl({{.*}},{{.*}})
declare i32 @llvm.hexagon.S2.asr.r.r.acc(i32, i32, i32)
define i32 @S2_asr_r_r_acc(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.S2.asr.r.r.acc(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: += asr({{.*}}, {{.*}})
+; CHECK: += asr({{.*}},{{.*}})
declare i32 @llvm.hexagon.S2.lsr.r.r.acc(i32, i32, i32)
define i32 @S2_lsr_r_r_acc(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.S2.lsr.r.r.acc(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: += lsr({{.*}}, {{.*}})
+; CHECK: += lsr({{.*}},{{.*}})
declare i32 @llvm.hexagon.S2.asl.r.r.acc(i32, i32, i32)
define i32 @S2_asl_r_r_acc(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.S2.asl.r.r.acc(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: += asl({{.*}}, {{.*}})
+; CHECK: += asl({{.*}},{{.*}})
declare i32 @llvm.hexagon.S2.lsl.r.r.acc(i32, i32, i32)
define i32 @S2_lsl_r_r_acc(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.S2.lsl.r.r.acc(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: += lsl({{.*}}, {{.*}})
+; CHECK: += lsl({{.*}},{{.*}})
; Shift by register and logical
declare i64 @llvm.hexagon.S2.asr.r.p.or(i64, i64, i32)
@@ -515,112 +515,112 @@ define i64 @S2_asr_r_p_or(i64 %a, i64 %b
%z = call i64 @llvm.hexagon.S2.asr.r.p.or(i64 %a, i64 %b, i32 %c)
ret i64 %z
}
-; CHECK: |= asr({{.*}}, r4)
+; CHECK: |= asr({{.*}},r4)
declare i64 @llvm.hexagon.S2.lsr.r.p.or(i64, i64, i32)
define i64 @S2_lsr_r_p_or(i64 %a, i64 %b, i32 %c) {
%z = call i64 @llvm.hexagon.S2.lsr.r.p.or(i64 %a, i64 %b, i32 %c)
ret i64 %z
}
-; CHECK: |= lsr({{.*}}, r4)
+; CHECK: |= lsr({{.*}},r4)
declare i64 @llvm.hexagon.S2.asl.r.p.or(i64, i64, i32)
define i64 @S2_asl_r_p_or(i64 %a, i64 %b, i32 %c) {
%z = call i64 @llvm.hexagon.S2.asl.r.p.or(i64 %a, i64 %b, i32 %c)
ret i64 %z
}
-; CHECK: |= asl({{.*}}, r4)
+; CHECK: |= asl({{.*}},r4)
declare i64 @llvm.hexagon.S2.lsl.r.p.or(i64, i64, i32)
define i64 @S2_lsl_r_p_or(i64 %a, i64 %b, i32 %c) {
%z = call i64 @llvm.hexagon.S2.lsl.r.p.or(i64 %a, i64 %b, i32 %c)
ret i64 %z
}
-; CHECK: |= lsl({{.*}}, r4)
+; CHECK: |= lsl({{.*}},r4)
declare i64 @llvm.hexagon.S2.asr.r.p.and(i64, i64, i32)
define i64 @S2_asr_r_p_and(i64 %a, i64 %b, i32 %c) {
%z = call i64 @llvm.hexagon.S2.asr.r.p.and(i64 %a, i64 %b, i32 %c)
ret i64 %z
}
-; CHECK: &= asr({{.*}}, r4)
+; CHECK: &= asr({{.*}},r4)
declare i64 @llvm.hexagon.S2.lsr.r.p.and(i64, i64, i32)
define i64 @S2_lsr_r_p_and(i64 %a, i64 %b, i32 %c) {
%z = call i64 @llvm.hexagon.S2.lsr.r.p.and(i64 %a, i64 %b, i32 %c)
ret i64 %z
}
-; CHECK: &= lsr({{.*}}, r4)
+; CHECK: &= lsr({{.*}},r4)
declare i64 @llvm.hexagon.S2.asl.r.p.and(i64, i64, i32)
define i64 @S2_asl_r_p_and(i64 %a, i64 %b, i32 %c) {
%z = call i64 @llvm.hexagon.S2.asl.r.p.and(i64 %a, i64 %b, i32 %c)
ret i64 %z
}
-; CHECK: &= asl({{.*}}, r4)
+; CHECK: &= asl({{.*}},r4)
declare i64 @llvm.hexagon.S2.lsl.r.p.and(i64, i64, i32)
define i64 @S2_lsl_r_p_and(i64 %a, i64 %b, i32 %c) {
%z = call i64 @llvm.hexagon.S2.lsl.r.p.and(i64 %a, i64 %b, i32 %c)
ret i64 %z
}
-; CHECK: &= lsl({{.*}}, r4)
+; CHECK: &= lsl({{.*}},r4)
declare i32 @llvm.hexagon.S2.asr.r.r.or(i32, i32, i32)
define i32 @S2_asr_r_r_or(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.S2.asr.r.r.or(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: |= asr({{.*}}, {{.*}})
+; CHECK: |= asr({{.*}},{{.*}})
declare i32 @llvm.hexagon.S2.lsr.r.r.or(i32, i32, i32)
define i32 @S2_lsr_r_r_or(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.S2.lsr.r.r.or(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: |= lsr({{.*}}, {{.*}})
+; CHECK: |= lsr({{.*}},{{.*}})
declare i32 @llvm.hexagon.S2.asl.r.r.or(i32, i32, i32)
define i32 @S2_asl_r_r_or(i32%a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.S2.asl.r.r.or(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: |= asl({{.*}}, {{.*}})
+; CHECK: |= asl({{.*}},{{.*}})
declare i32 @llvm.hexagon.S2.lsl.r.r.or(i32, i32, i32)
define i32 @S2_lsl_r_r_or(i32%a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.S2.lsl.r.r.or(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: |= lsl({{.*}}, {{.*}})
+; CHECK: |= lsl({{.*}},{{.*}})
declare i32 @llvm.hexagon.S2.asr.r.r.and(i32, i32, i32)
define i32 @S2_asr_r_r_and(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.S2.asr.r.r.and(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: &= asr({{.*}}, {{.*}})
+; CHECK: &= asr({{.*}},{{.*}})
declare i32 @llvm.hexagon.S2.lsr.r.r.and(i32, i32, i32)
define i32 @S2_lsr_r_r_and(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.S2.lsr.r.r.and(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: &= lsr({{.*}}, {{.*}})
+; CHECK: &= lsr({{.*}},{{.*}})
declare i32 @llvm.hexagon.S2.asl.r.r.and(i32, i32, i32)
define i32 @S2_asl_r_r_and(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.S2.asl.r.r.and(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: &= asl({{.*}}, {{.*}})
+; CHECK: &= asl({{.*}},{{.*}})
declare i32 @llvm.hexagon.S2.lsl.r.r.and(i32, i32, i32)
define i32 @S2_lsl_r_r_and(i32 %a, i32 %b, i32 %c) {
%z = call i32 @llvm.hexagon.S2.lsl.r.r.and(i32 %a, i32 %b, i32 %c)
ret i32 %z
}
-; CHECK: &= lsl({{.*}}, {{.*}})
+; CHECK: &= lsl({{.*}},{{.*}})
; Shift by register with saturation
declare i32 @llvm.hexagon.S2.asr.r.r.sat(i32, i32)
@@ -628,14 +628,14 @@ define i32 @S2_asr_r_r_sat(i32 %a, i32 %
%z = call i32 @llvm.hexagon.S2.asr.r.r.sat(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = asr({{.*}}, {{.*}}):sat
+; CHECK: = asr({{.*}},{{.*}}):sat
declare i32 @llvm.hexagon.S2.asl.r.r.sat(i32, i32)
define i32 @S2_asl_r_r_sat(i32 %a, i32 %b) {
%z = call i32 @llvm.hexagon.S2.asl.r.r.sat(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: = asl({{.*}}, {{.*}}):sat
+; CHECK: = asl({{.*}},{{.*}}):sat
; Vector shift halfwords by immediate
declare i64 @llvm.hexagon.S2.asr.i.vh(i64, i32)
@@ -643,21 +643,21 @@ define i64 @S2_asr_i_vh(i64 %a) {
%z = call i64 @llvm.hexagon.S2.asr.i.vh(i64 %a, i32 0)
ret i64 %z
}
-; CHECK: = vasrh({{.*}}, #0)
+; CHECK: = vasrh({{.*}},#0)
declare i64 @llvm.hexagon.S2.lsr.i.vh(i64, i32)
define i64 @S2_lsr_i_vh(i64 %a) {
%z = call i64 @llvm.hexagon.S2.lsr.i.vh(i64 %a, i32 0)
ret i64 %z
}
-; CHECK: = vlsrh({{.*}}, #0)
+; CHECK: = vlsrh({{.*}},#0)
declare i64 @llvm.hexagon.S2.asl.i.vh(i64, i32)
define i64 @S2_asl_i_vh(i64 %a) {
%z = call i64 @llvm.hexagon.S2.asl.i.vh(i64 %a, i32 0)
ret i64 %z
}
-; CHECK: = vaslh({{.*}}, #0)
+; CHECK: = vaslh({{.*}},#0)
; Vector shift halfwords by register
declare i64 @llvm.hexagon.S2.asr.r.vh(i64, i32)
@@ -665,28 +665,28 @@ define i64 @S2_asr_r_vh(i64 %a, i32 %b)
%z = call i64 @llvm.hexagon.S2.asr.r.vh(i64 %a, i32 %b)
ret i64 %z
}
-; CHECK: = vasrh({{.*}}, {{.*}})
+; CHECK: = vasrh({{.*}},{{.*}})
declare i64 @llvm.hexagon.S2.lsr.r.vh(i64, i32)
define i64 @S2_lsr_r_vh(i64 %a, i32 %b) {
%z = call i64 @llvm.hexagon.S2.lsr.r.vh(i64 %a, i32 %b)
ret i64 %z
}
-; CHECK: = vlsrh({{.*}}, {{.*}})
+; CHECK: = vlsrh({{.*}},{{.*}})
declare i64 @llvm.hexagon.S2.asl.r.vh(i64, i32)
define i64 @S2_asl_r_vh(i64 %a, i32 %b) {
%z = call i64 @llvm.hexagon.S2.asl.r.vh(i64 %a, i32 %b)
ret i64 %z
}
-; CHECK: = vaslh({{.*}}, {{.*}})
+; CHECK: = vaslh({{.*}},{{.*}})
declare i64 @llvm.hexagon.S2.lsl.r.vh(i64, i32)
define i64 @S2_lsl_r_vh(i64 %a, i32 %b) {
%z = call i64 @llvm.hexagon.S2.lsl.r.vh(i64 %a, i32 %b)
ret i64 %z
}
-; CHECK: = vlslh({{.*}}, {{.*}})
+; CHECK: = vlslh({{.*}},{{.*}})
; Vector shift words by immediate
declare i64 @llvm.hexagon.S2.asr.i.vw(i64, i32)
@@ -694,21 +694,21 @@ define i64 @S2_asr_i_vw(i64 %a) {
%z = call i64 @llvm.hexagon.S2.asr.i.vw(i64 %a, i32 0)
ret i64 %z
}
-; CHECK: = vasrw({{.*}}, #0)
+; CHECK: = vasrw({{.*}},#0)
declare i64 @llvm.hexagon.S2.lsr.i.vw(i64, i32)
define i64 @S2_lsr_i_vw(i64 %a) {
%z = call i64 @llvm.hexagon.S2.lsr.i.vw(i64 %a, i32 0)
ret i64 %z
}
-; CHECK: = vlsrw({{.*}}, #0)
+; CHECK: = vlsrw({{.*}},#0)
declare i64 @llvm.hexagon.S2.asl.i.vw(i64, i32)
define i64 @S2_asl_i_vw(i64 %a) {
%z = call i64 @llvm.hexagon.S2.asl.i.vw(i64 %a, i32 0)
ret i64 %z
}
-; CHECK: = vaslw({{.*}}, #0)
+; CHECK: = vaslw({{.*}},#0)
; Vector shift words by with truncate and pack
declare i32 @llvm.hexagon.S2.asr.i.svw.trun(i64, i32)
@@ -716,11 +716,11 @@ define i32 @S2_asr_i_svw_trun(i64 %a) {
%z = call i32 @llvm.hexagon.S2.asr.i.svw.trun(i64 %a, i32 0)
ret i32 %z
}
-; CHECK: = vasrw({{.*}}, #0)
+; CHECK: = vasrw({{.*}},#0)
declare i32 @llvm.hexagon.S2.asr.r.svw.trun(i64, i32)
define i32 @S2_asr_r_svw_trun(i64 %a, i32 %b) {
%z = call i32 @llvm.hexagon.S2.asr.r.svw.trun(i64 %a, i32 %b)
ret i32 %z
}
-; CHECK: = vasrw({{.*}}, {{.*}})
+; CHECK: = vasrw({{.*}},{{.*}})
Modified: llvm/trunk/test/CodeGen/Hexagon/newvalueSameReg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/newvalueSameReg.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/newvalueSameReg.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/newvalueSameReg.ll Fri Feb 10 09:33:13 2017
@@ -12,8 +12,8 @@
; Test that we don't generate a new value compare if the operands are
; the same register.
-; CHECK-NOT: cmp.eq([[REG0:(r[0-9]+)]].new, [[REG0]])
-; CHECK: cmp.eq([[REG1:(r[0-9]+)]], [[REG1]])
+; CHECK-NOT: cmp.eq([[REG0:(r[0-9]+)]].new,[[REG0]])
+; CHECK: cmp.eq([[REG1:(r[0-9]+)]],[[REG1]])
; Function Attrs: nounwind
declare void @fprintf(%struct._Dnk_filet.1* nocapture, i8* nocapture readonly, ...) #1
Modified: llvm/trunk/test/CodeGen/Hexagon/newvaluejump.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/newvaluejump.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/newvaluejump.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/newvaluejump.ll Fri Feb 10 09:33:13 2017
@@ -6,7 +6,7 @@
define i32 @foo(i32 %a) nounwind {
entry:
-; CHECK: if (cmp.eq(r{{[0-9]+}}.new, #0)) jump{{.}}
+; CHECK: if (cmp.eq(r{{[0-9]+}}.new,#0)) jump{{.}}
%addr1 = alloca i32, align 4
%addr2 = alloca i32, align 4
%0 = load i32, i32* @i, align 4
Modified: llvm/trunk/test/CodeGen/Hexagon/newvaluejump2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/newvaluejump2.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/newvaluejump2.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/newvaluejump2.ll Fri Feb 10 09:33:13 2017
@@ -6,7 +6,7 @@
@Reg = common global i32 0, align 4
define i32 @main() nounwind {
entry:
-; CHECK: if (cmp.gt(r{{[0-9]+}}, r{{[0-9]+}}.new)) jump:{{[t|nt]}} .LBB{{[0-9]+}}_{{[0-9]+}}
+; CHECK: if (cmp.gt(r{{[0-9]+}},r{{[0-9]+}}.new)) jump:{{[t|nt]}} .LBB{{[0-9]+}}_{{[0-9]+}}
%Reg2 = alloca i32, align 4
%0 = load i32, i32* %Reg2, align 4
%1 = load i32, i32* @Reg, align 4
Modified: llvm/trunk/test/CodeGen/Hexagon/opt-addr-mode.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/opt-addr-mode.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/opt-addr-mode.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/opt-addr-mode.ll Fri Feb 10 09:33:13 2017
@@ -2,10 +2,10 @@
; RUN: llc -march=hexagon -hexagon-small-data-threshold=0 -disable-hexagon-amodeopt=0 -hexagon-amode-growth-limit=4 < %s | FileCheck %s --check-prefix=CHECK-AMODE
; CHECK-NO-AMODE: [[REG0:(r[0-9]+)]] = ##global_2
-; CHECK-NO-AMODE: memw([[REG0]] + {{.*}}<<#2) =
+; CHECK-NO-AMODE: memw([[REG0]]+{{.*}}<<#2) =
; CHECK-AMODE: [[REG1:(r[0-9]+)]] = memw(##global_1)
-; CHECK-AMODE: memw([[REG1]]<<#2 + ##global_2) =
+; CHECK-AMODE: memw([[REG1]]<<#2+##global_2) =
@global_1 = external global i32, align 4
@global_2 = external global [128 x i32], align 8
Modified: llvm/trunk/test/CodeGen/Hexagon/opt-fabs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/opt-fabs.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/opt-fabs.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/opt-fabs.ll Fri Feb 10 09:33:13 2017
@@ -1,7 +1,7 @@
; RUN: llc -mtriple=hexagon-unknown-elf -mcpu=hexagonv5 -hexagon-bit=0 < %s | FileCheck %s
; Optimize fabsf to clrbit in V5.
-; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #31)
+; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}},#31)
define float @my_fabsf(float %x) nounwind {
entry:
Modified: llvm/trunk/test/CodeGen/Hexagon/opt-fneg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/opt-fneg.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/opt-fneg.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/opt-fneg.ll Fri Feb 10 09:33:13 2017
@@ -3,7 +3,7 @@
define float @foo(float %x) nounwind {
entry:
-; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #31)
+; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}},#31)
%x.addr = alloca float, align 4
store float %x, float* %x.addr, align 4
%0 = load float, float* %x.addr, align 4
@@ -13,14 +13,14 @@ entry:
define float @bar(float %x) nounwind {
entry:
-; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #31)
+; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}},#31)
%sub = fsub float -0.000000e+00, %x
ret float %sub
}
define float @baz(float %x) nounwind {
entry:
-; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #31)
+; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}},#31)
%conv1 = fmul float %x, -1.000000e+00
ret float %conv1
}
Modified: llvm/trunk/test/CodeGen/Hexagon/opt-spill-volatile.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/opt-spill-volatile.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/opt-spill-volatile.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/opt-spill-volatile.ll Fri Feb 10 09:33:13 2017
@@ -6,7 +6,7 @@ target triple = "hexagon"
; CHECK-LABEL: foo
; CHECK: memw(r29+#4) =
-; CHECK: = memw(r29 + #4)
+; CHECK: = memw(r29+#4)
define i32 @foo(i32 %a) #0 {
entry:
%x = alloca i32, align 4
Modified: llvm/trunk/test/CodeGen/Hexagon/pic-local.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/pic-local.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/pic-local.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/pic-local.ll Fri Feb 10 09:33:13 2017
@@ -9,11 +9,11 @@ define internal void @f2() {
}
define void()* @get_f1() {
- ; CHECK: r0 = add(pc, ##.Lf1 at PCREL)
+ ; CHECK: r0 = add(pc,##.Lf1 at PCREL)
ret void()* @f1
}
define void()* @get_f2() {
- ; CHECK: r0 = add(pc, ##f2 at PCREL)
+ ; CHECK: r0 = add(pc,##f2 at PCREL)
ret void()* @f2
}
Modified: llvm/trunk/test/CodeGen/Hexagon/pic-simple.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/pic-simple.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/pic-simple.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/pic-simple.ll Fri Feb 10 09:33:13 2017
@@ -1,8 +1,8 @@
; RUN: llc -mtriple=hexagon-- -mcpu=hexagonv5 -relocation-model=pic < %s | FileCheck %s
-; CHECK: r{{[0-9]+}} = add({{pc|PC}}, ##_GLOBAL_OFFSET_TABLE_ at PCREL)
-; CHECK: r{{[0-9]+}} = memw(r{{[0-9]+}}{{.*}}+{{.*}}##src at GOT)
-; CHECK: r{{[0-9]+}} = memw(r{{[0-9]+}}{{.*}}+{{.*}}##dst at GOT)
+; CHECK: r{{[0-9]+}} = add({{pc|PC}},##_GLOBAL_OFFSET_TABLE_ at PCREL)
+; CHECK: r{{[0-9]+}} = memw(r{{[0-9]+}}+##src at GOT)
+; CHECK: r{{[0-9]+}} = memw(r{{[0-9]+}}+##dst at GOT)
@dst = external global i32
@src = external global i32
Modified: llvm/trunk/test/CodeGen/Hexagon/pic-static.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/pic-static.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/pic-static.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/pic-static.ll Fri Feb 10 09:33:13 2017
@@ -1,8 +1,8 @@
; RUN: llc -mtriple=hexagon-- -mcpu=hexagonv5 -relocation-model=pic < %s | FileCheck %s
-; CHECK-DAG: r{{[0-9]+}} = add({{pc|PC}}, ##_GLOBAL_OFFSET_TABLE_ at PCREL)
-; CHECK-DAG: r{{[0-9]+}} = add({{pc|PC}}, ##x at PCREL)
-; CHECK: r{{[0-9]+}} = memw(r{{[0-9]+}}{{.*}}+{{.*}}##bar at GOT)
+; CHECK-DAG: r{{[0-9]+}} = add({{pc|PC}},##_GLOBAL_OFFSET_TABLE_ at PCREL)
+; CHECK-DAG: r{{[0-9]+}} = add({{pc|PC}},##x at PCREL)
+; CHECK: r{{[0-9]+}} = memw(r{{[0-9]+}}+##bar at GOT)
@x = internal global i32 9, align 4
@bar = external global i32*
Modified: llvm/trunk/test/CodeGen/Hexagon/predicate-logical.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/predicate-logical.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/predicate-logical.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/predicate-logical.ll Fri Feb 10 09:33:13 2017
@@ -1,5 +1,5 @@
; RUN: llc -O2 -march=hexagon < %s | FileCheck %s
-; CHECK: p{{[0-9]}} = or(p{{[0-9]}}, and(p{{[0-9]}}, p{{[0-9]}}))
+; CHECK: p{{[0-9]}} = or(p{{[0-9]}},and(p{{[0-9]}},p{{[0-9]}}))
target triple = "hexagon"
Modified: llvm/trunk/test/CodeGen/Hexagon/predicate-rcmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/predicate-rcmp.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/predicate-rcmp.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/predicate-rcmp.ll Fri Feb 10 09:33:13 2017
@@ -1,5 +1,5 @@
; RUN: llc -O2 -march=hexagon < %s | FileCheck %s
-; CHECK: cmp.eq(r{{[0-9]+}}, #0)
+; CHECK: cmp.eq(r{{[0-9]+}},#0)
; Check that the result of the builtin is not stored directly, i.e. that
; there is an instruction that converts it to {0,1} from {0,-1}. Right now
; the instruction is "r4 = !cmp.eq(r0, #0)".
Modified: llvm/trunk/test/CodeGen/Hexagon/ret-struct-by-val.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/ret-struct-by-val.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/ret-struct-by-val.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/ret-struct-by-val.ll Fri Feb 10 09:33:13 2017
@@ -1,5 +1,5 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
-; CHECK: r0 = add(r0, r1)
+; CHECK: r0 = add(r0,r1)
; Allow simple structures to be returned by value.
Modified: llvm/trunk/test/CodeGen/Hexagon/signed_immediates.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/signed_immediates.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/signed_immediates.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/signed_immediates.ll Fri Feb 10 09:33:13 2017
@@ -33,7 +33,7 @@ define i64* @foo4(i64* %a, i64 %b) {
}
; s6Ext
-; CHECK: if (p0.new) memw(r0+#0)=#-1
+; CHECK: if (p0.new) memw(r0+#0) = #-1
define void @foo5(i32* %a, i1 %b) {
br i1 %b, label %x, label %y
x:
@@ -44,7 +44,7 @@ y:
}
; s10Ext
-; CHECK: p0 = cmp.eq(r0, #-1)
+; CHECK: p0 = cmp.eq(r0,#-1)
define i1 @foo7(i32 %a) {
%b = icmp eq i32 %a, -1
ret i1 %b
@@ -96,4 +96,4 @@ y:
; CHECK: r0 = #-2
define i32 @foo13() {
ret i32 -2
-}
\ No newline at end of file
+}
Modified: llvm/trunk/test/CodeGen/Hexagon/stack-align1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/stack-align1.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/stack-align1.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/stack-align1.ll Fri Feb 10 09:33:13 2017
@@ -1,7 +1,7 @@
; RUN: llc -O0 -march=hexagon < %s | FileCheck %s
-; CHECK: and(r29, #-32)
-; CHECK-DAG: add(r29, #0)
-; CHECK-DAG: add(r29, #28)
+; CHECK: and(r29,#-32)
+; CHECK-DAG: add(r29,#0)
+; CHECK-DAG: add(r29,#28)
target triple = "hexagon-unknown-unknown"
Modified: llvm/trunk/test/CodeGen/Hexagon/stack-align2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/stack-align2.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/stack-align2.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/stack-align2.ll Fri Feb 10 09:33:13 2017
@@ -1,9 +1,9 @@
; RUN: llc -O0 -march=hexagon < %s | FileCheck %s
-; CHECK: and(r29, #-128)
-; CHECK-DAG: add(r29, #0)
-; CHECK-DAG: add(r29, #64)
-; CHECK-DAG: add(r29, #96)
-; CHECK-DAG: add(r29, #124)
+; CHECK: and(r29,#-128)
+; CHECK-DAG: add(r29,#0)
+; CHECK-DAG: add(r29,#64)
+; CHECK-DAG: add(r29,#96)
+; CHECK-DAG: add(r29,#124)
target triple = "hexagon-unknown-unknown"
Modified: llvm/trunk/test/CodeGen/Hexagon/stack-alloca1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/stack-alloca1.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/stack-alloca1.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/stack-alloca1.ll Fri Feb 10 09:33:13 2017
@@ -1,5 +1,5 @@
; RUN: llc -O0 -march=hexagon < %s | FileCheck %s
-; CHECK: sub(r29, r[[REG:[0-9]+]])
+; CHECK: sub(r29,r[[REG:[0-9]+]])
; CHECK: r29 = r[[REG]]
target triple = "hexagon-unknown-unknown"
Modified: llvm/trunk/test/CodeGen/Hexagon/stack-alloca2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/stack-alloca2.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/stack-alloca2.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/stack-alloca2.ll Fri Feb 10 09:33:13 2017
@@ -1,8 +1,8 @@
; RUN: llc -O0 -march=hexagon < %s | FileCheck %s
-; CHECK-DAG: r[[AP:[0-9]+]] = and(r30, #-32)
-; CHECK-DAG: r1 = add(r[[AP]], #-32)
+; CHECK-DAG: r[[AP:[0-9]+]] = and(r30,#-32)
+; CHECK-DAG: r1 = add(r[[AP]],#-32)
-; CHECK-DAG: sub(r29, r[[SP:[0-9]+]])
+; CHECK-DAG: sub(r29,r[[SP:[0-9]+]])
; CHECK-DAG: r29 = r[[SP]]
target triple = "hexagon-unknown-unknown"
Modified: llvm/trunk/test/CodeGen/Hexagon/store-shift.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/store-shift.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/store-shift.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/store-shift.ll Fri Feb 10 09:33:13 2017
@@ -1,12 +1,12 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; CHECK-DAG: r[[BASE:[0-9]+]] += add
-; CHECK-DAG: r[[IDX0:[0-9]+]] = add(r2, #5)
-; CHECK-DAG: r[[IDX1:[0-9]+]] = add(r2, #6)
-; CHECK-DAG: memw(r0 + r[[IDX0]]<<#2) = r3
-; CHECK-DAG: memw(r0 + r[[IDX1]]<<#2) = r3
-; CHECK-DAG: memw(r[[BASE]] + r[[IDX0]]<<#2) = r[[IDX0]]
-; CHECK-DAG: memw(r[[BASE]] + r[[IDX1]]<<#2) = r[[IDX0]]
+; CHECK-DAG: r[[IDX0:[0-9]+]] = add(r2,#5)
+; CHECK-DAG: r[[IDX1:[0-9]+]] = add(r2,#6)
+; CHECK-DAG: memw(r0+r[[IDX0]]<<#2) = r3
+; CHECK-DAG: memw(r0+r[[IDX1]]<<#2) = r3
+; CHECK-DAG: memw(r[[BASE]]+r[[IDX0]]<<#2) = r[[IDX0]]
+; CHECK-DAG: memw(r[[BASE]]+r[[IDX1]]<<#2) = r[[IDX0]]
target triple = "hexagon"
Modified: llvm/trunk/test/CodeGen/Hexagon/sube.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/sube.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/sube.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/sube.ll Fri Feb 10 09:33:13 2017
@@ -1,13 +1,13 @@
; RUN: llc -march=hexagon -disable-hsdr -hexagon-expand-condsets=0 -hexagon-bit=0 -disable-post-ra < %s | FileCheck %s
-; CHECK: r{{[0-9]+:[0-9]+}} = combine(#0, #0)
-; CHECK: r{{[0-9]+:[0-9]+}} = combine(#0, #1)
-; CHECK: p{{[0-9]+}} = cmp.gtu(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}})
-; CHECK: r{{[0-9]+:[0-9]+}} = sub(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}})
-; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}})
-; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}})
-; CHECK: r{{[0-9]+:[0-9]+}} = sub(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}})
-; CHECK: r{{[0-9]+:[0-9]+}} = combine(r{{[0-9]+}}, r{{[0-9]+}})
+; CHECK: r{{[0-9]+:[0-9]+}} = combine(#0,#0)
+; CHECK: r{{[0-9]+:[0-9]+}} = combine(#0,#1)
+; CHECK: p{{[0-9]+}} = cmp.gtu(r{{[0-9]+:[0-9]+}},r{{[0-9]+:[0-9]+}})
+; CHECK: r{{[0-9]+:[0-9]+}} = sub(r{{[0-9]+:[0-9]+}},r{{[0-9]+:[0-9]+}})
+; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}},r{{[0-9]+}},r{{[0-9]+}})
+; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}},r{{[0-9]+}},r{{[0-9]+}})
+; CHECK: r{{[0-9]+:[0-9]+}} = sub(r{{[0-9]+:[0-9]+}},r{{[0-9]+:[0-9]+}})
+; CHECK: r{{[0-9]+:[0-9]+}} = combine(r{{[0-9]+}},r{{[0-9]+}})
define void @check_sube_subc(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
entry:
Modified: llvm/trunk/test/CodeGen/Hexagon/subi-asl.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/subi-asl.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/subi-asl.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/subi-asl.ll Fri Feb 10 09:33:13 2017
@@ -3,11 +3,11 @@
; Check if S4_subi_asl_ri is being generated correctly.
; CHECK-LABEL: yes_sub_asl
-; CHECK: [[REG1:(r[0-9]+)]] = sub(#0, asl([[REG1]], #1))
+; CHECK: [[REG1:(r[0-9]+)]] = sub(#0,asl([[REG1]],#1))
; CHECK-LABEL: no_sub_asl
-; CHECK: [[REG2:(r[0-9]+)]] = asl(r{{[0-9]+}}, #1)
-; CHECK: r{{[0-9]+}} = sub([[REG2]], r{{[0-9]+}})
+; CHECK: [[REG2:(r[0-9]+)]] = asl(r{{[0-9]+}},#1)
+; CHECK: r{{[0-9]+}} = sub([[REG2]],r{{[0-9]+}})
%struct.rtx_def = type { i16, i8 }
Modified: llvm/trunk/test/CodeGen/Hexagon/swp-const-tc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/swp-const-tc.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/swp-const-tc.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/swp-const-tc.ll Fri Feb 10 09:33:13 2017
@@ -4,7 +4,7 @@
; of computing a new LC0 value.
; CHECK-LABEL: @test
-; CHECK: loop0(.LBB0_1, #998)
+; CHECK: loop0(.LBB0_1,#998)
define i32 @test(i32* %A, i32* %B, i32 %count) {
entry:
Modified: llvm/trunk/test/CodeGen/Hexagon/swp-matmul-bitext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/swp-matmul-bitext.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/swp-matmul-bitext.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/swp-matmul-bitext.ll Fri Feb 10 09:33:13 2017
@@ -11,7 +11,7 @@
; CHECK: [[REG0:(r[0-9]+)]] = memh
; CHECK: [[REG1:(r[0-9]+)]] = memh
; CHECK: += mpyi
-; CHECK: [[REG2]] = mpyi([[REG0]], [[REG1]])
+; CHECK: [[REG2]] = mpyi([[REG0]],[[REG1]])
; CHECK: endloop0
%union_h2_sem_t = type { i32 }
Modified: llvm/trunk/test/CodeGen/Hexagon/swp-max.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/swp-max.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/swp-max.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/swp-max.ll Fri Feb 10 09:33:13 2017
@@ -15,8 +15,8 @@ for.body.preheader:
; CHECK: loop0(.LBB0_[[LOOP:.]],
; CHECK: .LBB0_[[LOOP]]:
-; CHECK: [[REG1:(r[0-9]+)]] = max(r{{[0-9]+}}, [[REG1]])
-; CHECK: [[REG0:(r[0-9]+)]] = add([[REG2:(r[0-9]+)]], [[REG0]])
+; CHECK: [[REG1:(r[0-9]+)]] = max(r{{[0-9]+}},[[REG1]])
+; CHECK: [[REG0:(r[0-9]+)]] = add([[REG2:(r[0-9]+)]],[[REG0]])
; CHECK: [[REG2]] = memw
; CHECK: endloop0
Modified: llvm/trunk/test/CodeGen/Hexagon/swp-multi-loops.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/swp-multi-loops.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/swp-multi-loops.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/swp-multi-loops.ll Fri Feb 10 09:33:13 2017
@@ -5,15 +5,15 @@
; Check if the first loop is pipelined.
; CHECK: loop0(.LBB0_[[LOOP:.]],
; CHECK: .LBB0_[[LOOP]]:
-; CHECK: add(r{{[0-9]+}}, r{{[0-9]+}})
-; CHECK-NEXT: memw(r{{[0-9]+}}{{.*}}++{{.*}}#4)
+; CHECK: add(r{{[0-9]+}},r{{[0-9]+}})
+; CHECK-NEXT: memw(r{{[0-9]+}}++#4)
; CHECK-NEXT: endloop0
; Check if the second loop is pipelined.
; CHECK: loop0(.LBB0_[[LOOP:.]],
; CHECK: .LBB0_[[LOOP]]:
-; CHECK: add(r{{[0-9]+}}, r{{[0-9]+}})
-; CHECK-NEXT: memw(r{{[0-9]+}}{{.*}}++{{.*}}#4)
+; CHECK: add(r{{[0-9]+}},r{{[0-9]+}})
+; CHECK-NEXT: memw(r{{[0-9]+}}++#4)
; CHECK-NEXT: endloop0
define i32 @test(i32* %a, i32 %n, i32 %l) {
Modified: llvm/trunk/test/CodeGen/Hexagon/swp-stages4.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/swp-stages4.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/swp-stages4.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/swp-stages4.ll Fri Feb 10 09:33:13 2017
@@ -6,8 +6,8 @@
; CHECK: = and
; CHECK: = and
; CHECK: = and
-; CHECK: [[REG0:(r[0-9]+)]] = and([[REG1:(r[0-9]+)]], #255)
-; CHECK-NOT: [[REG0]] = and([[REG1]], #255)
+; CHECK: [[REG0:(r[0-9]+)]] = and([[REG1:(r[0-9]+)]],#255)
+; CHECK-NOT: [[REG0]] = and([[REG1]],#255)
; CHECK: loop0(.LBB0_[[LOOP:.]],
; CHECK: .LBB0_[[LOOP]]:
; CHECK: [[REG0]] += add
Modified: llvm/trunk/test/CodeGen/Hexagon/swp-stages5.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/swp-stages5.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/swp-stages5.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/swp-stages5.ll Fri Feb 10 09:33:13 2017
@@ -7,7 +7,7 @@
; CHECK-DAG: [[REG0:(r[0-9]+)]] = memub(r{{[0-9]+}}++#1)
; CHECK-DAG: loop0(.LBB0_[[LOOP:.]],
; CHECK: .LBB0_[[LOOP]]:
-; CHECK: = and([[REG0]], #255)
+; CHECK: = and([[REG0]],#255)
; CHECK: [[REG0]]{{[:0-9]*}} =
; CHECK: endloop
Modified: llvm/trunk/test/CodeGen/Hexagon/swp-vmult.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/swp-vmult.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/swp-vmult.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/swp-vmult.ll Fri Feb 10 09:33:13 2017
@@ -2,10 +2,10 @@
; RUN: llc -march=hexagon -mcpu=hexagonv5 -O3 < %s | FileCheck %s
; Multiply and accumulate
-; CHECK: mpyi([[REG0:r([0-9]+)]], [[REG1:r([0-9]+)]])
-; CHECK-NEXT: add(r{{[0-9]+}}, #4)
-; CHECK-NEXT: [[REG0]] = memw(r{{[0-9]+}} + r{{[0-9]+}}<<#0)
-; CHECK-NEXT: [[REG1]] = memw(r{{[0-9]+}} + r{{[0-9]+}}<<#0)
+; CHECK: mpyi([[REG0:r([0-9]+)]],[[REG1:r([0-9]+)]])
+; CHECK-NEXT: add(r{{[0-9]+}},#4)
+; CHECK-NEXT: [[REG0]] = memw(r{{[0-9]+}}+r{{[0-9]+}}<<#0)
+; CHECK-NEXT: [[REG1]] = memw(r{{[0-9]+}}+r{{[0-9]+}}<<#0)
; CHECK-NEXT: endloop0
define i32 @foo(i32* %a, i32* %b, i32 %n) {
Modified: llvm/trunk/test/CodeGen/Hexagon/swp-vsum.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/swp-vsum.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/swp-vsum.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/swp-vsum.ll Fri Feb 10 09:33:13 2017
@@ -4,9 +4,9 @@
; Simple vector total.
; CHECK: loop0(.LBB0_[[LOOP:.]],
; CHECK: .LBB0_[[LOOP]]:
-; CHECK: add([[REG:r([0-9]+)]], r{{[0-9]+}})
-; CHECK-NEXT: add(r{{[0-9]+}}, #4)
-; CHECK-NEXT: [[REG]] = memw(r{{[0-9]+}} + r{{[0-9]+}}<<#0)
+; CHECK: add([[REG:r([0-9]+)]],r{{[0-9]+}})
+; CHECK-NEXT: add(r{{[0-9]+}},#4)
+; CHECK-NEXT: [[REG]] = memw(r{{[0-9]+}}+r{{[0-9]+}}<<#0)
; CHECK-NEXT: endloop0
define i32 @foo(i32* %a, i32 %n) {
Modified: llvm/trunk/test/CodeGen/Hexagon/tail-dup-subreg-map.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/tail-dup-subreg-map.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/tail-dup-subreg-map.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/tail-dup-subreg-map.ll Fri Feb 10 09:33:13 2017
@@ -5,7 +5,7 @@
; subregisters were dropped by the tail duplicator, resulting in invalid
; COPY instructions being generated.
-; CHECK: = extractu(r{{[0-9]+}}, #15, #17)
+; CHECK: = extractu(r{{[0-9]+}},#15,#17)
target triple = "hexagon"
Modified: llvm/trunk/test/CodeGen/Hexagon/tfr-to-combine.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/tfr-to-combine.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/tfr-to-combine.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/tfr-to-combine.ll Fri Feb 10 09:33:13 2017
@@ -8,7 +8,7 @@
; Function Attrs: nounwind
define i64 @test1() #0 {
-; CHECK: combine(#10, #0)
+; CHECK: combine(#10,#0)
entry:
store i16 0, i16* @a, align 2
store i16 10, i16* @b, align 2
@@ -17,7 +17,7 @@ entry:
; Function Attrs: nounwind
define i64 @test2() #0 {
-; CHECK: combine(#0, r{{[0-9]+}})
+; CHECK: combine(#0,r{{[0-9]+}})
entry:
store i16 0, i16* @a, align 2
%0 = load i16, i16* @c, align 2
@@ -27,7 +27,7 @@ entry:
; Function Attrs: nounwind
define i64 @test4() #0 {
-; CHECK: combine(#0, #100)
+; CHECK: combine(#0,#100)
entry:
store i16 100, i16* @b, align 2
store i16 0, i16* @a, align 2
Modified: llvm/trunk/test/CodeGen/Hexagon/tls_pic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/tls_pic.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/tls_pic.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/tls_pic.ll Fri Feb 10 09:33:13 2017
@@ -4,7 +4,7 @@
@src_ie = thread_local(initialexec) global i32 0, align 4
; CHECK-LABEL: test_initial_exec
-; CHECK-DAG: = add(pc, ##_GLOBAL_OFFSET_TABLE_ at PCREL)
+; CHECK-DAG: = add(pc,##_GLOBAL_OFFSET_TABLE_ at PCREL)
; CHECK-DAG: = ##src_ie at IEGOT
; CHECK-DAG: = ##dst_ie at IEGOT
; CHECK-NOT: call
@@ -22,7 +22,7 @@ entry:
; general-dynamic model.
; CHECK-LABEL: test_dynamic
-; CHECK-DAG: = add(pc, ##_GLOBAL_OFFSET_TABLE_ at PCREL)
+; CHECK-DAG: = add(pc,##_GLOBAL_OFFSET_TABLE_ at PCREL)
; CHECK-DAG: = ##src_gd at GDGOT
; CHECK-DAG: = ##dst_gd at GDGOT
; CHECK-DAG: call src_gd at GDPLT
Modified: llvm/trunk/test/CodeGen/Hexagon/two-crash.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/two-crash.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/two-crash.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/two-crash.ll Fri Feb 10 09:33:13 2017
@@ -1,7 +1,7 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; This testcase crashed, because we propagated a reg:sub into a tied use.
; The two-address pass rewrote it in a way that generated incorrect code.
-; CHECK: r{{[0-9]+}} += lsr(r{{[0-9]+}}, #16)
+; CHECK: r{{[0-9]+}} += lsr(r{{[0-9]+}},#16)
target triple = "hexagon"
Modified: llvm/trunk/test/CodeGen/Hexagon/vaddh.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/vaddh.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/vaddh.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/vaddh.ll Fri Feb 10 09:33:13 2017
@@ -1,5 +1,5 @@
; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
-; CHECK: vaddh(r{{[0-9]+}}, r{{[0-9]+}})
+; CHECK: vaddh(r{{[0-9]+}},r{{[0-9]+}})
@j = external global i32
@k = external global i32
Modified: llvm/trunk/test/CodeGen/Hexagon/vect/vect-cst-v4i32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/vect/vect-cst-v4i32.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/vect/vect-cst-v4i32.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/vect/vect-cst-v4i32.ll Fri Feb 10 09:33:13 2017
@@ -1,6 +1,6 @@
; RUN: llc -march=hexagon -mcpu=hexagonv5 -disable-hsdr < %s | FileCheck %s
; This one should generate a combine with two immediates.
-; CHECK: combine(#7, #7)
+; CHECK: combine(#7,#7)
@B = common global [400 x i32] zeroinitializer, align 8
@A = common global [400 x i32] zeroinitializer, align 8
@C = common global [400 x i32] zeroinitializer, align 8
Modified: llvm/trunk/test/CodeGen/Hexagon/vect/vect-loadv4i16.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/vect/vect-loadv4i16.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/vect/vect-loadv4i16.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/vect/vect-loadv4i16.ll Fri Feb 10 09:33:13 2017
@@ -1,8 +1,8 @@
; RUN: llc -march=hexagon -mcpu=hexagonv5 -disable-hsdr < %s | FileCheck %s
; Check that store is post-incremented.
-; CHECK: memuh(r{{[0-9]+}} + {{ *}}#6{{ *}})
-; CHECK: combine(r{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}{{ *}})
+; CHECK: memuh(r{{[0-9]+}}+#6)
+; CHECK: combine(r{{[0-9]+}},r{{[0-9]+}})
; CHECK: vaddh
target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32"
Modified: llvm/trunk/test/CodeGen/Hexagon/vect/vect-shift-imm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/vect/vect-shift-imm.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/vect/vect-shift-imm.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/vect/vect-shift-imm.ll Fri Feb 10 09:33:13 2017
@@ -6,12 +6,12 @@
; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-LSRH
;
; Make sure that the instructions with immediate operands are generated.
-; CHECK-ASLW: vaslw({{.*}}, #9)
-; CHECK-ASRW: vasrw({{.*}}, #8)
-; CHECK-LSRW: vlsrw({{.*}}, #7)
-; CHECK-ASLH: vaslh({{.*}}, #6)
-; CHECK-ASRH: vasrh({{.*}}, #5)
-; CHECK-LSRH: vlsrh({{.*}}, #4)
+; CHECK-ASLW: vaslw({{.*}},#9)
+; CHECK-ASRW: vasrw({{.*}},#8)
+; CHECK-LSRW: vlsrw({{.*}},#7)
+; CHECK-ASLH: vaslh({{.*}},#6)
+; CHECK-ASRH: vasrh({{.*}},#5)
+; CHECK-LSRH: vlsrh({{.*}},#4)
target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32"
target triple = "hexagon"
Modified: llvm/trunk/test/CodeGen/Hexagon/vect/vect-vshifts.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/vect/vect-vshifts.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/vect/vect-vshifts.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/vect/vect-vshifts.ll Fri Feb 10 09:33:13 2017
@@ -1,8 +1,8 @@
; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
; Check that store is post-incremented.
-; CHECK: r{{[0-9]+:[0-9]+}} = vasrw(r{{[0-9]+:[0-9]+}}, r{{[0-9]+}})
-; CHECK: r{{[0-9]+:[0-9]+}} = vaslw(r{{[0-9]+:[0-9]+}}, r{{[0-9]+}})
+; CHECK: r{{[0-9]+:[0-9]+}} = vasrw(r{{[0-9]+:[0-9]+}},r{{[0-9]+}})
+; CHECK: r{{[0-9]+:[0-9]+}} = vaslw(r{{[0-9]+:[0-9]+}},r{{[0-9]+}})
target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32"
target triple = "hexagon"
Modified: llvm/trunk/test/CodeGen/Hexagon/vect/vect-xor.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/vect/vect-xor.ll?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/vect/vect-xor.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/vect/vect-xor.ll Fri Feb 10 09:33:13 2017
@@ -1,7 +1,7 @@
; RUN: llc -march=hexagon -mcpu=hexagonv5 -disable-hsdr < %s | FileCheck %s
; Check that the parsing succeeded.
-; CHECK: r{{[0-9]+:[0-9]+}} = xor(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}})
+; CHECK: r{{[0-9]+:[0-9]+}} = xor(r{{[0-9]+:[0-9]+}},r{{[0-9]+:[0-9]+}})
target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32"
target triple = "hexagon"
Modified: llvm/trunk/test/MC/Disassembler/Hexagon/alu32_alu.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/alu32_alu.txt?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Hexagon/alu32_alu.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Hexagon/alu32_alu.txt Fri Feb 10 09:33:13 2017
@@ -3,27 +3,27 @@
# Add
0xf1 0xc3 0x15 0xb0
-# CHECK: r17 = add(r21, #31)
+# CHECK: r17 = add(r21,#31)
0x11 0xdf 0x15 0xf3
-# CHECK: r17 = add(r21, r31)
+# CHECK: r17 = add(r21,r31)
0x11 0xdf 0x55 0xf6
-# CHECK: r17 = add(r21, r31):sat
+# CHECK: r17 = add(r21,r31):sat
# And
0xf1 0xc3 0x15 0x76
-# CHECK: r17 = and(r21, #31)
+# CHECK: r17 = and(r21,#31)
0xf1 0xc3 0x95 0x76
-# CHECK: r17 = or(r21, #31)
+# CHECK: r17 = or(r21,#31)
0x11 0xdf 0x15 0xf1
-# CHECK: r17 = and(r21, r31)
+# CHECK: r17 = and(r21,r31)
0x11 0xdf 0x35 0xf1
-# CHECK: r17 = or(r21, r31)
+# CHECK: r17 = or(r21,r31)
0x11 0xdf 0x75 0xf1
-# CHECK: r17 = xor(r21, r31)
+# CHECK: r17 = xor(r21,r31)
0x11 0xd5 0x9f 0xf1
-# CHECK: r17 = and(r21, ~r31)
+# CHECK: r17 = and(r21,~r31)
0x11 0xd5 0xbf 0xf1
-# CHECK: r17 = or(r21, ~r31)
+# CHECK: r17 = or(r21,~r31)
# Nop
0x00 0xc0 0x00 0x7f
@@ -31,11 +31,11 @@
# Subtract
0xb1 0xc2 0x5f 0x76
-# CHECK: r17 = sub(#21, r31)
+# CHECK: r17 = sub(#21,r31)
0x11 0xdf 0x35 0xf3
-# CHECK: r17 = sub(r31, r21)
+# CHECK: r17 = sub(r31,r21)
0x11 0xdf 0xd5 0xf6
-# CHECK: r17 = sub(r31, r21):sat
+# CHECK: r17 = sub(r31,r21):sat
# Sign extend
0x11 0xc0 0xbf 0x70
@@ -57,27 +57,27 @@
# Vector add halfwords
0x11 0xdf 0x15 0xf6
-# CHECK: r17 = vaddh(r21, r31)
+# CHECK: r17 = vaddh(r21,r31)
0x11 0xdf 0x35 0xf6
-# CHECK: r17 = vaddh(r21, r31):sat
+# CHECK: r17 = vaddh(r21,r31):sat
0x11 0xdf 0x75 0xf6
-# CHECK: r17 = vadduh(r21, r31):sat
+# CHECK: r17 = vadduh(r21,r31):sat
# Vector average halfwords
0x11 0xdf 0x15 0xf7
-# CHECK: r17 = vavgh(r21, r31)
+# CHECK: r17 = vavgh(r21,r31)
0x11 0xdf 0x35 0xf7
-# CHECK: r17 = vavgh(r21, r31):rnd
+# CHECK: r17 = vavgh(r21,r31):rnd
0x11 0xdf 0x75 0xf7
-# CHECK: r17 = vnavgh(r31, r21)
+# CHECK: r17 = vnavgh(r31,r21)
# Vector subtract halfwords
0x11 0xdf 0x95 0xf6
-# CHECK: r17 = vsubh(r31, r21)
+# CHECK: r17 = vsubh(r31,r21)
0x11 0xdf 0xb5 0xf6
-# CHECK: r17 = vsubh(r31, r21):sat
+# CHECK: r17 = vsubh(r31,r21):sat
0x11 0xdf 0xf5 0xf6
-# CHECK: r17 = vsubuh(r31, r21):sat
+# CHECK: r17 = vsubuh(r31,r21):sat
# Zero extend
0x11 0xc0 0xd5 0x70
Modified: llvm/trunk/test/MC/Disassembler/Hexagon/alu32_perm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/alu32_perm.txt?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Hexagon/alu32_perm.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Hexagon/alu32_perm.txt Fri Feb 10 09:33:13 2017
@@ -3,31 +3,31 @@
# Combine words in to doublewords
0x11 0xdf 0x95 0xf3
-# CHECK: r17 = combine(r31.h, r21.h)
+# CHECK: r17 = combine(r31.h,r21.h)
0x11 0xdf 0xb5 0xf3
-# CHECK: r17 = combine(r31.h, r21.l)
+# CHECK: r17 = combine(r31.h,r21.l)
0x11 0xdf 0xd5 0xf3
-# CHECK: r17 = combine(r31.l, r21.h)
+# CHECK: r17 = combine(r31.l,r21.h)
0x11 0xdf 0xf5 0xf3
-# CHECK: r17 = combine(r31.l, r21.l)
+# CHECK: r17 = combine(r31.l,r21.l)
0xb0 0xe2 0x0f 0x7c
-# CHECK: r17:16 = combine(#21, #31)
+# CHECK: r17:16 = combine(#21,#31)
0xb0 0xe2 0x3f 0x73
-# CHECK: r17:16 = combine(#21, r31)
+# CHECK: r17:16 = combine(#21,r31)
0xf0 0xe3 0x15 0x73
-# CHECK: r17:16 = combine(r21, #31)
+# CHECK: r17:16 = combine(r21,#31)
0x10 0xdf 0x15 0xf5
-# CHECK: r17:16 = combine(r21, r31)
+# CHECK: r17:16 = combine(r21,r31)
# Mux
0xf1 0xc3 0x75 0x73
-# CHECK: r17 = mux(p3, r21, #31)
+# CHECK: r17 = mux(p3,r21,#31)
0xb1 0xc2 0xff 0x73
-# CHECK: r17 = mux(p3, #21, r31)
+# CHECK: r17 = mux(p3,#21,r31)
0xb1 0xe2 0x8f 0x7b
-# CHECK: r17 = mux(p3, #21, #31)
+# CHECK: r17 = mux(p3,#21,#31)
0x71 0xdf 0x15 0xf4
-# CHECK: r17 = mux(p3, r21, r31)
+# CHECK: r17 = mux(p3,r21,r31)
# Shift word by 16
0x11 0xc0 0x15 0x70
@@ -37,4 +37,4 @@
# Pack high and low halfwords
0x10 0xdf 0x95 0xf5
-# CHECK: r17:16 = packhl(r21, r31)
+# CHECK: r17:16 = packhl(r21,r31)
Modified: llvm/trunk/test/MC/Disassembler/Hexagon/alu32_pred.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/alu32_pred.txt?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Hexagon/alu32_pred.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Hexagon/alu32_pred.txt Fri Feb 10 09:33:13 2017
@@ -3,25 +3,25 @@
# Conditional add
0xf1 0xc3 0x75 0x74
-# CHECK: if (p3) r17 = add(r21, #31)
+# CHECK: if (p3) r17 = add(r21,#31)
0x03 0x40 0x45 0x85 0xf1 0xe3 0x75 0x74
# CHECK: p3 = r5
-# CHECK-NEXT: if (p3.new) r17 = add(r21, #31)
+# CHECK-NEXT: if (p3.new) r17 = add(r21,#31)
0xf1 0xc3 0xf5 0x74
-# CHECK: if (!p3) r17 = add(r21, #31)
+# CHECK: if (!p3) r17 = add(r21,#31)
0x03 0x40 0x45 0x85 0xf1 0xe3 0xf5 0x74
# CHECK: p3 = r5
-# CHECK-NEXT: if (!p3.new) r17 = add(r21, #31)
+# CHECK-NEXT: if (!p3.new) r17 = add(r21,#31)
0x71 0xdf 0x15 0xfb
-# CHECK: if (p3) r17 = add(r21, r31)
+# CHECK: if (p3) r17 = add(r21,r31)
0x03 0x40 0x45 0x85 0x71 0xff 0x15 0xfb
# CHECK: p3 = r5
-# CHECK-NEXT: if (p3.new) r17 = add(r21, r31)
+# CHECK-NEXT: if (p3.new) r17 = add(r21,r31)
0xf1 0xdf 0x15 0xfb
-# CHECK: if (!p3) r17 = add(r21, r31)
+# CHECK: if (!p3) r17 = add(r21,r31)
0x03 0x40 0x45 0x85 0xf1 0xff 0x15 0xfb
# CHECK: p3 = r5
-# CHECK-NEXT: if (!p3.new) r17 = add(r21, r31)
+# CHECK-NEXT: if (!p3.new) r17 = add(r21,r31)
# Conditional shift halfword
0x11 0xe3 0x15 0x70
@@ -47,59 +47,59 @@
# Conditional combine
0x70 0xdf 0x15 0xfd
-# CHECK: if (p3) r17:16 = combine(r21, r31)
+# CHECK: if (p3) r17:16 = combine(r21,r31)
0xf0 0xdf 0x15 0xfd
-# CHECK: if (!p3) r17:16 = combine(r21, r31)
+# CHECK: if (!p3) r17:16 = combine(r21,r31)
0x03 0x40 0x45 0x85 0x70 0xff 0x15 0xfd
# CHECK: p3 = r5
-# CHECK-NEXT: if (p3.new) r17:16 = combine(r21, r31)
+# CHECK-NEXT: if (p3.new) r17:16 = combine(r21,r31)
0x03 0x40 0x45 0x85 0xf0 0xff 0x15 0xfd
# CHECK: p3 = r5
-# CHECK-NEXT: if (!p3.new) r17:16 = combine(r21, r31)
+# CHECK-NEXT: if (!p3.new) r17:16 = combine(r21,r31)
# Conditional logical operations
0x71 0xdf 0x15 0xf9
-# CHECK: if (p3) r17 = and(r21, r31)
+# CHECK: if (p3) r17 = and(r21,r31)
0xf1 0xdf 0x15 0xf9
-# CHECK: if (!p3) r17 = and(r21, r31)
+# CHECK: if (!p3) r17 = and(r21,r31)
0x03 0x40 0x45 0x85 0x71 0xff 0x15 0xf9
# CHECK: p3 = r5
-# CHECK-NEXT: if (p3.new) r17 = and(r21, r31)
+# CHECK-NEXT: if (p3.new) r17 = and(r21,r31)
0x03 0x40 0x45 0x85 0xf1 0xff 0x15 0xf9
# CHECK: p3 = r5
-# CHECK-NEXT: if (!p3.new) r17 = and(r21, r31)
+# CHECK-NEXT: if (!p3.new) r17 = and(r21,r31)
0x71 0xdf 0x35 0xf9
-# CHECK: if (p3) r17 = or(r21, r31)
+# CHECK: if (p3) r17 = or(r21,r31)
0xf1 0xdf 0x35 0xf9
-# CHECK: if (!p3) r17 = or(r21, r31)
+# CHECK: if (!p3) r17 = or(r21,r31)
0x03 0x40 0x45 0x85 0x71 0xff 0x35 0xf9
# CHECK: p3 = r5
-# CHECK-NEXT: if (p3.new) r17 = or(r21, r31)
+# CHECK-NEXT: if (p3.new) r17 = or(r21,r31)
0x03 0x40 0x45 0x85 0xf1 0xff 0x35 0xf9
# CHECK: p3 = r5
-# CHECK-NEXT: if (!p3.new) r17 = or(r21, r31)
+# CHECK-NEXT: if (!p3.new) r17 = or(r21,r31)
0x71 0xdf 0x75 0xf9
-# CHECK: if (p3) r17 = xor(r21, r31)
+# CHECK: if (p3) r17 = xor(r21,r31)
0xf1 0xdf 0x75 0xf9
-# CHECK: if (!p3) r17 = xor(r21, r31)
+# CHECK: if (!p3) r17 = xor(r21,r31)
0x03 0x40 0x45 0x85 0x71 0xff 0x75 0xf9
# CHECK: p3 = r5
-# CHECK-NEXT: if (p3.new) r17 = xor(r21, r31)
+# CHECK-NEXT: if (p3.new) r17 = xor(r21,r31)
0x03 0x40 0x45 0x85 0xf1 0xff 0x75 0xf9
# CHECK: p3 = r5
-# CHECK-NEXT: if (!p3.new) r17 = xor(r21, r31)
+# CHECK-NEXT: if (!p3.new) r17 = xor(r21,r31)
# Conditional subtract
0x71 0xdf 0x35 0xfb
-# CHECK: if (p3) r17 = sub(r31, r21)
+# CHECK: if (p3) r17 = sub(r31,r21)
0xf1 0xdf 0x35 0xfb
-# CHECK: if (!p3) r17 = sub(r31, r21)
+# CHECK: if (!p3) r17 = sub(r31,r21)
0x03 0x40 0x45 0x85 0x71 0xff 0x35 0xfb
# CHECK: p3 = r5
-# CHECK-NEXT: if (p3.new) r17 = sub(r31, r21)
+# CHECK-NEXT: if (p3.new) r17 = sub(r31,r21)
0x03 0x40 0x45 0x85 0xf1 0xff 0x35 0xfb
# CHECK: p3 = r5
-# CHECK-NEXT: if (!p3.new) r17 = sub(r31, r21)
+# CHECK-NEXT: if (!p3.new) r17 = sub(r31,r21)
# Conditional sign extend
0x11 0xe3 0xb5 0x70
@@ -159,36 +159,36 @@
# Compare
0xe3 0xc3 0x15 0x75
-# CHECK: p3 = cmp.eq(r21, #31)
+# CHECK: p3 = cmp.eq(r21,#31)
0xf3 0xc3 0x15 0x75
-# CHECK: p3 = !cmp.eq(r21, #31)
+# CHECK: p3 = !cmp.eq(r21,#31)
0xe3 0xc3 0x55 0x75
-# CHECK: p3 = cmp.gt(r21, #31)
+# CHECK: p3 = cmp.gt(r21,#31)
0xf3 0xc3 0x55 0x75
-# CHECK: p3 = !cmp.gt(r21, #31)
+# CHECK: p3 = !cmp.gt(r21,#31)
0xe3 0xc3 0x95 0x75
-# CHECK: p3 = cmp.gtu(r21, #31)
+# CHECK: p3 = cmp.gtu(r21,#31)
0xf3 0xc3 0x95 0x75
-# CHECK: p3 = !cmp.gtu(r21, #31)
+# CHECK: p3 = !cmp.gtu(r21,#31)
0x03 0xdf 0x15 0xf2
-# CHECK: p3 = cmp.eq(r21, r31)
+# CHECK: p3 = cmp.eq(r21,r31)
0x13 0xdf 0x15 0xf2
-# CHECK: p3 = !cmp.eq(r21, r31)
+# CHECK: p3 = !cmp.eq(r21,r31)
0x03 0xdf 0x55 0xf2
-# CHECK: p3 = cmp.gt(r21, r31)
+# CHECK: p3 = cmp.gt(r21,r31)
0x13 0xdf 0x55 0xf2
-# CHECK: p3 = !cmp.gt(r21, r31)
+# CHECK: p3 = !cmp.gt(r21,r31)
0x03 0xdf 0x75 0xf2
-# CHECK: p3 = cmp.gtu(r21, r31)
+# CHECK: p3 = cmp.gtu(r21,r31)
0x13 0xdf 0x75 0xf2
-# CHECK: p3 = !cmp.gtu(r21, r31)
+# CHECK: p3 = !cmp.gtu(r21,r31)
# Compare to general register
0xf1 0xe3 0x55 0x73
-# CHECK: r17 = cmp.eq(r21, #31)
+# CHECK: r17 = cmp.eq(r21,#31)
0xf1 0xe3 0x75 0x73
-# CHECK: r17 = !cmp.eq(r21, #31)
+# CHECK: r17 = !cmp.eq(r21,#31)
0x11 0xdf 0x55 0xf3
-# CHECK: r17 = cmp.eq(r21, r31)
+# CHECK: r17 = cmp.eq(r21,r31)
0x11 0xdf 0x75 0xf3
-# CHECK: r17 = !cmp.eq(r21, r31)
+# CHECK: r17 = !cmp.eq(r21,r31)
Modified: llvm/trunk/test/MC/Disassembler/Hexagon/cr.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/cr.txt?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Hexagon/cr.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Hexagon/cr.txt Fri Feb 10 09:33:13 2017
@@ -3,9 +3,9 @@
# Corner detection acceleration
0x93 0xe1 0x12 0x6b
-# CHECK: p3 = !fastcorner9(p2, p1)
+# CHECK: p3 = !fastcorner9(p2,p1)
0x91 0xe3 0x02 0x6b
-# CHECK: p1 = fastcorner9(p2, p3)
+# CHECK: p1 = fastcorner9(p2,p3)
# Logical reductions on predicates
0x01 0xc0 0x82 0x6b
@@ -25,7 +25,7 @@
# Add to PC
0x91 0xca 0x49 0x6a
-# CHECK: r17 = add(pc, #21)
+# CHECK: r17 = add(pc,#21)
# Pipelined loop instructions
0x08 0xc4 0xb5 0x60
@@ -43,33 +43,33 @@
# Logical operations on predicates
0x01 0xc3 0x02 0x6b
-# CHECK: p1 = and(p3, p2)
+# CHECK: p1 = and(p3,p2)
0xc1 0xc3 0x12 0x6b
-# CHECK: p1 = and(p2, and(p3, p3))
+# CHECK: p1 = and(p2,and(p3,p3))
0x01 0xc3 0x22 0x6b
-# CHECK: p1 = or(p3, p2)
+# CHECK: p1 = or(p3,p2)
0xc1 0xc3 0x32 0x6b
-# CHECK: p1 = and(p2, or(p3, p3))
+# CHECK: p1 = and(p2,or(p3,p3))
0x01 0xc3 0x42 0x6b
-# CHECK: p1 = xor(p2, p3)
+# CHECK: p1 = xor(p2,p3)
0xc1 0xc3 0x52 0x6b
-# CHECK: p1 = or(p2, and(p3, p3))
+# CHECK: p1 = or(p2,and(p3,p3))
0x01 0xc2 0x63 0x6b
-# CHECK: p1 = and(p2, !p3)
+# CHECK: p1 = and(p2,!p3)
0xc1 0xc3 0x72 0x6b
-# CHECK: p1 = or(p2, or(p3, p3))
+# CHECK: p1 = or(p2,or(p3,p3))
0xc1 0xc3 0x92 0x6b
-# CHECK: p1 = and(p2, and(p3, !p3))
+# CHECK: p1 = and(p2,and(p3,!p3))
0xc1 0xc3 0xb2 0x6b
-# CHECK: p1 = and(p2, or(p3, !p3))
+# CHECK: p1 = and(p2,or(p3,!p3))
0x01 0xc0 0xc2 0x6b
# CHECK: p1 = not(p2)
0xc1 0xc3 0xd2 0x6b
-# CHECK: p1 = or(p2, and(p3, !p3))
+# CHECK: p1 = or(p2,and(p3,!p3))
0x01 0xc2 0xe3 0x6b
-# CHECK: p1 = or(p2, !p3)
+# CHECK: p1 = or(p2,!p3)
0xc1 0xc3 0xf2 0x6b
-# CHECK: p1 = or(p2, or(p3, !p3))
+# CHECK: p1 = or(p2,or(p3,!p3))
# User control register transfer
0x0d 0xc0 0x35 0x62
Modified: llvm/trunk/test/MC/Disassembler/Hexagon/j.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/j.txt?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Hexagon/j.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Hexagon/j.txt Fri Feb 10 09:33:13 2017
@@ -15,145 +15,145 @@
0x00 0xc1 0x89 0x11
# CHECK: p0 = cmp.gt(r17,#-1); if (p0.new) jump:nt
0x00 0xc3 0x89 0x11
-# CHECK: p0 = tstbit(r17, #0); if (p0.new) jump:nt
+# CHECK: p0 = tstbit(r17,#0); if (p0.new) jump:nt
0x00 0xe0 0x89 0x11
# CHECK: p0 = cmp.eq(r17,#-1); if (p0.new) jump:t
0x00 0xe1 0x89 0x11
# CHECK: p0 = cmp.gt(r17,#-1); if (p0.new) jump:t
0x00 0xe3 0x89 0x11
-# CHECK: p0 = tstbit(r17, #0); if (p0.new) jump:t
+# CHECK: p0 = tstbit(r17,#0); if (p0.new) jump:t
0x00 0xc0 0xc9 0x11
# CHECK: p0 = cmp.eq(r17,#-1); if (!p0.new) jump:nt
0x00 0xc1 0xc9 0x11
# CHECK: p0 = cmp.gt(r17,#-1); if (!p0.new) jump:nt
0x00 0xc3 0xc9 0x11
-# CHECK: p0 = tstbit(r17, #0); if (!p0.new) jump:nt
+# CHECK: p0 = tstbit(r17,#0); if (!p0.new) jump:nt
0x00 0xe0 0xc9 0x11
# CHECK: p0 = cmp.eq(r17,#-1); if (!p0.new) jump:t
0x00 0xe1 0xc9 0x11
# CHECK: p0 = cmp.gt(r17,#-1); if (!p0.new) jump:t
0x00 0xe3 0xc9 0x11
-# CHECK: p0 = tstbit(r17, #0); if (!p0.new) jump:t
+# CHECK: p0 = tstbit(r17,#0); if (!p0.new) jump:t
0x00 0xd5 0x09 0x10
-# CHECK: p0 = cmp.eq(r17, #21); if (p0.new) jump:nt
+# CHECK: p0 = cmp.eq(r17,#21); if (p0.new) jump:nt
0x00 0xf5 0x09 0x10
-# CHECK: p0 = cmp.eq(r17, #21); if (p0.new) jump:t
+# CHECK: p0 = cmp.eq(r17,#21); if (p0.new) jump:t
0x00 0xd5 0x49 0x10
-# CHECK: p0 = cmp.eq(r17, #21); if (!p0.new) jump:nt
+# CHECK: p0 = cmp.eq(r17,#21); if (!p0.new) jump:nt
0x00 0xf5 0x49 0x10
-# CHECK: p0 = cmp.eq(r17, #21); if (!p0.new) jump:t
+# CHECK: p0 = cmp.eq(r17,#21); if (!p0.new) jump:t
0x00 0xd5 0x89 0x10
-# CHECK: p0 = cmp.gt(r17, #21); if (p0.new) jump:nt
+# CHECK: p0 = cmp.gt(r17,#21); if (p0.new) jump:nt
0x00 0xf5 0x89 0x10
-# CHECK: p0 = cmp.gt(r17, #21); if (p0.new) jump:t
+# CHECK: p0 = cmp.gt(r17,#21); if (p0.new) jump:t
0x00 0xd5 0xc9 0x10
-# CHECK: p0 = cmp.gt(r17, #21); if (!p0.new) jump:nt
+# CHECK: p0 = cmp.gt(r17,#21); if (!p0.new) jump:nt
0x00 0xf5 0xc9 0x10
-# CHECK: p0 = cmp.gt(r17, #21); if (!p0.new) jump:t
+# CHECK: p0 = cmp.gt(r17,#21); if (!p0.new) jump:t
0x00 0xd5 0x09 0x11
-# CHECK: p0 = cmp.gtu(r17, #21); if (p0.new) jump:nt
+# CHECK: p0 = cmp.gtu(r17,#21); if (p0.new) jump:nt
0x00 0xf5 0x09 0x11
-# CHECK: p0 = cmp.gtu(r17, #21); if (p0.new) jump:t
+# CHECK: p0 = cmp.gtu(r17,#21); if (p0.new) jump:t
0x00 0xd5 0x49 0x11
-# CHECK: p0 = cmp.gtu(r17, #21); if (!p0.new) jump:nt
+# CHECK: p0 = cmp.gtu(r17,#21); if (!p0.new) jump:nt
0x00 0xf5 0x49 0x11
-# CHECK: p0 = cmp.gtu(r17, #21); if (!p0.new) jump:t
+# CHECK: p0 = cmp.gtu(r17,#21); if (!p0.new) jump:t
0x00 0xc0 0x89 0x13
# CHECK: p1 = cmp.eq(r17,#-1); if (p1.new) jump:nt
0x00 0xc1 0x89 0x13
# CHECK: p1 = cmp.gt(r17,#-1); if (p1.new) jump:nt
0x00 0xc3 0x89 0x13
-# CHECK: p1 = tstbit(r17, #0); if (p1.new) jump:nt
+# CHECK: p1 = tstbit(r17,#0); if (p1.new) jump:nt
0x00 0xe0 0x89 0x13
# CHECK: p1 = cmp.eq(r17,#-1); if (p1.new) jump:t
0x00 0xe1 0x89 0x13
# CHECK: p1 = cmp.gt(r17,#-1); if (p1.new) jump:t
0x00 0xe3 0x89 0x13
-# CHECK: p1 = tstbit(r17, #0); if (p1.new) jump:t
+# CHECK: p1 = tstbit(r17,#0); if (p1.new) jump:t
0x00 0xc0 0xc9 0x13
# CHECK: p1 = cmp.eq(r17,#-1); if (!p1.new) jump:nt
0x00 0xc1 0xc9 0x13
# CHECK: p1 = cmp.gt(r17,#-1); if (!p1.new) jump:nt
0x00 0xc3 0xc9 0x13
-# CHECK: p1 = tstbit(r17, #0); if (!p1.new) jump:nt
+# CHECK: p1 = tstbit(r17,#0); if (!p1.new) jump:nt
0x00 0xe0 0xc9 0x13
# CHECK: p1 = cmp.eq(r17,#-1); if (!p1.new) jump:t
0x00 0xe1 0xc9 0x13
# CHECK: p1 = cmp.gt(r17,#-1); if (!p1.new) jump:t
0x00 0xe3 0xc9 0x13
-# CHECK: p1 = tstbit(r17, #0); if (!p1.new) jump:t
+# CHECK: p1 = tstbit(r17,#0); if (!p1.new) jump:t
0x00 0xd5 0x09 0x12
-# CHECK: p1 = cmp.eq(r17, #21); if (p1.new) jump:nt
+# CHECK: p1 = cmp.eq(r17,#21); if (p1.new) jump:nt
0x00 0xf5 0x09 0x12
-# CHECK: p1 = cmp.eq(r17, #21); if (p1.new) jump:t
+# CHECK: p1 = cmp.eq(r17,#21); if (p1.new) jump:t
0x00 0xd5 0x49 0x12
-# CHECK: p1 = cmp.eq(r17, #21); if (!p1.new) jump:nt
+# CHECK: p1 = cmp.eq(r17,#21); if (!p1.new) jump:nt
0x00 0xf5 0x49 0x12
-# CHECK: p1 = cmp.eq(r17, #21); if (!p1.new) jump:t
+# CHECK: p1 = cmp.eq(r17,#21); if (!p1.new) jump:t
0x00 0xd5 0x89 0x12
-# CHECK: p1 = cmp.gt(r17, #21); if (p1.new) jump:nt
+# CHECK: p1 = cmp.gt(r17,#21); if (p1.new) jump:nt
0x00 0xf5 0x89 0x12
-# CHECK: p1 = cmp.gt(r17, #21); if (p1.new) jump:t
+# CHECK: p1 = cmp.gt(r17,#21); if (p1.new) jump:t
0x00 0xd5 0xc9 0x12
-# CHECK: p1 = cmp.gt(r17, #21); if (!p1.new) jump:nt
+# CHECK: p1 = cmp.gt(r17,#21); if (!p1.new) jump:nt
0x00 0xf5 0xc9 0x12
-# CHECK: p1 = cmp.gt(r17, #21); if (!p1.new) jump:t
+# CHECK: p1 = cmp.gt(r17,#21); if (!p1.new) jump:t
0x00 0xd5 0x09 0x13
-# CHECK: p1 = cmp.gtu(r17, #21); if (p1.new) jump:nt
+# CHECK: p1 = cmp.gtu(r17,#21); if (p1.new) jump:nt
0x00 0xf5 0x09 0x13
-# CHECK: p1 = cmp.gtu(r17, #21); if (p1.new) jump:t
+# CHECK: p1 = cmp.gtu(r17,#21); if (p1.new) jump:t
0x00 0xd5 0x49 0x13
-# CHECK: p1 = cmp.gtu(r17, #21); if (!p1.new) jump:nt
+# CHECK: p1 = cmp.gtu(r17,#21); if (!p1.new) jump:nt
0x00 0xf5 0x49 0x13
-# CHECK: p1 = cmp.gtu(r17, #21); if (!p1.new) jump:t
+# CHECK: p1 = cmp.gtu(r17,#21); if (!p1.new) jump:t
0x00 0xcd 0x09 0x14
-# CHECK: p0 = cmp.eq(r17, r21); if (p0.new) jump:nt
+# CHECK: p0 = cmp.eq(r17,r21); if (p0.new) jump:nt
0x00 0xdd 0x09 0x14
-# CHECK: p1 = cmp.eq(r17, r21); if (p1.new) jump:nt
+# CHECK: p1 = cmp.eq(r17,r21); if (p1.new) jump:nt
0x00 0xed 0x09 0x14
-# CHECK: p0 = cmp.eq(r17, r21); if (p0.new) jump:t
+# CHECK: p0 = cmp.eq(r17,r21); if (p0.new) jump:t
0x00 0xfd 0x09 0x14
-# CHECK: p1 = cmp.eq(r17, r21); if (p1.new) jump:t
+# CHECK: p1 = cmp.eq(r17,r21); if (p1.new) jump:t
0x00 0xcd 0x49 0x14
-# CHECK: p0 = cmp.eq(r17, r21); if (!p0.new) jump:nt
+# CHECK: p0 = cmp.eq(r17,r21); if (!p0.new) jump:nt
0x00 0xdd 0x49 0x14
-# CHECK: p1 = cmp.eq(r17, r21); if (!p1.new) jump:nt
+# CHECK: p1 = cmp.eq(r17,r21); if (!p1.new) jump:nt
0x00 0xed 0x49 0x14
-# CHECK: p0 = cmp.eq(r17, r21); if (!p0.new) jump:t
+# CHECK: p0 = cmp.eq(r17,r21); if (!p0.new) jump:t
0x00 0xfd 0x49 0x14
-# CHECK: p1 = cmp.eq(r17, r21); if (!p1.new) jump:t
+# CHECK: p1 = cmp.eq(r17,r21); if (!p1.new) jump:t
0x00 0xcd 0x89 0x14
-# CHECK: p0 = cmp.gt(r17, r21); if (p0.new) jump:nt
+# CHECK: p0 = cmp.gt(r17,r21); if (p0.new) jump:nt
0x00 0xdd 0x89 0x14
-# CHECK: p1 = cmp.gt(r17, r21); if (p1.new) jump:nt
+# CHECK: p1 = cmp.gt(r17,r21); if (p1.new) jump:nt
0x00 0xed 0x89 0x14
-# CHECK: p0 = cmp.gt(r17, r21); if (p0.new) jump:t
+# CHECK: p0 = cmp.gt(r17,r21); if (p0.new) jump:t
0x00 0xfd 0x89 0x14
-# CHECK: p1 = cmp.gt(r17, r21); if (p1.new) jump:t
+# CHECK: p1 = cmp.gt(r17,r21); if (p1.new) jump:t
0x00 0xcd 0xc9 0x14
-# CHECK: p0 = cmp.gt(r17, r21); if (!p0.new) jump:nt
+# CHECK: p0 = cmp.gt(r17,r21); if (!p0.new) jump:nt
0x00 0xdd 0xc9 0x14
-# CHECK: p1 = cmp.gt(r17, r21); if (!p1.new) jump:nt
+# CHECK: p1 = cmp.gt(r17,r21); if (!p1.new) jump:nt
0x00 0xed 0xc9 0x14
-# CHECK: p0 = cmp.gt(r17, r21); if (!p0.new) jump:t
+# CHECK: p0 = cmp.gt(r17,r21); if (!p0.new) jump:t
0x00 0xfd 0xc9 0x14
-# CHECK: p1 = cmp.gt(r17, r21); if (!p1.new) jump:t
+# CHECK: p1 = cmp.gt(r17,r21); if (!p1.new) jump:t
0x00 0xcd 0x09 0x15
-# CHECK: p0 = cmp.gtu(r17, r21); if (p0.new) jump:nt
+# CHECK: p0 = cmp.gtu(r17,r21); if (p0.new) jump:nt
0x00 0xdd 0x09 0x15
-# CHECK: p1 = cmp.gtu(r17, r21); if (p1.new) jump:nt
+# CHECK: p1 = cmp.gtu(r17,r21); if (p1.new) jump:nt
0x00 0xed 0x09 0x15
-# CHECK: p0 = cmp.gtu(r17, r21); if (p0.new) jump:t
+# CHECK: p0 = cmp.gtu(r17,r21); if (p0.new) jump:t
0x00 0xfd 0x09 0x15
-# CHECK: p1 = cmp.gtu(r17, r21); if (p1.new) jump:t
+# CHECK: p1 = cmp.gtu(r17,r21); if (p1.new) jump:t
0x00 0xcd 0x49 0x15
-# CHECK: p0 = cmp.gtu(r17, r21); if (!p0.new) jump:nt
+# CHECK: p0 = cmp.gtu(r17,r21); if (!p0.new) jump:nt
0x00 0xdd 0x49 0x15
-# CHECK: p1 = cmp.gtu(r17, r21); if (!p1.new) jump:nt
+# CHECK: p1 = cmp.gtu(r17,r21); if (!p1.new) jump:nt
0x00 0xed 0x49 0x15
-# CHECK: p0 = cmp.gtu(r17, r21); if (!p0.new) jump:t
+# CHECK: p0 = cmp.gtu(r17,r21); if (!p0.new) jump:t
0x00 0xfd 0x49 0x15
-# CHECK: p1 = cmp.gtu(r17, r21); if (!p1.new) jump:t
+# CHECK: p1 = cmp.gtu(r17,r21); if (!p1.new) jump:t
# Jump to address
0x22 0xc0 0x00 0x58
Modified: llvm/trunk/test/MC/Disassembler/Hexagon/ld.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/ld.txt?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Hexagon/ld.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Hexagon/ld.txt Fri Feb 10 09:33:13 2017
@@ -3,25 +3,25 @@
# Load doubleword
0x90 0xff 0xd5 0x3a
-# CHECK: r17:16 = memd(r21 + r31<<#3)
+# CHECK: r17:16 = memd(r21+r31<<#3)
0xb0 0xc2 0xc0 0x49
# CHECK: r17:16 = memd(gp+#168)
0x02 0x40 0x00 0x00 0x10 0xc5 0xc0 0x49
# CHECK: r17:16 = memd(##168)
0xd0 0xc0 0xd5 0x91
-# CHECK: r17:16 = memd(r21 + #48)
+# CHECK: r17:16 = memd(r21+#48)
0xb0 0xe0 0xd5 0x99
-# CHECK: r17:16 = memd(r21 ++ #40:circ(m1))
+# CHECK: r17:16 = memd(r21++#40:circ(m1))
0x10 0xe2 0xd5 0x99
-# CHECK: r17:16 = memd(r21 ++ I:circ(m1))
+# CHECK: r17:16 = memd(r21++I:circ(m1))
0x00 0x40 0x00 0x00 0x70 0xd7 0xd5 0x9b
-# CHECK: r17:16 = memd(r21 = ##31)
+# CHECK: r17:16 = memd(r21=##31)
0xb0 0xc0 0xd5 0x9b
# CHECK: r17:16 = memd(r21++#40)
0x10 0xe0 0xd5 0x9d
# CHECK: r17:16 = memd(r21++m1)
0x10 0xe0 0xd5 0x9f
-# CHECK: r17:16 = memd(r21 ++ m1:brev)
+# CHECK: r17:16 = memd(r21++m1:brev)
# Load doubleword conditionally
0xf0 0xff 0xd5 0x30
@@ -35,15 +35,15 @@
# CHECK: p3 = r5
# CHECK-NEXT: if (!p3.new) r17:16 = memd(r21+r31<<#3)
0x70 0xd8 0xd5 0x41
-# CHECK: if (p3) r17:16 = memd(r21 + #24)
+# CHECK: if (p3) r17:16 = memd(r21+#24)
0x03 0x40 0x45 0x85 0x70 0xd8 0xd5 0x43
# CHECK: p3 = r5
-# CHECK-NEXT: if (p3.new) r17:16 = memd(r21 + #24)
+# CHECK-NEXT: if (p3.new) r17:16 = memd(r21+#24)
0x70 0xd8 0xd5 0x45
-# CHECK: if (!p3) r17:16 = memd(r21 + #24)
+# CHECK: if (!p3) r17:16 = memd(r21+#24)
0x03 0x40 0x45 0x85 0x70 0xd8 0xd5 0x47
# CHECK: p3 = r5
-# CHECK-NEXT: if (!p3.new) r17:16 = memd(r21 + #24)
+# CHECK-NEXT: if (!p3.new) r17:16 = memd(r21+#24)
0xb0 0xe6 0xd5 0x9b
# CHECK: if (p3) r17:16 = memd(r21++#40)
0xb0 0xee 0xd5 0x9b
@@ -57,25 +57,25 @@
# Load byte
0x91 0xff 0x15 0x3a
-# CHECK: r17 = memb(r21 + r31<<#3)
+# CHECK: r17 = memb(r21+r31<<#3)
0xb1 0xc2 0x00 0x49
# CHECK: r17 = memb(gp+#21)
0x00 0x40 0x00 0x00 0xb1 0xc2 0x00 0x49
# CHECK: r17 = memb(##21)
0xf1 0xc3 0x15 0x91
-# CHECK: r17 = memb(r21 + #31)
+# CHECK: r17 = memb(r21+#31)
0xb1 0xe0 0x15 0x99
-# CHECK: r17 = memb(r21 ++ #5:circ(m1))
+# CHECK: r17 = memb(r21++#5:circ(m1))
0x11 0xe2 0x15 0x99
-# CHECK: r17 = memb(r21 ++ I:circ(m1))
+# CHECK: r17 = memb(r21++I:circ(m1))
0x00 0x40 0x00 0x00 0x71 0xd7 0x15 0x9b
-# CHECK: r17 = memb(r21 = ##31)
+# CHECK: r17 = memb(r21=##31)
0xb1 0xc0 0x15 0x9b
# CHECK: r17 = memb(r21++#5)
0x11 0xe0 0x15 0x9d
# CHECK: r17 = memb(r21++m1)
0x11 0xe0 0x15 0x9f
-# CHECK: r17 = memb(r21 ++ m1:brev)
+# CHECK: r17 = memb(r21++m1:brev)
# Load byte conditionally
0xf1 0xff 0x15 0x30
@@ -89,15 +89,15 @@
# CHECK: p3 = r5
# CHECK-NEXT: if (!p3.new) r17 = memb(r21+r31<<#3)
0x91 0xdd 0x15 0x41
-# CHECK: if (p3) r17 = memb(r21 + #44)
+# CHECK: if (p3) r17 = memb(r21+#44)
0x03 0x40 0x45 0x85 0x91 0xdd 0x15 0x43
# CHECK: p3 = r5
-# CHECK-NEXT: if (p3.new) r17 = memb(r21 + #44)
+# CHECK-NEXT: if (p3.new) r17 = memb(r21+#44)
0x91 0xdd 0x15 0x45
-# CHECK: if (!p3) r17 = memb(r21 + #44)
+# CHECK: if (!p3) r17 = memb(r21+#44)
0x03 0x40 0x45 0x85 0x91 0xdd 0x15 0x47
# CHECK: p3 = r5
-# CHECK-NEXT: if (!p3.new) r17 = memb(r21 + #44)
+# CHECK-NEXT: if (!p3.new) r17 = memb(r21+#44)
0xb1 0xe6 0x15 0x9b
# CHECK: if (p3) r17 = memb(r21++#5)
0xb1 0xee 0x15 0x9b
@@ -111,41 +111,41 @@
# Load byte into shifted vector
0xf0 0xc3 0x95 0x90
-# CHECK: r17:16 = memb_fifo(r21 + #31)
+# CHECK: r17:16 = memb_fifo(r21+#31)
0xb0 0xe0 0x95 0x98
-# CHECK: r17:16 = memb_fifo(r21 ++ #5:circ(m1))
+# CHECK: r17:16 = memb_fifo(r21++#5:circ(m1))
0x10 0xe2 0x95 0x98
-# CHECK: r17:16 = memb_fifo(r21 ++ I:circ(m1))
+# CHECK: r17:16 = memb_fifo(r21++I:circ(m1))
# Load half into shifted vector
0xf0 0xc3 0x55 0x90
-# CHECK: r17:16 = memh_fifo(r21 + #62)
+# CHECK: r17:16 = memh_fifo(r21+#62)
0xb0 0xe0 0x55 0x98
-# CHECK: r17:16 = memh_fifo(r21 ++ #10:circ(m1))
+# CHECK: r17:16 = memh_fifo(r21++#10:circ(m1))
0x10 0xe2 0x55 0x98
-# CHECK: r17:16 = memh_fifo(r21 ++ I:circ(m1))
+# CHECK: r17:16 = memh_fifo(r21++I:circ(m1))
# Load halfword
0x91 0xff 0x55 0x3a
-# CHECK: r17 = memh(r21 + r31<<#3)
+# CHECK: r17 = memh(r21+r31<<#3)
0xb1 0xc2 0x40 0x49
# CHECK: r17 = memh(gp+#42)
0x00 0x40 0x00 0x00 0x51 0xc5 0x40 0x49
# CHECK: r17 = memh(##42)
0xf1 0xc3 0x55 0x91
-# CHECK: r17 = memh(r21 + #62)
+# CHECK: r17 = memh(r21+#62)
0xb1 0xe0 0x55 0x99
-# CHECK: r17 = memh(r21 ++ #10:circ(m1))
+# CHECK: r17 = memh(r21++#10:circ(m1))
0x11 0xe2 0x55 0x99
-# CHECK: r17 = memh(r21 ++ I:circ(m1))
+# CHECK: r17 = memh(r21++I:circ(m1))
0x00 0x40 0x00 0x00 0x71 0xd7 0x55 0x9b
-# CHECK: r17 = memh(r21 = ##31)
+# CHECK: r17 = memh(r21=##31)
0xb1 0xc0 0x55 0x9b
# CHECK: r17 = memh(r21++#10)
0x11 0xe0 0x55 0x9d
# CHECK: r17 = memh(r21++m1)
0x11 0xe0 0x55 0x9f
-# CHECK: r17 = memh(r21 ++ m1:brev)
+# CHECK: r17 = memh(r21++m1:brev)
# Load halfword conditionally
0xf1 0xff 0x55 0x30
@@ -169,37 +169,37 @@
# CHECK: p3 = r5
# CHECK-NEXT: if (!p3.new) r17 = memh(r21++#10)
0xf1 0xdb 0x55 0x41
-# CHECK: if (p3) r17 = memh(r21 + #62)
+# CHECK: if (p3) r17 = memh(r21+#62)
0xf1 0xdb 0x55 0x45
-# CHECK: if (!p3) r17 = memh(r21 + #62)
+# CHECK: if (!p3) r17 = memh(r21+#62)
0x03 0x40 0x45 0x85 0xf1 0xdb 0x55 0x43
# CHECK: p3 = r5
-# CHECK-NEXT: if (p3.new) r17 = memh(r21 + #62)
+# CHECK-NEXT: if (p3.new) r17 = memh(r21+#62)
0x03 0x40 0x45 0x85 0xf1 0xdb 0x55 0x47
# CHECK: p3 = r5
-# CHECK-NEXT: if (!p3.new) r17 = memh(r21 + #62)
+# CHECK-NEXT: if (!p3.new) r17 = memh(r21+#62)
# Load unsigned byte
0x91 0xff 0x35 0x3a
-# CHECK: r17 = memub(r21 + r31<<#3)
+# CHECK: r17 = memub(r21+r31<<#3)
0xb1 0xc2 0x20 0x49
# CHECK: r17 = memub(gp+#21)
0x00 0x40 0x00 0x00 0xb1 0xc2 0x20 0x49
# CHECK: r17 = memub(##21)
0xf1 0xc3 0x35 0x91
-# CHECK: r17 = memub(r21 + #31)
+# CHECK: r17 = memub(r21+#31)
0xb1 0xe0 0x35 0x99
-# CHECK: r17 = memub(r21 ++ #5:circ(m1))
+# CHECK: r17 = memub(r21++#5:circ(m1))
0x11 0xe2 0x35 0x99
-# CHECK: r17 = memub(r21 ++ I:circ(m1))
+# CHECK: r17 = memub(r21++I:circ(m1))
0x00 0x40 0x00 0x00 0x71 0xd7 0x35 0x9b
-# CHECK: r17 = memub(r21 = ##31)
+# CHECK: r17 = memub(r21=##31)
0xb1 0xc0 0x35 0x9b
# CHECK: r17 = memub(r21++#5)
0x11 0xe0 0x35 0x9d
# CHECK: r17 = memub(r21++m1)
0x11 0xe0 0x35 0x9f
-# CHECK: r17 = memub(r21 ++ m1:brev)
+# CHECK: r17 = memub(r21++m1:brev)
# Load unsigned byte conditionally
0xf1 0xff 0x35 0x30
@@ -213,15 +213,15 @@
# CHECK: p3 = r5
# CHECK-NEXT: if (!p3.new) r17 = memub(r21+r31<<#3)
0xf1 0xdb 0x35 0x41
-# CHECK: if (p3) r17 = memub(r21 + #31)
+# CHECK: if (p3) r17 = memub(r21+#31)
0x03 0x40 0x45 0x85 0xf1 0xdb 0x35 0x43
# CHECK: p3 = r5
-# CHECK-NEXT: if (p3.new) r17 = memub(r21 + #31)
+# CHECK-NEXT: if (p3.new) r17 = memub(r21+#31)
0xf1 0xdb 0x35 0x45
-# CHECK: if (!p3) r17 = memub(r21 + #31)
+# CHECK: if (!p3) r17 = memub(r21+#31)
0x03 0x40 0x45 0x85 0xf1 0xdb 0x35 0x47
# CHECK: p3 = r5
-# CHECK-NEXT: if (!p3.new) r17 = memub(r21 + #31)
+# CHECK-NEXT: if (!p3.new) r17 = memub(r21+#31)
0xb1 0xe6 0x35 0x9b
# CHECK: if (p3) r17 = memub(r21++#5)
0xb1 0xee 0x35 0x9b
@@ -235,25 +235,25 @@
# Load unsigned halfword
0x91 0xff 0x75 0x3a
-# CHECK: r17 = memuh(r21 + r31<<#3)
+# CHECK: r17 = memuh(r21+r31<<#3)
0xb1 0xc2 0x60 0x49
# CHECK: r17 = memuh(gp+#42)
0x00 0x40 0x00 0x00 0x51 0xc5 0x60 0x49
# CHECK: r17 = memuh(##42)
0xb1 0xc2 0x75 0x91
-# CHECK: r17 = memuh(r21 + #42)
+# CHECK: r17 = memuh(r21+#42)
0xb1 0xe0 0x75 0x99
-# CHECK: r17 = memuh(r21 ++ #10:circ(m1))
+# CHECK: r17 = memuh(r21++#10:circ(m1))
0x11 0xe2 0x75 0x99
-# CHECK: r17 = memuh(r21 ++ I:circ(m1))
+# CHECK: r17 = memuh(r21++I:circ(m1))
0x00 0x40 0x00 0x00 0x71 0xd7 0x75 0x9b
-# CHECK: r17 = memuh(r21 = ##31)
+# CHECK: r17 = memuh(r21=##31)
0xb1 0xc0 0x75 0x9b
# CHECK: r17 = memuh(r21++#10)
0x11 0xe0 0x75 0x9d
# CHECK: r17 = memuh(r21++m1)
0x11 0xe0 0x75 0x9f
-# CHECK: r17 = memuh(r21 ++ m1:brev)
+# CHECK: r17 = memuh(r21++m1:brev)
# Load unsigned halfword conditionally
0xf1 0xff 0x75 0x30
@@ -267,15 +267,15 @@
# CHECK: p3 = r5
# CHECK-NEXT: if (!p3.new) r17 = memuh(r21+r31<<#3)
0xb1 0xda 0x75 0x41
-# CHECK: if (p3) r17 = memuh(r21 + #42)
+# CHECK: if (p3) r17 = memuh(r21+#42)
0xb1 0xda 0x75 0x45
-# CHECK: if (!p3) r17 = memuh(r21 + #42)
+# CHECK: if (!p3) r17 = memuh(r21+#42)
0x03 0x40 0x45 0x85 0xb1 0xda 0x75 0x43
# CHECK: p3 = r5
-# CHECK-NEXT: if (p3.new) r17 = memuh(r21 + #42)
+# CHECK-NEXT: if (p3.new) r17 = memuh(r21+#42)
0x03 0x40 0x45 0x85 0xb1 0xda 0x75 0x47
# CHECK: p3 = r5
-# CHECK-NEXT: if (!p3.new) r17 = memuh(r21 + #42)
+# CHECK-NEXT: if (!p3.new) r17 = memuh(r21+#42)
0xb1 0xe6 0x75 0x9b
# CHECK: if (p3) r17 = memuh(r21++#10)
0xb1 0xee 0x75 0x9b
@@ -289,25 +289,25 @@
# Load word
0x91 0xff 0x95 0x3a
-# CHECK: r17 = memw(r21 + r31<<#3)
+# CHECK: r17 = memw(r21+r31<<#3)
0xb1 0xc2 0x80 0x49
# CHECK: r17 = memw(gp+#84)
0x01 0x40 0x00 0x00 0x91 0xc2 0x80 0x49
# CHECK: r17 = memw(##84)
0xb1 0xc2 0x95 0x91
-# CHECK: r17 = memw(r21 + #84)
+# CHECK: r17 = memw(r21+#84)
0xb1 0xe0 0x95 0x99
-# CHECK: r17 = memw(r21 ++ #20:circ(m1))
+# CHECK: r17 = memw(r21++#20:circ(m1))
0x11 0xe2 0x95 0x99
-# CHECK: r17 = memw(r21 ++ I:circ(m1))
+# CHECK: r17 = memw(r21++I:circ(m1))
0x00 0x40 0x00 0x00 0x71 0xd7 0x95 0x9b
-# CHECK: r17 = memw(r21 = ##31)
+# CHECK: r17 = memw(r21=##31)
0xb1 0xc0 0x95 0x9b
# CHECK: r17 = memw(r21++#20)
0x11 0xe0 0x95 0x9d
# CHECK: r17 = memw(r21++m1)
0x11 0xe0 0x95 0x9f
-# CHECK: r17 = memw(r21 ++ m1:brev)
+# CHECK: r17 = memw(r21++m1:brev)
# Load word conditionally
0xf1 0xff 0x95 0x30
@@ -321,15 +321,15 @@
# CHECK: p3 = r5
# CHECK-NEXT: if (!p3.new) r17 = memw(r21+r31<<#3)
0xb1 0xda 0x95 0x41
-# CHECK: if (p3) r17 = memw(r21 + #84)
+# CHECK: if (p3) r17 = memw(r21+#84)
0xb1 0xda 0x95 0x45
-# CHECK: if (!p3) r17 = memw(r21 + #84)
+# CHECK: if (!p3) r17 = memw(r21+#84)
0x03 0x40 0x45 0x85 0xb1 0xda 0x95 0x43
# CHECK: p3 = r5
-# CHECK-NEXT: if (p3.new) r17 = memw(r21 + #84)
+# CHECK-NEXT: if (p3.new) r17 = memw(r21+#84)
0x03 0x40 0x45 0x85 0xb1 0xda 0x95 0x47
# CHECK: p3 = r5
-# CHECK-NEXT: if (!p3.new) r17 = memw(r21 + #84)
+# CHECK-NEXT: if (!p3.new) r17 = memw(r21+#84)
0xb1 0xe6 0x95 0x9b
# CHECK: if (p3) r17 = memw(r21++#20)
0xb1 0xee 0x95 0x9b
@@ -367,59 +367,59 @@
# Load and unpack bytes to halfwords
0xf1 0xc3 0x35 0x90
-# CHECK: r17 = membh(r21 + #62)
+# CHECK: r17 = membh(r21+#62)
0xf1 0xc3 0x75 0x90
-# CHECK: r17 = memubh(r21 + #62)
+# CHECK: r17 = memubh(r21+#62)
0xf0 0xc3 0xb5 0x90
-# CHECK: r17:16 = memubh(r21 + #124)
+# CHECK: r17:16 = memubh(r21+#124)
0xf0 0xc3 0xf5 0x90
-# CHECK: r17:16 = membh(r21 + #124)
+# CHECK: r17:16 = membh(r21+#124)
0xb1 0xe0 0x35 0x98
-# CHECK: r17 = membh(r21 ++ #10:circ(m1))
+# CHECK: r17 = membh(r21++#10:circ(m1))
0x11 0xe2 0x35 0x98
-# CHECK: r17 = membh(r21 ++ I:circ(m1))
+# CHECK: r17 = membh(r21++I:circ(m1))
0xb1 0xe0 0x75 0x98
-# CHECK: r17 = memubh(r21 ++ #10:circ(m1))
+# CHECK: r17 = memubh(r21++#10:circ(m1))
0x11 0xe2 0x75 0x98
-# CHECK: r17 = memubh(r21 ++ I:circ(m1))
+# CHECK: r17 = memubh(r21++I:circ(m1))
0xb0 0xe0 0xf5 0x98
-# CHECK: r17:16 = membh(r21 ++ #20:circ(m1))
+# CHECK: r17:16 = membh(r21++#20:circ(m1))
0x10 0xe2 0xf5 0x98
-# CHECK: r17:16 = membh(r21 ++ I:circ(m1))
+# CHECK: r17:16 = membh(r21++I:circ(m1))
0xb0 0xe0 0xb5 0x98
-# CHECK: r17:16 = memubh(r21 ++ #20:circ(m1))
+# CHECK: r17:16 = memubh(r21++#20:circ(m1))
0x10 0xe2 0xb5 0x98
-# CHECK: r17:16 = memubh(r21 ++ I:circ(m1))
+# CHECK: r17:16 = memubh(r21++I:circ(m1))
0x00 0x40 0x00 0x00 0x71 0xd7 0x35 0x9a
-# CHECK: r17 = membh(r21 = ##31)
+# CHECK: r17 = membh(r21=##31)
0xb1 0xc0 0x35 0x9a
# CHECK: r17 = membh(r21++#10)
0x00 0x40 0x00 0x00 0x71 0xd7 0x75 0x9a
-# CHECK: r17 = memubh(r21 = ##31)
+# CHECK: r17 = memubh(r21=##31)
0xb1 0xc0 0x75 0x9a
# CHECK: r17 = memubh(r21++#10)
0x00 0x40 0x00 0x00 0x70 0xd7 0xb5 0x9a
-# CHECK: r17:16 = memubh(r21 = ##31)
+# CHECK: r17:16 = memubh(r21=##31)
0xb0 0xc0 0xb5 0x9a
# CHECK: r17:16 = memubh(r21++#20)
0x00 0x40 0x00 0x00 0x70 0xd7 0xf5 0x9a
-# CHECK: r17:16 = membh(r21 = ##31)
+# CHECK: r17:16 = membh(r21=##31)
0xb0 0xc0 0xf5 0x9a
# CHECK: r17:16 = membh(r21++#20)
0x00 0x40 0x00 0x00 0xf1 0xf7 0x35 0x9c
-# CHECK: r17 = membh(r21<<#3 + ##31)
+# CHECK: r17 = membh(r21<<#3+##31)
0x11 0xe0 0x35 0x9c
# CHECK: r17 = membh(r21++m1)
0x00 0x40 0x00 0x00 0xf1 0xf7 0x75 0x9c
-# CHECK: r17 = memubh(r21<<#3 + ##31)
+# CHECK: r17 = memubh(r21<<#3+##31)
0x11 0xe0 0x75 0x9c
# CHECK: r17 = memubh(r21++m1)
0x00 0x40 0x00 0x00 0xf0 0xf7 0xf5 0x9c
-# CHECK: r17:16 = membh(r21<<#3 + ##31)
+# CHECK: r17:16 = membh(r21<<#3+##31)
0x10 0xe0 0xf5 0x9c
# CHECK: r17:16 = membh(r21++m1)
0x00 0x40 0x00 0x00 0xf0 0xf7 0xb5 0x9c
-# CHECK: r17:16 = memubh(r21<<#3 + ##31)
+# CHECK: r17:16 = memubh(r21<<#3+##31)
0x11 0xe0 0x35 0x9c
# CHECK: r17 = membh(r21++m1)
0x11 0xe0 0x75 0x9c
@@ -429,10 +429,10 @@
0x10 0xe0 0xb5 0x9c
# CHECK: r17:16 = memubh(r21++m1)
0x11 0xe0 0x35 0x9e
-# CHECK: r17 = membh(r21 ++ m1:brev)
+# CHECK: r17 = membh(r21++m1:brev)
0x11 0xe0 0x75 0x9e
-# CHECK: r17 = memubh(r21 ++ m1:brev)
+# CHECK: r17 = memubh(r21++m1:brev)
0x10 0xe0 0xb5 0x9e
-# CHECK: r17:16 = memubh(r21 ++ m1:brev)
+# CHECK: r17:16 = memubh(r21++m1:brev)
0x10 0xe0 0xf5 0x9e
-# CHECK: r17:16 = membh(r21 ++ m1:brev)
+# CHECK: r17:16 = membh(r21++m1:brev)
Modified: llvm/trunk/test/MC/Disassembler/Hexagon/nv_j.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/nv_j.txt?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Hexagon/nv_j.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Hexagon/nv_j.txt Fri Feb 10 09:33:13 2017
@@ -4,133 +4,133 @@
# Jump to address conditioned on new register value
0x11 0x40 0x71 0x70 0x92 0xd5 0x02 0x20
# CHECK: r17 = r17
-# CHECK-NEXT: if (cmp.eq(r17.new, r21)) jump:nt
+# CHECK-NEXT: if (cmp.eq(r17.new,r21)) jump:nt
0x11 0x40 0x71 0x70 0x92 0xf5 0x02 0x20
# CHECK: r17 = r17
-# CHECK-NEXT: if (cmp.eq(r17.new, r21)) jump:t
+# CHECK-NEXT: if (cmp.eq(r17.new,r21)) jump:t
0x11 0x40 0x71 0x70 0x92 0xd5 0x42 0x20
# CHECK: r17 = r17
-# CHECK-NEXT: if (!cmp.eq(r17.new, r21)) jump:nt
+# CHECK-NEXT: if (!cmp.eq(r17.new,r21)) jump:nt
0x11 0x40 0x71 0x70 0x92 0xf5 0x42 0x20
# CHECK: r17 = r17
-# CHECK-NEXT: if (!cmp.eq(r17.new, r21)) jump:t
+# CHECK-NEXT: if (!cmp.eq(r17.new,r21)) jump:t
0x11 0x40 0x71 0x70 0x92 0xd5 0x82 0x20
# CHECK: r17 = r17
-# CHECK-NEXT: if (cmp.gt(r17.new, r21)) jump:nt
+# CHECK-NEXT: if (cmp.gt(r17.new,r21)) jump:nt
0x11 0x40 0x71 0x70 0x92 0xf5 0x82 0x20
# CHECK: r17 = r17
-# CHECK-NEXT: if (cmp.gt(r17.new, r21)) jump:t
+# CHECK-NEXT: if (cmp.gt(r17.new,r21)) jump:t
0x11 0x40 0x71 0x70 0x92 0xd5 0xc2 0x20
# CHECK: r17 = r17
-# CHECK-NEXT: if (!cmp.gt(r17.new, r21)) jump:nt
+# CHECK-NEXT: if (!cmp.gt(r17.new,r21)) jump:nt
0x11 0x40 0x71 0x70 0x92 0xf5 0xc2 0x20
# CHECK: r17 = r17
-# CHECK-NEXT: if (!cmp.gt(r17.new, r21)) jump:t
+# CHECK-NEXT: if (!cmp.gt(r17.new,r21)) jump:t
0x11 0x40 0x71 0x70 0x92 0xd5 0x02 0x21
# CHECK: r17 = r17
-# CHECK-NEXT: if (cmp.gtu(r17.new, r21)) jump:nt
+# CHECK-NEXT: if (cmp.gtu(r17.new,r21)) jump:nt
0x11 0x40 0x71 0x70 0x92 0xf5 0x02 0x21
# CHECK: r17 = r17
-# CHECK-NEXT: if (cmp.gtu(r17.new, r21)) jump:t
+# CHECK-NEXT: if (cmp.gtu(r17.new,r21)) jump:t
0x11 0x40 0x71 0x70 0x92 0xd5 0x42 0x21
# CHECK: r17 = r17
-# CHECK-NEXT: if (!cmp.gtu(r17.new, r21)) jump:nt
+# CHECK-NEXT: if (!cmp.gtu(r17.new,r21)) jump:nt
0x11 0x40 0x71 0x70 0x92 0xf5 0x42 0x21
# CHECK: r17 = r17
-# CHECK-NEXT: if (!cmp.gtu(r17.new, r21)) jump:t
+# CHECK-NEXT: if (!cmp.gtu(r17.new,r21)) jump:t
0x11 0x40 0x71 0x70 0x92 0xd5 0x82 0x21
# CHECK: r17 = r17
-# CHECK-NEXT: if (cmp.gt(r21, r17.new)) jump:nt
+# CHECK-NEXT: if (cmp.gt(r21,r17.new)) jump:nt
0x11 0x40 0x71 0x70 0x92 0xf5 0x82 0x21
# CHECK: r17 = r17
-# CHECK-NEXT: if (cmp.gt(r21, r17.new)) jump:t
+# CHECK-NEXT: if (cmp.gt(r21,r17.new)) jump:t
0x11 0x40 0x71 0x70 0x92 0xd5 0xc2 0x21
# CHECK: r17 = r17
-# CHECK-NEXT: if (!cmp.gt(r21, r17.new)) jump:nt
+# CHECK-NEXT: if (!cmp.gt(r21,r17.new)) jump:nt
0x11 0x40 0x71 0x70 0x92 0xf5 0xc2 0x21
# CHECK: r17 = r17
-# CHECK-NEXT: if (!cmp.gt(r21, r17.new)) jump:t
+# CHECK-NEXT: if (!cmp.gt(r21,r17.new)) jump:t
0x11 0x40 0x71 0x70 0x92 0xd5 0x02 0x22
# CHECK: r17 = r17
-# CHECK-NEXT: if (cmp.gtu(r21, r17.new)) jump:nt
+# CHECK-NEXT: if (cmp.gtu(r21,r17.new)) jump:nt
0x11 0x40 0x71 0x70 0x92 0xf5 0x02 0x22
# CHECK: r17 = r17
-# CHECK-NEXT: if (cmp.gtu(r21, r17.new)) jump:t
+# CHECK-NEXT: if (cmp.gtu(r21,r17.new)) jump:t
0x11 0x40 0x71 0x70 0x92 0xd5 0x42 0x22
# CHECK: r17 = r17
-# CHECK-NEXT: if (!cmp.gtu(r21, r17.new)) jump:nt
+# CHECK-NEXT: if (!cmp.gtu(r21,r17.new)) jump:nt
0x11 0x40 0x71 0x70 0x92 0xf5 0x42 0x22
# CHECK: r17 = r17
-# CHECK-NEXT: if (!cmp.gtu(r21, r17.new)) jump:t
+# CHECK-NEXT: if (!cmp.gtu(r21,r17.new)) jump:t
0x11 0x40 0x71 0x70 0x92 0xd5 0x02 0x24
# CHECK: r17 = r17
-# CHECK-NEXT: if (cmp.eq(r17.new, #21)) jump:nt
+# CHECK-NEXT: if (cmp.eq(r17.new,#21)) jump:nt
0x11 0x40 0x71 0x70 0x92 0xf5 0x02 0x24
# CHECK: r17 = r17
-# CHECK-NETX: if (cmp.eq(r17.new, #21)) jump:t
+# CHECK-NETX: if (cmp.eq(r17.new,#21)) jump:t
0x11 0x40 0x71 0x70 0x92 0xd5 0x42 0x24
# CHECK: r17 = r17
-# CHECK-NEXT: if (!cmp.eq(r17.new, #21)) jump:nt
+# CHECK-NEXT: if (!cmp.eq(r17.new,#21)) jump:nt
0x11 0x40 0x71 0x70 0x92 0xf5 0x42 0x24
# CHECK: r17 = r17
-# CHECK-NEXT: if (!cmp.eq(r17.new, #21)) jump:t
+# CHECK-NEXT: if (!cmp.eq(r17.new,#21)) jump:t
0x11 0x40 0x71 0x70 0x92 0xd5 0x82 0x24
# CHECK: r17 = r17
-# CHECK-NEXT: if (cmp.gt(r17.new, #21)) jump:nt
+# CHECK-NEXT: if (cmp.gt(r17.new,#21)) jump:nt
0x11 0x40 0x71 0x70 0x92 0xf5 0x82 0x24
# CHECK: r17 = r17
-# CHECK-NEXT: if (cmp.gt(r17.new, #21)) jump:t
+# CHECK-NEXT: if (cmp.gt(r17.new,#21)) jump:t
0x11 0x40 0x71 0x70 0x92 0xd5 0xc2 0x24
# CHECK: r17 = r17
-# CHECK-NEXT: if (!cmp.gt(r17.new, #21)) jump:nt
+# CHECK-NEXT: if (!cmp.gt(r17.new,#21)) jump:nt
0x11 0x40 0x71 0x70 0x92 0xf5 0xc2 0x24
# CHECK: r17 = r17
-# CHECK-NEXT: if (!cmp.gt(r17.new, #21)) jump:t
+# CHECK-NEXT: if (!cmp.gt(r17.new,#21)) jump:t
0x11 0x40 0x71 0x70 0x92 0xd5 0x02 0x25
# CHECK: r17 = r17
-# CHECK-NEXT: if (cmp.gtu(r17.new, #21)) jump:nt
+# CHECK-NEXT: if (cmp.gtu(r17.new,#21)) jump:nt
0x11 0x40 0x71 0x70 0x92 0xf5 0x02 0x25
# CHECK: r17 = r17
-# CHECK-NEXT: if (cmp.gtu(r17.new, #21)) jump:t
+# CHECK-NEXT: if (cmp.gtu(r17.new,#21)) jump:t
0x11 0x40 0x71 0x70 0x92 0xd5 0x42 0x25
# CHECK: r17 = r17
-# CHECK-NEXT: if (!cmp.gtu(r17.new, #21)) jump:nt
+# CHECK-NEXT: if (!cmp.gtu(r17.new,#21)) jump:nt
0x11 0x40 0x71 0x70 0x92 0xf5 0x42 0x25
# CHECK: r17 = r17
-# CHECK-NEXT: if (!cmp.gtu(r17.new, #21)) jump:t
+# CHECK-NEXT: if (!cmp.gtu(r17.new,#21)) jump:t
0x11 0x40 0x71 0x70 0x92 0xc0 0x82 0x25
# CHECK: r17 = r17
-# CHECK-NEXT: if (tstbit(r17.new, #0)) jump:nt
+# CHECK-NEXT: if (tstbit(r17.new,#0)) jump:nt
0x11 0x40 0x71 0x70 0x92 0xe0 0x82 0x25
# CHECK: r17 = r17
-# CHECK-NEXT: if (tstbit(r17.new, #0)) jump:t
+# CHECK-NEXT: if (tstbit(r17.new,#0)) jump:t
0x11 0x40 0x71 0x70 0x92 0xc0 0xc2 0x25
# CHECK: r17 = r17
-# CHECK-NEXT: if (!tstbit(r17.new, #0)) jump:nt
+# CHECK-NEXT: if (!tstbit(r17.new,#0)) jump:nt
0x11 0x40 0x71 0x70 0x92 0xe0 0xc2 0x25
# CHECK: r17 = r17
-# CHECK-NEXT: if (!tstbit(r17.new, #0)) jump:t
+# CHECK-NEXT: if (!tstbit(r17.new,#0)) jump:t
0x11 0x40 0x71 0x70 0x92 0xc0 0x02 0x26
# CHECK: r17 = r17
-# CHECK-NEXT: if (cmp.eq(r17.new, #-1)) jump:nt
+# CHECK-NEXT: if (cmp.eq(r17.new,#-1)) jump:nt
0x11 0x40 0x71 0x70 0x92 0xe0 0x02 0x26
# CHECK: r17 = r17
-# CHECK-NEXT: if (cmp.eq(r17.new, #-1)) jump:t
+# CHECK-NEXT: if (cmp.eq(r17.new,#-1)) jump:t
0x11 0x40 0x71 0x70 0x92 0xc0 0x42 0x26
# CHECK: r17 = r17
-# CHECK-NEXT: if (!cmp.eq(r17.new, #-1)) jump:nt
+# CHECK-NEXT: if (!cmp.eq(r17.new,#-1)) jump:nt
0x11 0x40 0x71 0x70 0x92 0xe0 0x42 0x26
# CHECK: r17 = r17
-# CHECK-NEXT: if (!cmp.eq(r17.new, #-1)) jump:t
+# CHECK-NEXT: if (!cmp.eq(r17.new,#-1)) jump:t
0x11 0x40 0x71 0x70 0x92 0xc0 0x82 0x26
# CHECK: r17 = r17
-# CHECK-NEXT: if (cmp.gt(r17.new, #-1)) jump:nt
+# CHECK-NEXT: if (cmp.gt(r17.new,#-1)) jump:nt
0x11 0x40 0x71 0x70 0x92 0xe0 0x82 0x26
# CHECK: r17 = r17
-# CHECK-NEXT: if (cmp.gt(r17.new, #-1)) jump:t
+# CHECK-NEXT: if (cmp.gt(r17.new,#-1)) jump:t
0x11 0x40 0x71 0x70 0x92 0xc0 0xc2 0x26
# CHECK: r17 = r17
-# CHECK-NEXT: if (!cmp.gt(r17.new, #-1)) jump:nt
+# CHECK-NEXT: if (!cmp.gt(r17.new,#-1)) jump:nt
0x11 0x40 0x71 0x70 0x92 0xe0 0xc2 0x26
# CHECK: r17 = r17
-# CHECK-NEXT: if (!cmp.gt(r17.new, #-1)) jump:t
+# CHECK-NEXT: if (!cmp.gt(r17.new,#-1)) jump:t
Modified: llvm/trunk/test/MC/Disassembler/Hexagon/nv_st.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/nv_st.txt?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Hexagon/nv_st.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Hexagon/nv_st.txt Fri Feb 10 09:33:13 2017
@@ -4,7 +4,7 @@
# Store new-value byte
0x1f 0x40 0x7f 0x70 0x82 0xf5 0xb1 0x3b
# CHECK: r31 = r31
-# CHECK-NEXT: memb(r17 + r21<<#3) = r31.new
+# CHECK-NEXT: memb(r17+r21<<#3) = r31.new
0x1f 0x40 0x7f 0x70 0x11 0xc2 0xa0 0x48
# CHECK: r31 = r31
# CHECK-NEXT: memb(gp+#17) = r31.new
@@ -13,10 +13,10 @@
# CHECK-NEXT: memb(r17+#21) = r31.new
0x1f 0x40 0x7f 0x70 0x02 0xe2 0xb1 0xa9
# CHECK: r31 = r31
-# CHECK-NEXT: memb(r17 ++ I:circ(m1)) = r31.new
+# CHECK-NEXT: memb(r17++I:circ(m1)) = r31.new
0x1f 0x40 0x7f 0x70 0x28 0xe2 0xb1 0xa9
# CHECK: r31 = r31
-# CHECK-NEXT: memb(r17 ++ #5:circ(m1)) = r31.new
+# CHECK-NEXT: memb(r17++#5:circ(m1)) = r31.new
0x1f 0x40 0x7f 0x70 0x28 0xc2 0xb1 0xab
# CHECK: r31 = r31
# CHECK-NEXT: memb(r17++#5) = r31.new
@@ -25,7 +25,7 @@
# CHECK-NEXT: memb(r17++m1) = r31.new
0x1f 0x40 0x7f 0x70 0x00 0xe2 0xb1 0xaf
# CHECK: r31 = r31
-# CHECK-NEXT: memb(r17 ++ m1:brev) = r31.new
+# CHECK-NEXT: memb(r17++m1:brev) = r31.new
# Store new-value byte conditionally
0x1f 0x40 0x7f 0x70 0xe2 0xf5 0xb1 0x34
@@ -74,7 +74,7 @@
# Store new-value halfword
0x1f 0x40 0x7f 0x70 0x8a 0xf5 0xb1 0x3b
# CHECK: r31 = r31
-# CHECK-NEXT: memh(r17 + r21<<#3) = r31.new
+# CHECK-NEXT: memh(r17+r21<<#3) = r31.new
0x1f 0x40 0x7f 0x70 0x15 0xca 0xa0 0x48
# CHECK: r31 = r31
# CHECK-NEXT: memh(gp+#42) = r31.new
@@ -83,10 +83,10 @@
# CHECK-NEXT: memh(r17+#42) = r31.new
0x1f 0x40 0x7f 0x70 0x02 0xea 0xb1 0xa9
# CHECK: r31 = r31
-# CHECK-NEXT: memh(r17 ++ I:circ(m1)) = r31.new
+# CHECK-NEXT: memh(r17++I:circ(m1)) = r31.new
0x1f 0x40 0x7f 0x70 0x28 0xea 0xb1 0xa9
# CHECK: r31 = r31
-# CHECK-NEXT: memh(r17 ++ #10:circ(m1)) = r31.new
+# CHECK-NEXT: memh(r17++#10:circ(m1)) = r31.new
0x1f 0x40 0x7f 0x70 0x28 0xca 0xb1 0xab
# CHECK: r31 = r31
# CHECK-NEXT: memh(r17++#10) = r31.new
@@ -95,7 +95,7 @@
# CHECK-NEXT: memh(r17++m1) = r31.new
0x1f 0x40 0x7f 0x70 0x00 0xea 0xb1 0xaf
# CHECK: r31 = r31
-# CHECK-NEXT: memh(r17 ++ m1:brev) = r31.new
+# CHECK-NEXT: memh(r17++m1:brev) = r31.new
# Store new-value halfword conditionally
0x1f 0x40 0x7f 0x70 0xea 0xf5 0xb1 0x34
@@ -144,7 +144,7 @@
# Store new-value word
0x1f 0x40 0x7f 0x70 0x92 0xf5 0xb1 0x3b
# CHECK: r31 = r31
-# CHECK-NEXT: memw(r17 + r21<<#3) = r31.new
+# CHECK-NEXT: memw(r17+r21<<#3) = r31.new
0x1f 0x40 0x7f 0x70 0x15 0xd2 0xa0 0x48
# CHECK: r31 = r31
# CHECK-NEXT: memw(gp+#84) = r31.new
@@ -153,10 +153,10 @@
# CHECK-NEXT: memw(r17+#84) = r31.new
0x1f 0x40 0x7f 0x70 0x02 0xf2 0xb1 0xa9
# CHECK: r31 = r31
-# CHECK-NEXT: memw(r17 ++ I:circ(m1)) = r31.new
+# CHECK-NEXT: memw(r17++I:circ(m1)) = r31.new
0x1f 0x40 0x7f 0x70 0x28 0xf2 0xb1 0xa9
# CHECK: r31 = r31
-# CHECK-NEXT: memw(r17 ++ #20:circ(m1)) = r31.new
+# CHECK-NEXT: memw(r17++#20:circ(m1)) = r31.new
0x1f 0x40 0x7f 0x70 0x28 0xd2 0xb1 0xab
# CHECK: r31 = r31
# CHECK-NEXT: memw(r17++#20) = r31.new
@@ -165,7 +165,7 @@
# CHECK-NEXT: memw(r17++m1) = r31.new
0x1f 0x40 0x7f 0x70 0x00 0xf2 0xb1 0xaf
# CHECK: r31 = r31
-# CHECK-NEXT: memw(r17 ++ m1:brev) = r31.new
+# CHECK-NEXT: memw(r17++m1:brev) = r31.new
# Store new-value word conditionally
0x1f 0x40 0x7f 0x70 0xf2 0xf5 0xb1 0x34
Modified: llvm/trunk/test/MC/Disassembler/Hexagon/st.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/st.txt?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Hexagon/st.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Hexagon/st.txt Fri Feb 10 09:33:13 2017
@@ -3,7 +3,7 @@
# Store doubleword
0x9e 0xf5 0xd1 0x3b
-# CHECK: memd(r17 + r21<<#3) = r31:30
+# CHECK: memd(r17+r21<<#3) = r31:30
0x28 0xd4 0xc0 0x48
# CHECK: memd(gp+#320) = r21:20
0x02 0x40 0x00 0x00 0x28 0xd4 0xc0 0x48
@@ -11,17 +11,17 @@
0x15 0xd4 0xd1 0xa1
# CHECK: memd(r17+#168) = r21:20
0x02 0xf4 0xd1 0xa9
-# CHECK: memd(r17 ++ I:circ(m1)) = r21:20
+# CHECK: memd(r17++I:circ(m1)) = r21:20
0x28 0xf4 0xd1 0xa9
-# CHECK: memd(r17 ++ #40:circ(m1)) = r21:20
+# CHECK: memd(r17++#40:circ(m1)) = r21:20
0x28 0xd4 0xd1 0xab
# CHECK: memd(r17++#40) = r21:20
0x00 0x40 0x00 0x00 0xd5 0xfe 0xd1 0xad
-# CHECK: memd(r17<<#3 + ##21) = r31:30
+# CHECK: memd(r17<<#3+##21) = r31:30
0x00 0xf4 0xd1 0xad
# CHECK: memd(r17++m1) = r21:20
0x00 0xf4 0xd1 0xaf
-# CHECK: memd(r17 ++ m1:brev) = r21:20
+# CHECK: memd(r17++m1:brev) = r21:20
# Store doubleword conditionally
0xfe 0xf5 0xd1 0x34
@@ -67,9 +67,9 @@
# Store byte
0x9f 0xf5 0x11 0x3b
-# CHECK: memb(r17 + r21<<#3) = r31
+# CHECK: memb(r17+r21<<#3) = r31
0x9f 0xca 0x11 0x3c
-# CHECK: memb(r17+#21)=#31
+# CHECK: memb(r17+#21) = #31
0x15 0xd5 0x00 0x48
# CHECK: memb(gp+#21) = r21
0x00 0x40 0x00 0x00 0x15 0xd5 0x00 0x48
@@ -77,17 +77,17 @@
0x15 0xd5 0x11 0xa1
# CHECK: memb(r17+#21) = r21
0x02 0xf5 0x11 0xa9
-# CHECK: memb(r17 ++ I:circ(m1)) = r21
+# CHECK: memb(r17++I:circ(m1)) = r21
0x28 0xf5 0x11 0xa9
-# CHECK: memb(r17 ++ #5:circ(m1)) = r21
+# CHECK: memb(r17++#5:circ(m1)) = r21
0x28 0xd5 0x11 0xab
# CHECK: memb(r17++#5) = r21
0x00 0x40 0x00 0x00 0xd5 0xff 0x11 0xad
-# CHECK: memb(r17<<#3 + ##21) = r31
+# CHECK: memb(r17<<#3+##21) = r31
0x00 0xf5 0x11 0xad
# CHECK: memb(r17++m1) = r21
0x00 0xf5 0x11 0xaf
-# CHECK: memb(r17 ++ m1:brev) = r21
+# CHECK: memb(r17++m1:brev) = r21
# Store byte conditionally
0xff 0xf5 0x11 0x34
@@ -101,15 +101,15 @@
# CHECK: p3 = r5
# CHECK-NEXT: if (!p3.new) memb(r17+r21<<#3) = r31
0xff 0xca 0x11 0x38
-# CHECK: if (p3) memb(r17+#21)=#31
+# CHECK: if (p3) memb(r17+#21) = #31
0xff 0xca 0x91 0x38
-# CHECK: if (!p3) memb(r17+#21)=#31
+# CHECK: if (!p3) memb(r17+#21) = #31
0x03 0x40 0x45 0x85 0xff 0xca 0x11 0x39
# CHECK: p3 = r5
-# CHECK-NEXT: if (p3.new) memb(r17+#21)=#31
+# CHECK-NEXT: if (p3.new) memb(r17+#21) = #31
0x03 0x40 0x45 0x85 0xff 0xca 0x91 0x39
# CHECK: p3 = r5
-# CHECK-NEXT: if (!p3.new) memb(r17+#21)=#31
+# CHECK-NEXT: if (!p3.new) memb(r17+#21) = #31
0xab 0xdf 0x11 0x40
# CHECK: if (p3) memb(r17+#21) = r31
0xab 0xdf 0x11 0x44
@@ -143,11 +143,11 @@
# Store halfword
0x9f 0xf5 0x51 0x3b
-# CHECK: memh(r17 + r21<<#3) = r31
+# CHECK: memh(r17+r21<<#3) = r31
0x9f 0xf5 0x71 0x3b
-# CHECK: memh(r17 + r21<<#3) = r31.h
+# CHECK: memh(r17+r21<<#3) = r31.h
0x95 0xcf 0x31 0x3c
-# CHECK: memh(r17+#62)=#21
+# CHECK: memh(r17+#62) = #21
0x00 0x40 0x00 0x00 0x2a 0xd5 0x40 0x48
# CHECK: memh(##42) = r21
0x00 0x40 0x00 0x00 0x2a 0xd5 0x60 0x48
@@ -161,29 +161,29 @@
0x15 0xdf 0x71 0xa1
# CHECK: memh(r17+#42) = r31.h
0x02 0xf5 0x51 0xa9
-# CHECK: memh(r17 ++ I:circ(m1)) = r21
+# CHECK: memh(r17++I:circ(m1)) = r21
0x28 0xf5 0x51 0xa9
-# CHECK: memh(r17 ++ #10:circ(m1)) = r21
+# CHECK: memh(r17++#10:circ(m1)) = r21
0x02 0xf5 0x71 0xa9
-# CHECK: memh(r17 ++ I:circ(m1)) = r21.h
+# CHECK: memh(r17++I:circ(m1)) = r21.h
0x28 0xf5 0x71 0xa9
-# CHECK: memh(r17 ++ #10:circ(m1)) = r21.h
+# CHECK: memh(r17++#10:circ(m1)) = r21.h
0x28 0xd5 0x51 0xab
# CHECK: memh(r17++#10) = r21
0x00 0x40 0x00 0x00 0xd5 0xff 0x51 0xad
-# CHECK: memh(r17<<#3 + ##21) = r31
+# CHECK: memh(r17<<#3+##21) = r31
0x28 0xd5 0x71 0xab
# CHECK: memh(r17++#10) = r21.h
0x00 0x40 0x00 0x00 0xd5 0xff 0x71 0xad
-# CHECK: memh(r17<<#3 + ##21) = r31.h
+# CHECK: memh(r17<<#3+##21) = r31.h
0x00 0xf5 0x51 0xad
# CHECK: memh(r17++m1) = r21
0x00 0xf5 0x71 0xad
# CHECK: memh(r17++m1) = r21.h
0x00 0xf5 0x51 0xaf
-# CHECK: memh(r17 ++ m1:brev) = r21
+# CHECK: memh(r17++m1:brev) = r21
0x00 0xf5 0x71 0xaf
-# CHECK: memh(r17 ++ m1:brev) = r21.h
+# CHECK: memh(r17++m1:brev) = r21.h
# Store halfword conditionally
0xff 0xf5 0x51 0x34
@@ -207,15 +207,15 @@
# CHECK: p3 = r5
# CHECK-NEXT: if (!p3.new) memh(r17+r21<<#3) = r31.h
0xf5 0xcf 0x31 0x38
-# CHECK: if (p3) memh(r17+#62)=#21
+# CHECK: if (p3) memh(r17+#62) = #21
0xf5 0xcf 0xb1 0x38
-# CHECK: if (!p3) memh(r17+#62)=#21
+# CHECK: if (!p3) memh(r17+#62) = #21
0x03 0x40 0x45 0x85 0xf5 0xcf 0x31 0x39
# CHECK: p3 = r5
-# CHECK-NEXT: if (p3.new) memh(r17+#62)=#21
+# CHECK-NEXT: if (p3.new) memh(r17+#62) = #21
0x03 0x40 0x45 0x85 0xf5 0xcf 0xb1 0x39
# CHECK: p3 = r5
-# CHECK-NEXT: if (!p3.new) memh(r17+#62)=#21
+# CHECK-NEXT: if (!p3.new) memh(r17+#62) = #21
0xfb 0xd5 0x51 0x40
# CHECK: if (p3) memh(r17+#62) = r21
0xfb 0xd5 0x71 0x40
@@ -279,29 +279,29 @@
# Store word
0x9f 0xf5 0x91 0x3b
-# CHECK: memw(r17 + r21<<#3) = r31
+# CHECK: memw(r17+r21<<#3) = r31
0x9f 0xca 0x51 0x3c
-# CHECK: memw(r17{{ *}}+{{ *}}#84)=#31
+# CHECK: memw(r17+#84) = #31
0x15 0xdf 0x80 0x48
# CHECK: memw(gp+#84) = r31
0x01 0x40 0x00 0x00 0x14 0xd5 0x80 0x48
# CHECK: memw(##84) = r21
0x9f 0xca 0x51 0x3c
-# CHECK: memw(r17+#84)=#31
+# CHECK: memw(r17+#84) = #31
0x15 0xdf 0x91 0xa1
# CHECK: memw(r17+#84) = r31
0x02 0xf5 0x91 0xa9
-# CHECK: memw(r17 ++ I:circ(m1)) = r21
+# CHECK: memw(r17++I:circ(m1)) = r21
0x28 0xf5 0x91 0xa9
-# CHECK: memw(r17 ++ #20:circ(m1)) = r21
+# CHECK: memw(r17++#20:circ(m1)) = r21
0x28 0xd5 0x91 0xab
# CHECK: memw(r17++#20) = r21
0x00 0x40 0x00 0x00 0xd5 0xff 0x91 0xad
-# CHECK: memw(r17<<#3 + ##21) = r31
+# CHECK: memw(r17<<#3+##21) = r31
0x00 0xf5 0x91 0xad
# CHECK: memw(r17++m1) = r21
0x00 0xf5 0x91 0xaf
-# CHECK: memw(r17 ++ m1:brev) = r21
+# CHECK: memw(r17++m1:brev) = r21
# Store word conditionally
0xff 0xf5 0x91 0x34
@@ -315,15 +315,15 @@
# CHECK: p3 = r5
# CHECK-NEXT: if (!p3.new) memw(r17+r21<<#3) = r31
0xff 0xca 0x51 0x38
-# CHECK: if (p3) memw(r17+#84)=#31
+# CHECK: if (p3) memw(r17+#84) = #31
0xff 0xca 0xd1 0x38
-# CHECK: if (!p3) memw(r17+#84)=#31
+# CHECK: if (!p3) memw(r17+#84) = #31
0x03 0x40 0x45 0x85 0xff 0xca 0x51 0x39
# CHECK: p3 = r5
-# CHECK-NEXT: if (p3.new) memw(r17+#84)=#31
+# CHECK-NEXT: if (p3.new) memw(r17+#84) = #31
0x03 0x40 0x45 0x85 0xff 0xca 0xd1 0x39
# CHECK: p3 = r5
-# CHECK-NEXT: if (!p3.new) memw(r17+#84)=#31
+# CHECK-NEXT: if (!p3.new) memw(r17+#84) = #31
0xab 0xdf 0x91 0x40
# CHECK: if (p3) memw(r17+#84) = r31
0xab 0xdf 0x91 0x44
Modified: llvm/trunk/test/MC/Disassembler/Hexagon/system_user.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/system_user.txt?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Hexagon/system_user.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Hexagon/system_user.txt Fri Feb 10 09:33:13 2017
@@ -9,9 +9,9 @@
# Store conditional
0x03 0xd5 0xb1 0xa0
-# CHECK: memw_locked(r17, p3) = r21
+# CHECK: memw_locked(r17,p3) = r21
0x03 0xd4 0xf1 0xa0
-# CHECK: memd_locked(r17, p3) = r21:20
+# CHECK: memd_locked(r17,p3) = r21:20
# Memory barrier
0x00 0xc0 0x00 0xa8
@@ -19,7 +19,7 @@
# Data cache prefetch
0x15 0xc0 0x11 0x94
-# CHECK: dcfetch(r17 + #168)
+# CHECK: dcfetch(r17+#168)
# Send value to ETM trace
0x00 0xc0 0x51 0x62
Modified: llvm/trunk/test/MC/Disassembler/Hexagon/xtype_alu.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/xtype_alu.txt?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Hexagon/xtype_alu.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Hexagon/xtype_alu.txt Fri Feb 10 09:33:13 2017
@@ -11,137 +11,137 @@
# Add and accumulate
0xff 0xd1 0x35 0xdb
-# CHECK: r17 = add(r21, add(r31, #23))
+# CHECK: r17 = add(r21,add(r31,#23))
0xff 0xd1 0xb5 0xdb
-# CHECK: r17 = add(r21, sub(#23, r31))
+# CHECK: r17 = add(r21,sub(#23,r31))
0xf1 0xc2 0x15 0xe2
-# CHECK: r17 += add(r21, #23)
+# CHECK: r17 += add(r21,#23)
0xf1 0xc2 0x95 0xe2
-# CHECK: r17 -= add(r21, #23)
+# CHECK: r17 -= add(r21,#23)
0x31 0xdf 0x15 0xef
-# CHECK: r17 += add(r21, r31)
+# CHECK: r17 += add(r21,r31)
0x31 0xdf 0x95 0xef
-# CHECK: r17 -= add(r21, r31)
+# CHECK: r17 -= add(r21,r31)
# Add doublewords
0xf0 0xde 0x14 0xd3
-# CHECK: r17:16 = add(r21:20, r31:30)
+# CHECK: r17:16 = add(r21:20,r31:30)
0xb0 0xde 0x74 0xd3
-# CHECK: r17:16 = add(r21:20, r31:30):sat
+# CHECK: r17:16 = add(r21:20,r31:30):sat
0xd0 0xde 0x74 0xd3
-# CHECK: r17:16 = add(r21:20, r31:30):raw:lo
+# CHECK: r17:16 = add(r21:20,r31:30):raw:lo
0xf0 0xde 0x74 0xd3
-# CHECK: r17:16 = add(r21:20, r31:30):raw:hi
+# CHECK: r17:16 = add(r21:20,r31:30):raw:hi
# Add halfword
0x11 0xd5 0x1f 0xd5
-# CHECK: r17 = add(r21.l, r31.l)
+# CHECK: r17 = add(r21.l,r31.l)
0x51 0xd5 0x1f 0xd5
-# CHECK: r17 = add(r21.l, r31.h)
+# CHECK: r17 = add(r21.l,r31.h)
0x91 0xd5 0x1f 0xd5
-# CHECK: r17 = add(r21.l, r31.l):sat
+# CHECK: r17 = add(r21.l,r31.l):sat
0xd1 0xd5 0x1f 0xd5
-# CHECK: r17 = add(r21.l, r31.h):sat
+# CHECK: r17 = add(r21.l,r31.h):sat
0x11 0xd5 0x5f 0xd5
-# CHECK: r17 = add(r21.l, r31.l):<<16
+# CHECK: r17 = add(r21.l,r31.l):<<16
0x31 0xd5 0x5f 0xd5
-# CHECK: r17 = add(r21.l, r31.h):<<16
+# CHECK: r17 = add(r21.l,r31.h):<<16
0x51 0xd5 0x5f 0xd5
-# CHECK: r17 = add(r21.h, r31.l):<<16
+# CHECK: r17 = add(r21.h,r31.l):<<16
0x71 0xd5 0x5f 0xd5
-# CHECK: r17 = add(r21.h, r31.h):<<16
+# CHECK: r17 = add(r21.h,r31.h):<<16
0x91 0xd5 0x5f 0xd5
-# CHECK: r17 = add(r21.l, r31.l):sat:<<16
+# CHECK: r17 = add(r21.l,r31.l):sat:<<16
0xb1 0xd5 0x5f 0xd5
-# CHECK: r17 = add(r21.l, r31.h):sat:<<16
+# CHECK: r17 = add(r21.l,r31.h):sat:<<16
0xd1 0xd5 0x5f 0xd5
-# CHECK: r17 = add(r21.h, r31.l):sat:<<16
+# CHECK: r17 = add(r21.h,r31.l):sat:<<16
0xf1 0xd5 0x5f 0xd5
-# CHECK: r17 = add(r21.h, r31.h):sat:<<16
+# CHECK: r17 = add(r21.h,r31.h):sat:<<16
# Add or subtract doublewords with carry
0x70 0xde 0xd4 0xc2
-# CHECK: r17:16 = add(r21:20, r31:30, p3):carry
+# CHECK: r17:16 = add(r21:20,r31:30,p3):carry
0x70 0xde 0xf4 0xc2
-# CHECK: r17:16 = sub(r21:20, r31:30, p3):carry
+# CHECK: r17:16 = sub(r21:20,r31:30,p3):carry
# Logical doublewords
0x90 0xc0 0x94 0x80
# CHECK: r17:16 = not(r21:20)
0x10 0xde 0xf4 0xd3
-# CHECK: r17:16 = and(r21:20, r31:30)
+# CHECK: r17:16 = and(r21:20,r31:30)
0x30 0xd4 0xfe 0xd3
-# CHECK: r17:16 = and(r21:20, ~r31:30)
+# CHECK: r17:16 = and(r21:20,~r31:30)
0x50 0xde 0xf4 0xd3
-# CHECK: r17:16 = or(r21:20, r31:30)
+# CHECK: r17:16 = or(r21:20,r31:30)
0x70 0xd4 0xfe 0xd3
-# CHECK: r17:16 = or(r21:20, ~r31:30)
+# CHECK: r17:16 = or(r21:20,~r31:30)
0x90 0xde 0xf4 0xd3
-# CHECK: r17:16 = xor(r21:20, r31:30)
+# CHECK: r17:16 = xor(r21:20,r31:30)
# Logical-logical doublewords
0x10 0xde 0x94 0xca
-# CHECK: r17:16 ^= xor(r21:20, r31:30)
+# CHECK: r17:16 ^= xor(r21:20,r31:30)
# Logical-logical words
0xf1 0xc3 0x15 0xda
-# CHECK: r17 |= and(r21, #31)
+# CHECK: r17 |= and(r21,#31)
0xf5 0xc3 0x51 0xda
-# CHECK: r17 = or(r21, and(r17, #31))
+# CHECK: r17 = or(r21,and(r17,#31))
0xf1 0xc3 0x95 0xda
-# CHECK: r17 |= or(r21, #31)
+# CHECK: r17 |= or(r21,#31)
0x11 0xdf 0x35 0xef
-# CHECK: r17 |= and(r21, ~r31)
+# CHECK: r17 |= and(r21,~r31)
0x31 0xdf 0x35 0xef
-# CHECK: r17 &= and(r21, ~r31)
+# CHECK: r17 &= and(r21,~r31)
0x51 0xdf 0x35 0xef
-# CHECK: r17 ^= and(r21, ~r31)
+# CHECK: r17 ^= and(r21,~r31)
0x11 0xdf 0x55 0xef
-# CHECK: r17 &= and(r21, r31)
+# CHECK: r17 &= and(r21,r31)
0x31 0xdf 0x55 0xef
-# CHECK: r17 &= or(r21, r31)
+# CHECK: r17 &= or(r21,r31)
0x51 0xdf 0x55 0xef
-# CHECK: r17 &= xor(r21, r31)
+# CHECK: r17 &= xor(r21,r31)
0x71 0xdf 0x55 0xef
-# CHECK: r17 |= and(r21, r31)
+# CHECK: r17 |= and(r21,r31)
0x71 0xdf 0x95 0xef
-# CHECK: r17 ^= xor(r21, r31)
+# CHECK: r17 ^= xor(r21,r31)
0x11 0xdf 0xd5 0xef
-# CHECK: r17 |= or(r21, r31)
+# CHECK: r17 |= or(r21,r31)
0x31 0xdf 0xd5 0xef
-# CHECK: r17 |= xor(r21, r31)
+# CHECK: r17 |= xor(r21,r31)
0x51 0xdf 0xd5 0xef
-# CHECK: r17 ^= and(r21, r31)
+# CHECK: r17 ^= and(r21,r31)
0x71 0xdf 0xd5 0xef
-# CHECK: r17 ^= or(r21, r31)
+# CHECK: r17 ^= or(r21,r31)
# Maximum words
0x11 0xdf 0xd5 0xd5
-# CHECK: r17 = max(r21, r31)
+# CHECK: r17 = max(r21,r31)
0x91 0xdf 0xd5 0xd5
-# CHECK: r17 = maxu(r21, r31)
+# CHECK: r17 = maxu(r21,r31)
# Maximum doublewords
0x90 0xde 0xd4 0xd3
-# CHECK: r17:16 = max(r21:20, r31:30)
+# CHECK: r17:16 = max(r21:20,r31:30)
0xb0 0xde 0xd4 0xd3
-# CHECK: r17:16 = maxu(r21:20, r31:30)
+# CHECK: r17:16 = maxu(r21:20,r31:30)
# Minimum words
0x11 0xd5 0xbf 0xd5
-# CHECK: r17 = min(r21, r31)
+# CHECK: r17 = min(r21,r31)
0x91 0xd5 0xbf 0xd5
-# CHECK: r17 = minu(r21, r31)
+# CHECK: r17 = minu(r21,r31)
# Minimum doublewords
0xd0 0xd4 0xbe 0xd3
-# CHECK: r17:16 = min(r21:20, r31:30)
+# CHECK: r17:16 = min(r21:20,r31:30)
0xf0 0xd4 0xbe 0xd3
-# CHECK: r17:16 = minu(r21:20, r31:30)
+# CHECK: r17:16 = minu(r21:20,r31:30)
# Module wrap
0xf1 0xdf 0xf5 0xd3
-# CHECK: r17 = modwrap(r21, r31)
+# CHECK: r17 = modwrap(r21,r31)
# Negate
0xb0 0xc0 0x94 0x80
@@ -153,51 +153,51 @@
0x31 0xc0 0xd4 0x88
# CHECK: r17 = round(r21:20):sat
0x11 0xdf 0xf5 0x8c
-# CHECK: r17 = cround(r21, #31)
+# CHECK: r17 = cround(r21,#31)
0x91 0xdf 0xf5 0x8c
-# CHECK: r17 = round(r21, #31)
+# CHECK: r17 = round(r21,#31)
0xd1 0xdf 0xf5 0x8c
-# CHECK: r17 = round(r21, #31):sat
+# CHECK: r17 = round(r21,#31):sat
0x11 0xdf 0xd5 0xc6
-# CHECK: r17 = cround(r21, r31)
+# CHECK: r17 = cround(r21,r31)
0x91 0xdf 0xd5 0xc6
-# CHECK: r17 = round(r21, r31)
+# CHECK: r17 = round(r21,r31)
0xd1 0xdf 0xd5 0xc6
-# CHECK: r17 = round(r21, r31):sat
+# CHECK: r17 = round(r21,r31):sat
# Subtract doublewords
0xf0 0xd4 0x3e 0xd3
-# CHECK: r17:16 = sub(r21:20, r31:30)
+# CHECK: r17:16 = sub(r21:20,r31:30)
# Subtract and accumulate words
0x71 0xd5 0x1f 0xef
-# CHECK: r17 += sub(r21, r31)
+# CHECK: r17 += sub(r21,r31)
# Subtract halfword
0x11 0xd5 0x3f 0xd5
-# CHECK: r17 = sub(r21.l, r31.l)
+# CHECK: r17 = sub(r21.l,r31.l)
0x51 0xd5 0x3f 0xd5
-# CHECK: r17 = sub(r21.l, r31.h)
+# CHECK: r17 = sub(r21.l,r31.h)
0x91 0xd5 0x3f 0xd5
-# CHECK: r17 = sub(r21.l, r31.l):sat
+# CHECK: r17 = sub(r21.l,r31.l):sat
0xd1 0xd5 0x3f 0xd5
-# CHECK: r17 = sub(r21.l, r31.h):sat
+# CHECK: r17 = sub(r21.l,r31.h):sat
0x11 0xd5 0x7f 0xd5
-# CHECK: r17 = sub(r21.l, r31.l):<<16
+# CHECK: r17 = sub(r21.l,r31.l):<<16
0x31 0xd5 0x7f 0xd5
-# CHECK: r17 = sub(r21.l, r31.h):<<16
+# CHECK: r17 = sub(r21.l,r31.h):<<16
0x51 0xd5 0x7f 0xd5
-# CHECK: r17 = sub(r21.h, r31.l):<<16
+# CHECK: r17 = sub(r21.h,r31.l):<<16
0x71 0xd5 0x7f 0xd5
-# CHECK: r17 = sub(r21.h, r31.h):<<16
+# CHECK: r17 = sub(r21.h,r31.h):<<16
0x91 0xd5 0x7f 0xd5
-# CHECK: r17 = sub(r21.l, r31.l):sat:<<16
+# CHECK: r17 = sub(r21.l,r31.l):sat:<<16
0xb1 0xd5 0x7f 0xd5
-# CHECK: r17 = sub(r21.l, r31.h):sat:<<16
+# CHECK: r17 = sub(r21.l,r31.h):sat:<<16
0xd1 0xd5 0x7f 0xd5
-# CHECK: r17 = sub(r21.h, r31.l):sat:<<16
+# CHECK: r17 = sub(r21.h,r31.l):sat:<<16
0xf1 0xd5 0x7f 0xd5
-# CHECK: r17 = sub(r21.h, r31.h):sat:<<16
+# CHECK: r17 = sub(r21.h,r31.h):sat:<<16
# Sign extend word to doubleword
0x10 0xc0 0x55 0x84
@@ -217,179 +217,179 @@
# Vector absolute difference halfwords
0x10 0xd4 0x7e 0xe8
-# CHECK: r17:16 = vabsdiffh(r21:20, r31:30)
+# CHECK: r17:16 = vabsdiffh(r21:20,r31:30)
# Vector absolute difference words
0x10 0xd4 0x3e 0xe8
-# CHECK: r17:16 = vabsdiffw(r21:20, r31:30)
+# CHECK: r17:16 = vabsdiffw(r21:20,r31:30)
# Vector add halfwords
0x50 0xde 0x14 0xd3
-# CHECK: r17:16 = vaddh(r21:20, r31:30)
+# CHECK: r17:16 = vaddh(r21:20,r31:30)
0x70 0xde 0x14 0xd3
-# CHECK: r17:16 = vaddh(r21:20, r31:30):sat
+# CHECK: r17:16 = vaddh(r21:20,r31:30):sat
0x90 0xde 0x14 0xd3
-# CHECK: r17:16 = vadduh(r21:20, r31:30):sat
+# CHECK: r17:16 = vadduh(r21:20,r31:30):sat
# Vector add halfwords with saturate and pack to unsigned bytes
0x31 0xde 0x54 0xc1
-# CHECK: r17 = vaddhub(r21:20, r31:30):sat
+# CHECK: r17 = vaddhub(r21:20,r31:30):sat
# Vector reduce add unsigned bytes
0x30 0xde 0x54 0xe8
-# CHECK: r17:16 = vraddub(r21:20, r31:30)
+# CHECK: r17:16 = vraddub(r21:20,r31:30)
0x30 0xde 0x54 0xea
-# CHECK: r17:16 += vraddub(r21:20, r31:30)
+# CHECK: r17:16 += vraddub(r21:20,r31:30)
# Vector reduce add halfwords
0x31 0xde 0x14 0xe9
-# CHECK: r17 = vradduh(r21:20, r31:30)
+# CHECK: r17 = vradduh(r21:20,r31:30)
0xf1 0xde 0x34 0xe9
-# CHECK: r17 = vraddh(r21:20, r31:30)
+# CHECK: r17 = vraddh(r21:20,r31:30)
# Vector add bytes
0x10 0xde 0x14 0xd3
-# CHECK: r17:16 = vaddub(r21:20, r31:30)
+# CHECK: r17:16 = vaddub(r21:20,r31:30)
0x30 0xde 0x14 0xd3
-# CHECK: r17:16 = vaddub(r21:20, r31:30):sat
+# CHECK: r17:16 = vaddub(r21:20,r31:30):sat
# Vector add words
0xb0 0xde 0x14 0xd3
-# CHECK: r17:16 = vaddw(r21:20, r31:30)
+# CHECK: r17:16 = vaddw(r21:20,r31:30)
0xd0 0xde 0x14 0xd3
-# CHECK: r17:16 = vaddw(r21:20, r31:30):sat
+# CHECK: r17:16 = vaddw(r21:20,r31:30):sat
# Vector average halfwords
0x50 0xde 0x54 0xd3
-# CHECK: r17:16 = vavgh(r21:20, r31:30)
+# CHECK: r17:16 = vavgh(r21:20,r31:30)
0x70 0xde 0x54 0xd3
-# CHECK: r17:16 = vavgh(r21:20, r31:30):rnd
+# CHECK: r17:16 = vavgh(r21:20,r31:30):rnd
0x90 0xde 0x54 0xd3
-# CHECK: r17:16 = vavgh(r21:20, r31:30):crnd
+# CHECK: r17:16 = vavgh(r21:20,r31:30):crnd
0xb0 0xde 0x54 0xd3
-# CHECK: r17:16 = vavguh(r21:20, r31:30)
+# CHECK: r17:16 = vavguh(r21:20,r31:30)
0xd0 0xde 0x54 0xd3
-# CHECK: r17:16 = vavguh(r21:20, r31:30):rnd
+# CHECK: r17:16 = vavguh(r21:20,r31:30):rnd
0x10 0xd4 0x9e 0xd3
-# CHECK: r17:16 = vnavgh(r21:20, r31:30)
+# CHECK: r17:16 = vnavgh(r21:20,r31:30)
0x30 0xd4 0x9e 0xd3
-# CHECK: r17:16 = vnavgh(r21:20, r31:30):rnd:sat
+# CHECK: r17:16 = vnavgh(r21:20,r31:30):rnd:sat
0x50 0xd4 0x9e 0xd3
-# CHECK: r17:16 = vnavgh(r21:20, r31:30):crnd:sat
+# CHECK: r17:16 = vnavgh(r21:20,r31:30):crnd:sat
# Vector average unsigned bytes
0x10 0xde 0x54 0xd3
-# CHECK: r17:16 = vavgub(r21:20, r31:30)
+# CHECK: r17:16 = vavgub(r21:20,r31:30)
0x30 0xde 0x54 0xd3
-# CHECK: r17:16 = vavgub(r21:20, r31:30):rnd
+# CHECK: r17:16 = vavgub(r21:20,r31:30):rnd
# Vector average words
0x10 0xde 0x74 0xd3
-# CHECK: r17:16 = vavgw(r21:20, r31:30)
+# CHECK: r17:16 = vavgw(r21:20,r31:30)
0x30 0xde 0x74 0xd3
-# CHECK: r17:16 = vavgw(r21:20, r31:30):rnd
+# CHECK: r17:16 = vavgw(r21:20,r31:30):rnd
0x50 0xde 0x74 0xd3
-# CHECK: r17:16 = vavgw(r21:20, r31:30):crnd
+# CHECK: r17:16 = vavgw(r21:20,r31:30):crnd
0x70 0xde 0x74 0xd3
-# CHECK: r17:16 = vavguw(r21:20, r31:30)
+# CHECK: r17:16 = vavguw(r21:20,r31:30)
0x90 0xde 0x74 0xd3
-# CHECK: r17:16 = vavguw(r21:20, r31:30):rnd
+# CHECK: r17:16 = vavguw(r21:20,r31:30):rnd
0x70 0xd4 0x9e 0xd3
-# CHECK: r17:16 = vnavgw(r21:20, r31:30)
+# CHECK: r17:16 = vnavgw(r21:20,r31:30)
0x90 0xd4 0x9e 0xd3
-# CHECK: r17:16 = vnavgw(r21:20, r31:30):rnd:sat
+# CHECK: r17:16 = vnavgw(r21:20,r31:30):rnd:sat
0xd0 0xd4 0x9e 0xd3
-# CHECK: r17:16 = vnavgw(r21:20, r31:30):crnd:sat
+# CHECK: r17:16 = vnavgw(r21:20,r31:30):crnd:sat
# Vector conditional negate
0x50 0xdf 0xd4 0xc3
-# CHECK: r17:16 = vcnegh(r21:20, r31)
+# CHECK: r17:16 = vcnegh(r21:20,r31)
0xf0 0xff 0x34 0xcb
-# CHECK: r17:16 += vrcnegh(r21:20, r31)
+# CHECK: r17:16 += vrcnegh(r21:20,r31)
# Vector maximum bytes
0x10 0xd4 0xde 0xd3
-# CHECK: r17:16 = vmaxub(r21:20, r31:30)
+# CHECK: r17:16 = vmaxub(r21:20,r31:30)
0xd0 0xd4 0xde 0xd3
-# CHECK: r17:16 = vmaxb(r21:20, r31:30)
+# CHECK: r17:16 = vmaxb(r21:20,r31:30)
# Vector maximum halfwords
0x30 0xd4 0xde 0xd3
-# CHECK: r17:16 = vmaxh(r21:20, r31:30)
+# CHECK: r17:16 = vmaxh(r21:20,r31:30)
0x50 0xd4 0xde 0xd3
-# CHECK: r17:16 = vmaxuh(r21:20, r31:30)
+# CHECK: r17:16 = vmaxuh(r21:20,r31:30)
# Vector reduce maximum halfwords
0x3f 0xd0 0x34 0xcb
-# CHECK: r17:16 = vrmaxh(r21:20, r31)
+# CHECK: r17:16 = vrmaxh(r21:20,r31)
0x3f 0xf0 0x34 0xcb
-# CHECK: r17:16 = vrmaxuh(r21:20, r31)
+# CHECK: r17:16 = vrmaxuh(r21:20,r31)
# Vector reduce maximum words
0x5f 0xd0 0x34 0xcb
-# CHECK: r17:16 = vrmaxw(r21:20, r31)
+# CHECK: r17:16 = vrmaxw(r21:20,r31)
0x5f 0xf0 0x34 0xcb
-# CHECK: r17:16 = vrmaxuw(r21:20, r31)
+# CHECK: r17:16 = vrmaxuw(r21:20,r31)
# Vector maximum words
0xb0 0xd4 0xbe 0xd3
-# CHECK: r17:16 = vmaxuw(r21:20, r31:30)
+# CHECK: r17:16 = vmaxuw(r21:20,r31:30)
0x70 0xd4 0xde 0xd3
-# CHECK: r17:16 = vmaxw(r21:20, r31:30)
+# CHECK: r17:16 = vmaxw(r21:20,r31:30)
# Vector minimum bytes
0x10 0xd4 0xbe 0xd3
-# CHECK: r17:16 = vminub(r21:20, r31:30)
+# CHECK: r17:16 = vminub(r21:20,r31:30)
0xf0 0xd4 0xde 0xd3
-# CHECK: r17:16 = vminb(r21:20, r31:30)
+# CHECK: r17:16 = vminb(r21:20,r31:30)
# Vector minimum halfwords
0x30 0xd4 0xbe 0xd3
-# CHECK: r17:16 = vminh(r21:20, r31:30)
+# CHECK: r17:16 = vminh(r21:20,r31:30)
0x50 0xd4 0xbe 0xd3
-# CHECK: r17:16 = vminuh(r21:20, r31:30)
+# CHECK: r17:16 = vminuh(r21:20,r31:30)
# Vector reduce minimum halfwords
0xbf 0xd0 0x34 0xcb
-# CHECK: r17:16 = vrminh(r21:20, r31)
+# CHECK: r17:16 = vrminh(r21:20,r31)
0xbf 0xf0 0x34 0xcb
-# CHECK: r17:16 = vrminuh(r21:20, r31)
+# CHECK: r17:16 = vrminuh(r21:20,r31)
# Vector reduce minimum words
0xdf 0xd0 0x34 0xcb
-# CHECK: r17:16 = vrminw(r21:20, r31)
+# CHECK: r17:16 = vrminw(r21:20,r31)
0xdf 0xf0 0x34 0xcb
-# CHECK: r17:16 = vrminuw(r21:20, r31)
+# CHECK: r17:16 = vrminuw(r21:20,r31)
# Vector minimum words
0x70 0xd4 0xbe 0xd3
-# CHECK: r17:16 = vminw(r21:20, r31:30)
+# CHECK: r17:16 = vminw(r21:20,r31:30)
0x90 0xd4 0xbe 0xd3
-# CHECK: r17:16 = vminuw(r21:20, r31:30)
+# CHECK: r17:16 = vminuw(r21:20,r31:30)
# Vector sum of absolute differences unsigned bytes
0x50 0xde 0x54 0xe8
-# CHECK: r17:16 = vrsadub(r21:20, r31:30)
+# CHECK: r17:16 = vrsadub(r21:20,r31:30)
0x50 0xde 0x54 0xea
-# CHECK: r17:16 += vrsadub(r21:20, r31:30)
+# CHECK: r17:16 += vrsadub(r21:20,r31:30)
# Vector subtract halfwords
0x50 0xd4 0x3e 0xd3
-# CHECK: r17:16 = vsubh(r21:20, r31:30)
+# CHECK: r17:16 = vsubh(r21:20,r31:30)
0x70 0xd4 0x3e 0xd3
-# CHECK: r17:16 = vsubh(r21:20, r31:30):sat
+# CHECK: r17:16 = vsubh(r21:20,r31:30):sat
0x90 0xd4 0x3e 0xd3
-# CHECK: r17:16 = vsubuh(r21:20, r31:30):sat
+# CHECK: r17:16 = vsubuh(r21:20,r31:30):sat
# Vector subtract bytes
0x10 0xd4 0x3e 0xd3
-# CHECK: r17:16 = vsubub(r21:20, r31:30)
+# CHECK: r17:16 = vsubub(r21:20,r31:30)
0x30 0xd4 0x3e 0xd3
-# CHECK: r17:16 = vsubub(r21:20, r31:30):sat
+# CHECK: r17:16 = vsubub(r21:20,r31:30):sat
# Vector subtract words
0xb0 0xd4 0x3e 0xd3
-# CHECK: r17:16 = vsubw(r21:20, r31:30)
+# CHECK: r17:16 = vsubw(r21:20,r31:30)
0xd0 0xd4 0x3e 0xd3
-# CHECK: r17:16 = vsubw(r21:20, r31:30):sat
+# CHECK: r17:16 = vsubw(r21:20,r31:30):sat
Modified: llvm/trunk/test/MC/Disassembler/Hexagon/xtype_bit.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/xtype_bit.txt?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Hexagon/xtype_bit.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Hexagon/xtype_bit.txt Fri Feb 10 09:33:13 2017
@@ -11,9 +11,9 @@
0x11 0xc0 0x74 0x88
# CHECK: r17 = normamt(r21:20)
0x51 0xd7 0x74 0x88
-# CHECK: r17 = add(clb(r21:20), #23)
+# CHECK: r17 = add(clb(r21:20),#23)
0x11 0xd7 0x35 0x8c
-# CHECK: r17 = add(clb(r21), #23)
+# CHECK: r17 = add(clb(r21),#23)
0x91 0xc0 0x15 0x8c
# CHECK: r17 = clb(r21)
0xb1 0xc0 0x15 0x8c
@@ -39,31 +39,31 @@
# Extract bitfield
0xf0 0xdf 0x54 0x81
-# CHECK: r17:16 = extractu(r21:20, #31, #23)
+# CHECK: r17:16 = extractu(r21:20,#31,#23)
0xf0 0xdf 0x54 0x8a
-# CHECK: r17:16 = extract(r21:20, #31, #23)
+# CHECK: r17:16 = extract(r21:20,#31,#23)
0xf1 0xdf 0x55 0x8d
-# CHECK: r17 = extractu(r21, #31, #23)
+# CHECK: r17 = extractu(r21,#31,#23)
0xf1 0xdf 0xd5 0x8d
-# CHECK: r17 = extract(r21, #31, #23)
+# CHECK: r17 = extract(r21,#31,#23)
0x10 0xde 0x14 0xc1
-# CHECK: r17:16 = extractu(r21:20, r31:30)
+# CHECK: r17:16 = extractu(r21:20,r31:30)
0x90 0xde 0xd4 0xc1
-# CHECK: r17:16 = extract(r21:20, r31:30)
+# CHECK: r17:16 = extract(r21:20,r31:30)
0x11 0xde 0x15 0xc9
-# CHECK: r17 = extractu(r21, r31:30)
+# CHECK: r17 = extractu(r21,r31:30)
0x51 0xde 0x15 0xc9
-# CHECK: r17 = extract(r21, r31:30)
+# CHECK: r17 = extract(r21,r31:30)
# Insert bitfield
0xf0 0xdf 0x54 0x83
-# CHECK: r17:16 = insert(r21:20, #31, #23)
+# CHECK: r17:16 = insert(r21:20,#31,#23)
0xf1 0xdf 0x55 0x8f
-# CHECK: r17 = insert(r21, #31, #23)
+# CHECK: r17 = insert(r21,#31,#23)
0x11 0xde 0x15 0xc8
-# CHECK: r17 = insert(r21, r31:30)
+# CHECK: r17 = insert(r21,r31:30)
0x10 0xde 0x14 0xca
-# CHECK: r17:16 = insert(r21:20, r31:30)
+# CHECK: r17:16 = insert(r21:20,r31:30)
# Interleave/deinterleave
0x90 0xc0 0xd4 0x80
@@ -73,13 +73,13 @@
# Linear feedback-shift iteration
0xd0 0xde 0x94 0xc1
-# CHECK: r17:16 = lfs(r21:20, r31:30)
+# CHECK: r17:16 = lfs(r21:20,r31:30)
# Masked parity
0x11 0xde 0x14 0xd0
-# CHECK: r17 = parity(r21:20, r31:30)
+# CHECK: r17 = parity(r21:20,r31:30)
0x11 0xdf 0xf5 0xd5
-# CHECK: r17 = parity(r21, r31)
+# CHECK: r17 = parity(r21,r31)
# Bit reverse
0xd0 0xc0 0xd4 0x80
@@ -89,30 +89,30 @@
# Set/clear/toggle bit
0x11 0xdf 0xd5 0x8c
-# CHECK: r17 = setbit(r21, #31)
+# CHECK: r17 = setbit(r21,#31)
0x31 0xdf 0xd5 0x8c
-# CHECK: r17 = clrbit(r21, #31)
+# CHECK: r17 = clrbit(r21,#31)
0x51 0xdf 0xd5 0x8c
-# CHECK: r17 = togglebit(r21, #31)
+# CHECK: r17 = togglebit(r21,#31)
0x11 0xdf 0x95 0xc6
-# CHECK: r17 = setbit(r21, r31)
+# CHECK: r17 = setbit(r21,r31)
0x51 0xdf 0x95 0xc6
-# CHECK: r17 = clrbit(r21, r31)
+# CHECK: r17 = clrbit(r21,r31)
0x91 0xdf 0x95 0xc6
-# CHECK: r17 = togglebit(r21, r31)
+# CHECK: r17 = togglebit(r21,r31)
# Split bitfield
0x90 0xdf 0xd5 0x88
-# CHECK: r17:16 = bitsplit(r21, #31)
+# CHECK: r17:16 = bitsplit(r21,#31)
0x10 0xdf 0x35 0xd4
-# CHECK: r17:16 = bitsplit(r21, r31)
+# CHECK: r17:16 = bitsplit(r21,r31)
# Table index
0xf1 0xcd 0x15 0x87
-# CHECK: r17 = tableidxb(r21, #7, #13):raw
+# CHECK: r17 = tableidxb(r21,#7,#13):raw
0xf1 0xcd 0x55 0x87
-# CHECK: r17 = tableidxh(r21, #7, #13):raw
+# CHECK: r17 = tableidxh(r21,#7,#13):raw
0xf1 0xcd 0x95 0x87
-# CHECK: r17 = tableidxw(r21, #7, #13):raw
+# CHECK: r17 = tableidxw(r21,#7,#13):raw
0xf1 0xcd 0xd5 0x87
-# CHECK: r17 = tableidxd(r21, #7, #13):raw
+# CHECK: r17 = tableidxd(r21,#7,#13):raw
Modified: llvm/trunk/test/MC/Disassembler/Hexagon/xtype_complex.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/xtype_complex.txt?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Hexagon/xtype_complex.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Hexagon/xtype_complex.txt Fri Feb 10 09:33:13 2017
@@ -3,89 +3,89 @@
# Complex add/sub halfwords
0x90 0xde 0x54 0xc1
-# CHECK: r17:16 = vxaddsubh(r21:20, r31:30):sat
+# CHECK: r17:16 = vxaddsubh(r21:20,r31:30):sat
0xd0 0xde 0x54 0xc1
-# CHECK: r17:16 = vxsubaddh(r21:20, r31:30):sat
+# CHECK: r17:16 = vxsubaddh(r21:20,r31:30):sat
0x10 0xde 0xd4 0xc1
-# CHECK: r17:16 = vxaddsubh(r21:20, r31:30):rnd:>>1:sat
+# CHECK: r17:16 = vxaddsubh(r21:20,r31:30):rnd:>>1:sat
0x50 0xde 0xd4 0xc1
-# CHECK: r17:16 = vxsubaddh(r21:20, r31:30):rnd:>>1:sat
+# CHECK: r17:16 = vxsubaddh(r21:20,r31:30):rnd:>>1:sat
# Complex add/sub words
0x10 0xde 0x54 0xc1
-# CHECK: r17:16 = vxaddsubw(r21:20, r31:30):sat
+# CHECK: r17:16 = vxaddsubw(r21:20,r31:30):sat
0x50 0xde 0x54 0xc1
-# CHECK: r17:16 = vxsubaddw(r21:20, r31:30):sat
+# CHECK: r17:16 = vxsubaddw(r21:20,r31:30):sat
# Complex multiply
0xd0 0xdf 0x15 0xe5
-# CHECK: r17:16 = cmpy(r21, r31):sat
+# CHECK: r17:16 = cmpy(r21,r31):sat
0xd0 0xdf 0x95 0xe5
-# CHECK: r17:16 = cmpy(r21, r31):<<1:sat
+# CHECK: r17:16 = cmpy(r21,r31):<<1:sat
0xd0 0xdf 0x55 0xe5
-# CHECK: r17:16 = cmpy(r21, r31*):sat
+# CHECK: r17:16 = cmpy(r21,r31*):sat
0xd0 0xdf 0xd5 0xe5
-# CHECK: r17:16 = cmpy(r21, r31*):<<1:sat
+# CHECK: r17:16 = cmpy(r21,r31*):<<1:sat
0xd0 0xdf 0x15 0xe7
-# CHECK: r17:16 += cmpy(r21, r31):sat
+# CHECK: r17:16 += cmpy(r21,r31):sat
0xd0 0xdf 0x95 0xe7
-# CHECK: r17:16 += cmpy(r21, r31):<<1:sat
+# CHECK: r17:16 += cmpy(r21,r31):<<1:sat
0xf0 0xdf 0x15 0xe7
-# CHECK: r17:16 -= cmpy(r21, r31):sat
+# CHECK: r17:16 -= cmpy(r21,r31):sat
0xf0 0xdf 0x95 0xe7
-# CHECK: r17:16 -= cmpy(r21, r31):<<1:sat
+# CHECK: r17:16 -= cmpy(r21,r31):<<1:sat
0xd0 0xdf 0x55 0xe7
-# CHECK: r17:16 += cmpy(r21, r31*):sat
+# CHECK: r17:16 += cmpy(r21,r31*):sat
0xd0 0xdf 0xd5 0xe7
-# CHECK: r17:16 += cmpy(r21, r31*):<<1:sat
+# CHECK: r17:16 += cmpy(r21,r31*):<<1:sat
0xf0 0xdf 0x55 0xe7
-# CHECK: r17:16 -= cmpy(r21, r31*):sat
+# CHECK: r17:16 -= cmpy(r21,r31*):sat
0xf0 0xdf 0xd5 0xe7
-# CHECK: r17:16 -= cmpy(r21, r31*):<<1:sat
+# CHECK: r17:16 -= cmpy(r21,r31*):<<1:sat
# Complex multiply real or imaginary
0x30 0xdf 0x15 0xe5
-# CHECK: r17:16 = cmpyi(r21, r31)
+# CHECK: r17:16 = cmpyi(r21,r31)
0x50 0xdf 0x15 0xe5
-# CHECK: r17:16 = cmpyr(r21, r31)
+# CHECK: r17:16 = cmpyr(r21,r31)
0x30 0xdf 0x15 0xe7
-# CHECK: r17:16 += cmpyi(r21, r31)
+# CHECK: r17:16 += cmpyi(r21,r31)
0x50 0xdf 0x15 0xe7
-# CHECK: r17:16 += cmpyr(r21, r31)
+# CHECK: r17:16 += cmpyr(r21,r31)
# Complex multiply with round and pack
0xd1 0xdf 0x35 0xed
-# CHECK: r17 = cmpy(r21, r31):rnd:sat
+# CHECK: r17 = cmpy(r21,r31):rnd:sat
0xd1 0xdf 0xb5 0xed
-# CHECK: r17 = cmpy(r21, r31):<<1:rnd:sat
+# CHECK: r17 = cmpy(r21,r31):<<1:rnd:sat
0xd1 0xdf 0x75 0xed
-# CHECK: r17 = cmpy(r21, r31*):rnd:sat
+# CHECK: r17 = cmpy(r21,r31*):rnd:sat
0xd1 0xdf 0xf5 0xed
-# CHECK: r17 = cmpy(r21, r31*):<<1:rnd:sat
+# CHECK: r17 = cmpy(r21,r31*):<<1:rnd:sat
# Complex multiply 32x16
0x91 0xdf 0x14 0xc5
-# CHECK: r17 = cmpyiwh(r21:20, r31):<<1:rnd:sat
+# CHECK: r17 = cmpyiwh(r21:20,r31):<<1:rnd:sat
0xb1 0xdf 0x14 0xc5
-# CHECK: r17 = cmpyiwh(r21:20, r31*):<<1:rnd:sat
+# CHECK: r17 = cmpyiwh(r21:20,r31*):<<1:rnd:sat
0xd1 0xdf 0x14 0xc5
-# CHECK: r17 = cmpyrwh(r21:20, r31):<<1:rnd:sat
+# CHECK: r17 = cmpyrwh(r21:20,r31):<<1:rnd:sat
0xf1 0xdf 0x14 0xc5
-# CHECK: r17 = cmpyrwh(r21:20, r31*):<<1:rnd:sat
+# CHECK: r17 = cmpyrwh(r21:20,r31*):<<1:rnd:sat
# Vector complex multiply real or imaginary
0xd0 0xde 0x34 0xe8
-# CHECK: r17:16 = vcmpyr(r21:20, r31:30):sat
+# CHECK: r17:16 = vcmpyr(r21:20,r31:30):sat
0xd0 0xde 0xb4 0xe8
-# CHECK: r17:16 = vcmpyr(r21:20, r31:30):<<1:sat
+# CHECK: r17:16 = vcmpyr(r21:20,r31:30):<<1:sat
0xd0 0xde 0x54 0xe8
-# CHECK: r17:16 = vcmpyi(r21:20, r31:30):sat
+# CHECK: r17:16 = vcmpyi(r21:20,r31:30):sat
0xd0 0xde 0xd4 0xe8
-# CHECK: r17:16 = vcmpyi(r21:20, r31:30):<<1:sat
+# CHECK: r17:16 = vcmpyi(r21:20,r31:30):<<1:sat
0x90 0xde 0x34 0xea
-# CHECK: r17:16 += vcmpyr(r21:20, r31:30):sat
+# CHECK: r17:16 += vcmpyr(r21:20,r31:30):sat
0x90 0xde 0x54 0xea
-# CHECK: r17:16 += vcmpyi(r21:20, r31:30):sat
+# CHECK: r17:16 += vcmpyi(r21:20,r31:30):sat
# Vector complex conjugate
0xf0 0xc0 0x94 0x80
@@ -93,36 +93,36 @@
# Vector complex rotate
0x10 0xdf 0xd4 0xc3
-# CHECK: r17:16 = vcrotate(r21:20, r31)
+# CHECK: r17:16 = vcrotate(r21:20,r31)
# Vector reduce complex multiply real or imaginary
0x10 0xde 0x14 0xe8
-# CHECK: r17:16 = vrcmpyi(r21:20, r31:30)
+# CHECK: r17:16 = vrcmpyi(r21:20,r31:30)
0x30 0xde 0x14 0xe8
-# CHECK: r17:16 = vrcmpyr(r21:20, r31:30)
+# CHECK: r17:16 = vrcmpyr(r21:20,r31:30)
0x10 0xde 0x54 0xe8
-# CHECK: r17:16 = vrcmpyi(r21:20, r31:30*)
+# CHECK: r17:16 = vrcmpyi(r21:20,r31:30*)
0x30 0xde 0x74 0xe8
-# CHECK: r17:16 = vrcmpyr(r21:20, r31:30*)
+# CHECK: r17:16 = vrcmpyr(r21:20,r31:30*)
# Vector reduce complex multiply by scalar
0x90 0xde 0xb4 0xe8
-# CHECK: r17:16 = vrcmpys(r21:20, r31:30):<<1:sat:raw:hi
+# CHECK: r17:16 = vrcmpys(r21:20,r31:30):<<1:sat:raw:hi
0x90 0xde 0xf4 0xe8
-# CHECK: r17:16 = vrcmpys(r21:20, r31:30):<<1:sat:raw:lo
+# CHECK: r17:16 = vrcmpys(r21:20,r31:30):<<1:sat:raw:lo
0x90 0xde 0xb4 0xea
-# CHECK: r17:16 += vrcmpys(r21:20, r31:30):<<1:sat:raw:hi
+# CHECK: r17:16 += vrcmpys(r21:20,r31:30):<<1:sat:raw:hi
0x90 0xde 0xf4 0xea
-# CHECK: r17:16 += vrcmpys(r21:20, r31:30):<<1:sat:raw:lo
+# CHECK: r17:16 += vrcmpys(r21:20,r31:30):<<1:sat:raw:lo
# Vector reduce complex multiply by scalar with round and pack
0xd1 0xde 0xb4 0xe9
-# CHECK: r17 = vrcmpys(r21:20, r31:30):<<1:rnd:sat:raw:hi
+# CHECK: r17 = vrcmpys(r21:20,r31:30):<<1:rnd:sat:raw:hi
0xf1 0xde 0xb4 0xe9
-# CHECK: r17 = vrcmpys(r21:20, r31:30):<<1:rnd:sat:raw:lo
+# CHECK: r17 = vrcmpys(r21:20,r31:30):<<1:rnd:sat:raw:lo
# Vector reduce complex rotate
0xf0 0xff 0xd4 0xc3
-# CHECK: r17:16 = vrcrotate(r21:20, r31, #3)
+# CHECK: r17:16 = vrcrotate(r21:20,r31,#3)
0x30 0xff 0xb4 0xcb
-# CHECK: r17:16 += vrcrotate(r21:20, r31, #3)
+# CHECK: r17:16 += vrcrotate(r21:20,r31,#3)
Modified: llvm/trunk/test/MC/Disassembler/Hexagon/xtype_fp.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/xtype_fp.txt?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Hexagon/xtype_fp.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Hexagon/xtype_fp.txt Fri Feb 10 09:33:13 2017
@@ -3,31 +3,31 @@
# Floating point addition
0x11 0xdf 0x15 0xeb
-# CHECK: r17 = sfadd(r21, r31)
+# CHECK: r17 = sfadd(r21,r31)
# Classify floating-point value
0x03 0xd5 0xf1 0x85
-# CHECK: p3 = sfclass(r17, #21)
+# CHECK: p3 = sfclass(r17,#21)
0xb3 0xc2 0x90 0xdc
-# CHECK: p3 = dfclass(r17:16, #21)
+# CHECK: p3 = dfclass(r17:16,#21)
# Compare floating-point value
0x03 0xd5 0xf1 0xc7
-# CHECK: p3 = sfcmp.ge(r17, r21)
+# CHECK: p3 = sfcmp.ge(r17,r21)
0x23 0xd5 0xf1 0xc7
-# CHECK: p3 = sfcmp.uo(r17, r21)
+# CHECK: p3 = sfcmp.uo(r17,r21)
0x63 0xd5 0xf1 0xc7
-# CHECK: p3 = sfcmp.eq(r17, r21)
+# CHECK: p3 = sfcmp.eq(r17,r21)
0x83 0xd5 0xf1 0xc7
-# CHECK: p3 = sfcmp.gt(r17, r21)
+# CHECK: p3 = sfcmp.gt(r17,r21)
0x03 0xd4 0xf0 0xd2
-# CHECK: p3 = dfcmp.eq(r17:16, r21:20)
+# CHECK: p3 = dfcmp.eq(r17:16,r21:20)
0x23 0xd4 0xf0 0xd2
-# CHECK: p3 = dfcmp.gt(r17:16, r21:20)
+# CHECK: p3 = dfcmp.gt(r17:16,r21:20)
0x43 0xd4 0xf0 0xd2
-# CHECK: p3 = dfcmp.ge(r17:16, r21:20)
+# CHECK: p3 = dfcmp.ge(r17:16,r21:20)
0x63 0xd4 0xf0 0xd2
-# CHECK: p3 = dfcmp.uo(r17:16, r21:20)
+# CHECK: p3 = dfcmp.uo(r17:16,r21:20)
# Convert floating-point value to other format
0x10 0xc0 0x95 0x84
@@ -91,29 +91,29 @@
0x11 0xc0 0xb5 0x8b
# CHECK: r17 = sffixupr(r21)
0x11 0xdf 0xd5 0xeb
-# CHECK: r17 = sffixupn(r21, r31)
+# CHECK: r17 = sffixupn(r21,r31)
0x31 0xdf 0xd5 0xeb
-# CHECK: r17 = sffixupd(r21, r31)
+# CHECK: r17 = sffixupd(r21,r31)
# Floating point fused multiply-add
0x91 0xdf 0x15 0xef
-# CHECK: r17 += sfmpy(r21, r31)
+# CHECK: r17 += sfmpy(r21,r31)
0xb1 0xdf 0x15 0xef
-# CHECK: r17 -= sfmpy(r21, r31)
+# CHECK: r17 -= sfmpy(r21,r31)
# Floating point fused multiply-add with scaling
0xf1 0xdf 0x75 0xef
-# CHECK: r17 += sfmpy(r21, r31, p3):scale
+# CHECK: r17 += sfmpy(r21,r31,p3):scale
# Floating point reciprocal square root approximation
0x71 0xc0 0xf5 0x8b
-# CHECK: r17, p3 = sfinvsqrta(r21)
+# CHECK: r17,p3 = sfinvsqrta(r21)
# Floating point fused multiply-add for library routines
0xd1 0xdf 0x15 0xef
-# CHECK: r17 += sfmpy(r21, r31):lib
+# CHECK: r17 += sfmpy(r21,r31):lib
0xf1 0xdf 0x15 0xef
-# CHECK: r17 -= sfmpy(r21, r31):lib
+# CHECK: r17 -= sfmpy(r21,r31):lib
# Create floating-point constant
0xb1 0xc2 0x00 0xd6
@@ -127,20 +127,20 @@
# Floating point maximum
0x11 0xdf 0x95 0xeb
-# CHECK: r17 = sfmax(r21, r31)
+# CHECK: r17 = sfmax(r21,r31)
# Floating point minimum
0x31 0xdf 0x95 0xeb
-# CHECK: r17 = sfmin(r21, r31)
+# CHECK: r17 = sfmin(r21,r31)
# Floating point multiply
0x11 0xdf 0x55 0xeb
-# CHECK: r17 = sfmpy(r21, r31)
+# CHECK: r17 = sfmpy(r21,r31)
# Floating point reciprocal approximation
0xf1 0xdf 0xf5 0xeb
-# CHECK: r17, p3 = sfrecipa(r21, r31)
+# CHECK: r17,p3 = sfrecipa(r21,r31)
# Floating point subtraction
0x31 0xdf 0x15 0xeb
-# CHECK: r17 = sfsub(r21, r31)
+# CHECK: r17 = sfsub(r21,r31)
Modified: llvm/trunk/test/MC/Disassembler/Hexagon/xtype_mpy.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/xtype_mpy.txt?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Hexagon/xtype_mpy.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Hexagon/xtype_mpy.txt Fri Feb 10 09:33:13 2017
@@ -3,398 +3,398 @@
# Multiply and use lower result
0xb1 0xdf 0x35 0xd7
-# CHECK: r17 = add(#21, mpyi(r21, r31))
+# CHECK: r17 = add(#21,mpyi(r21,r31))
0xbf 0xd1 0x35 0xd8
-# CHECK: r17 = add(#21, mpyi(r21, #31))
+# CHECK: r17 = add(#21,mpyi(r21,#31))
0xb5 0xd1 0x3f 0xdf
-# CHECK: r17 = add(r21, mpyi(#84, r31))
+# CHECK: r17 = add(r21,mpyi(#84,r31))
0xf5 0xf1 0xb5 0xdf
-# CHECK: r17 = add(r21, mpyi(r21, #31))
+# CHECK: r17 = add(r21,mpyi(r21,#31))
0x15 0xd1 0x1f 0xe3
-# CHECK: r17 = add(r21, mpyi(r17, r31))
+# CHECK: r17 = add(r21,mpyi(r17,r31))
0xf1 0xc3 0x15 0xe0
-# CHECK: r17 =+ mpyi(r21, #31)
+# CHECK: r17 = +mpyi(r21,#31)
0xf1 0xc3 0x95 0xe0
-# CHECK: r17 =- mpyi(r21, #31)
+# CHECK: r17 = -mpyi(r21,#31)
0xf1 0xc3 0x15 0xe1
-# CHECK: r17 += mpyi(r21, #31)
+# CHECK: r17 += mpyi(r21,#31)
0xf1 0xc3 0x95 0xe1
-# CHECK: r17 -= mpyi(r21, #31)
+# CHECK: r17 -= mpyi(r21,#31)
0x11 0xdf 0x15 0xed
-# CHECK: r17 = mpyi(r21, r31)
+# CHECK: r17 = mpyi(r21,r31)
0x11 0xdf 0x15 0xef
-# CHECK: r17 += mpyi(r21, r31)
+# CHECK: r17 += mpyi(r21,r31)
# Vector multiply word by signed half (32x16)
0xb0 0xde 0x14 0xe8
-# CHECK: r17:16 = vmpyweh(r21:20, r31:30):sat
+# CHECK: r17:16 = vmpyweh(r21:20,r31:30):sat
0xb0 0xde 0x94 0xe8
-# CHECK: r17:16 = vmpyweh(r21:20, r31:30):<<1:sat
+# CHECK: r17:16 = vmpyweh(r21:20,r31:30):<<1:sat
0xf0 0xde 0x14 0xe8
-# CHECK: r17:16 = vmpywoh(r21:20, r31:30):sat
+# CHECK: r17:16 = vmpywoh(r21:20,r31:30):sat
0xf0 0xde 0x94 0xe8
-# CHECK: r17:16 = vmpywoh(r21:20, r31:30):<<1:sat
+# CHECK: r17:16 = vmpywoh(r21:20,r31:30):<<1:sat
0xb0 0xde 0x34 0xe8
-# CHECK: r17:16 = vmpyweh(r21:20, r31:30):rnd:sat
+# CHECK: r17:16 = vmpyweh(r21:20,r31:30):rnd:sat
0xb0 0xde 0xb4 0xe8
-# CHECK: r17:16 = vmpyweh(r21:20, r31:30):<<1:rnd:sat
+# CHECK: r17:16 = vmpyweh(r21:20,r31:30):<<1:rnd:sat
0xf0 0xde 0x34 0xe8
-# CHECK: r17:16 = vmpywoh(r21:20, r31:30):rnd:sat
+# CHECK: r17:16 = vmpywoh(r21:20,r31:30):rnd:sat
0xf0 0xde 0xb4 0xe8
-# CHECK: r17:16 = vmpywoh(r21:20, r31:30):<<1:rnd:sat
+# CHECK: r17:16 = vmpywoh(r21:20,r31:30):<<1:rnd:sat
0xb0 0xde 0x14 0xea
-# CHECK: r17:16 += vmpyweh(r21:20, r31:30):sat
+# CHECK: r17:16 += vmpyweh(r21:20,r31:30):sat
0xb0 0xde 0x94 0xea
-# CHECK: r17:16 += vmpyweh(r21:20, r31:30):<<1:sat
+# CHECK: r17:16 += vmpyweh(r21:20,r31:30):<<1:sat
0xf0 0xde 0x14 0xea
-# CHECK: r17:16 += vmpywoh(r21:20, r31:30):sat
+# CHECK: r17:16 += vmpywoh(r21:20,r31:30):sat
0xf0 0xde 0x94 0xea
-# CHECK: r17:16 += vmpywoh(r21:20, r31:30):<<1:sat
+# CHECK: r17:16 += vmpywoh(r21:20,r31:30):<<1:sat
0xb0 0xde 0x34 0xea
-# CHECK: r17:16 += vmpyweh(r21:20, r31:30):rnd:sat
+# CHECK: r17:16 += vmpyweh(r21:20,r31:30):rnd:sat
0xb0 0xde 0xb4 0xea
-# CHECK: r17:16 += vmpyweh(r21:20, r31:30):<<1:rnd:sat
+# CHECK: r17:16 += vmpyweh(r21:20,r31:30):<<1:rnd:sat
0xf0 0xde 0x34 0xea
-# CHECK: r17:16 += vmpywoh(r21:20, r31:30):rnd:sat
+# CHECK: r17:16 += vmpywoh(r21:20,r31:30):rnd:sat
0xf0 0xde 0xb4 0xea
-# CHECK: r17:16 += vmpywoh(r21:20, r31:30):<<1:rnd:sat
+# CHECK: r17:16 += vmpywoh(r21:20,r31:30):<<1:rnd:sat
# Vector multiply word by unsigned half (32x16)
0xb0 0xde 0x54 0xe8
-# CHECK: r17:16 = vmpyweuh(r21:20, r31:30):sat
+# CHECK: r17:16 = vmpyweuh(r21:20,r31:30):sat
0xb0 0xde 0xd4 0xe8
-# CHECK: r17:16 = vmpyweuh(r21:20, r31:30):<<1:sat
+# CHECK: r17:16 = vmpyweuh(r21:20,r31:30):<<1:sat
0xf0 0xde 0x54 0xe8
-# CHECK: r17:16 = vmpywouh(r21:20, r31:30):sat
+# CHECK: r17:16 = vmpywouh(r21:20,r31:30):sat
0xf0 0xde 0xd4 0xe8
-# CHECK: r17:16 = vmpywouh(r21:20, r31:30):<<1:sat
+# CHECK: r17:16 = vmpywouh(r21:20,r31:30):<<1:sat
0xb0 0xde 0x74 0xe8
-# CHECK: r17:16 = vmpyweuh(r21:20, r31:30):rnd:sat
+# CHECK: r17:16 = vmpyweuh(r21:20,r31:30):rnd:sat
0xb0 0xde 0xf4 0xe8
-# CHECK: r17:16 = vmpyweuh(r21:20, r31:30):<<1:rnd:sat
+# CHECK: r17:16 = vmpyweuh(r21:20,r31:30):<<1:rnd:sat
0xf0 0xde 0x74 0xe8
-# CHECK: r17:16 = vmpywouh(r21:20, r31:30):rnd:sat
+# CHECK: r17:16 = vmpywouh(r21:20,r31:30):rnd:sat
0xf0 0xde 0xf4 0xe8
-# CHECK: r17:16 = vmpywouh(r21:20, r31:30):<<1:rnd:sat
+# CHECK: r17:16 = vmpywouh(r21:20,r31:30):<<1:rnd:sat
0xb0 0xde 0x54 0xea
-# CHECK: r17:16 += vmpyweuh(r21:20, r31:30):sat
+# CHECK: r17:16 += vmpyweuh(r21:20,r31:30):sat
0xb0 0xde 0xd4 0xea
-# CHECK: r17:16 += vmpyweuh(r21:20, r31:30):<<1:sat
+# CHECK: r17:16 += vmpyweuh(r21:20,r31:30):<<1:sat
0xf0 0xde 0x54 0xea
-# CHECK: r17:16 += vmpywouh(r21:20, r31:30):sat
+# CHECK: r17:16 += vmpywouh(r21:20,r31:30):sat
0xf0 0xde 0xd4 0xea
-# CHECK: r17:16 += vmpywouh(r21:20, r31:30):<<1:sat
+# CHECK: r17:16 += vmpywouh(r21:20,r31:30):<<1:sat
0xb0 0xde 0x74 0xea
-# CHECK: r17:16 += vmpyweuh(r21:20, r31:30):rnd:sat
+# CHECK: r17:16 += vmpyweuh(r21:20,r31:30):rnd:sat
0xb0 0xde 0xf4 0xea
-# CHECK: r17:16 += vmpyweuh(r21:20, r31:30):<<1:rnd:sat
+# CHECK: r17:16 += vmpyweuh(r21:20,r31:30):<<1:rnd:sat
0xf0 0xde 0x74 0xea
-# CHECK: r17:16 += vmpywouh(r21:20, r31:30):rnd:sat
+# CHECK: r17:16 += vmpywouh(r21:20,r31:30):rnd:sat
0xf0 0xde 0xf4 0xea
-# CHECK: r17:16 += vmpywouh(r21:20, r31:30):<<1:rnd:sat
+# CHECK: r17:16 += vmpywouh(r21:20,r31:30):<<1:rnd:sat
# Multiply signed halfwords
0x10 0xdf 0x95 0xe4
-# CHECK: r17:16 = mpy(r21.l, r31.l):<<1
+# CHECK: r17:16 = mpy(r21.l,r31.l):<<1
0x30 0xdf 0x95 0xe4
-# CHECK: r17:16 = mpy(r21.l, r31.h):<<1
+# CHECK: r17:16 = mpy(r21.l,r31.h):<<1
0x50 0xdf 0x95 0xe4
-# CHECK: r17:16 = mpy(r21.h, r31.l):<<1
+# CHECK: r17:16 = mpy(r21.h,r31.l):<<1
0x70 0xdf 0x95 0xe4
-# CHECK: r17:16 = mpy(r21.h, r31.h):<<1
+# CHECK: r17:16 = mpy(r21.h,r31.h):<<1
0x10 0xdf 0xb5 0xe4
-# CHECK: r17:16 = mpy(r21.l, r31.l):<<1:rnd
+# CHECK: r17:16 = mpy(r21.l,r31.l):<<1:rnd
0x30 0xdf 0xb5 0xe4
-# CHECK: r17:16 = mpy(r21.l, r31.h):<<1:rnd
+# CHECK: r17:16 = mpy(r21.l,r31.h):<<1:rnd
0x50 0xdf 0xb5 0xe4
-# CHECK: r17:16 = mpy(r21.h, r31.l):<<1:rnd
+# CHECK: r17:16 = mpy(r21.h,r31.l):<<1:rnd
0x70 0xdf 0xb5 0xe4
-# CHECK: r17:16 = mpy(r21.h, r31.h):<<1:rnd
+# CHECK: r17:16 = mpy(r21.h,r31.h):<<1:rnd
0x10 0xdf 0x95 0xe6
-# CHECK: r17:16 += mpy(r21.l, r31.l):<<1
+# CHECK: r17:16 += mpy(r21.l,r31.l):<<1
0x30 0xdf 0x95 0xe6
-# CHECK: r17:16 += mpy(r21.l, r31.h):<<1
+# CHECK: r17:16 += mpy(r21.l,r31.h):<<1
0x50 0xdf 0x95 0xe6
-# CHECK: r17:16 += mpy(r21.h, r31.l):<<1
+# CHECK: r17:16 += mpy(r21.h,r31.l):<<1
0x70 0xdf 0x95 0xe6
-# CHECK: r17:16 += mpy(r21.h, r31.h):<<1
+# CHECK: r17:16 += mpy(r21.h,r31.h):<<1
0x10 0xdf 0xb5 0xe6
-# CHECK: r17:16 -= mpy(r21.l, r31.l):<<1
+# CHECK: r17:16 -= mpy(r21.l,r31.l):<<1
0x30 0xdf 0xb5 0xe6
-# CHECK: r17:16 -= mpy(r21.l, r31.h):<<1
+# CHECK: r17:16 -= mpy(r21.l,r31.h):<<1
0x50 0xdf 0xb5 0xe6
-# CHECK: r17:16 -= mpy(r21.h, r31.l):<<1
+# CHECK: r17:16 -= mpy(r21.h,r31.l):<<1
0x70 0xdf 0xb5 0xe6
-# CHECK: r17:16 -= mpy(r21.h, r31.h):<<1
+# CHECK: r17:16 -= mpy(r21.h,r31.h):<<1
0x11 0xdf 0x95 0xec
-# CHECK: r17 = mpy(r21.l, r31.l):<<1
+# CHECK: r17 = mpy(r21.l,r31.l):<<1
0x31 0xdf 0x95 0xec
-# CHECK: r17 = mpy(r21.l, r31.h):<<1
+# CHECK: r17 = mpy(r21.l,r31.h):<<1
0x51 0xdf 0x95 0xec
-# CHECK: r17 = mpy(r21.h, r31.l):<<1
+# CHECK: r17 = mpy(r21.h,r31.l):<<1
0x71 0xdf 0x95 0xec
-# CHECK: r17 = mpy(r21.h, r31.h):<<1
+# CHECK: r17 = mpy(r21.h,r31.h):<<1
0x91 0xdf 0x95 0xec
-# CHECK: r17 = mpy(r21.l, r31.l):<<1:sat
+# CHECK: r17 = mpy(r21.l,r31.l):<<1:sat
0xb1 0xdf 0x95 0xec
-# CHECK: r17 = mpy(r21.l, r31.h):<<1:sat
+# CHECK: r17 = mpy(r21.l,r31.h):<<1:sat
0xd1 0xdf 0x95 0xec
-# CHECK: r17 = mpy(r21.h, r31.l):<<1:sat
+# CHECK: r17 = mpy(r21.h,r31.l):<<1:sat
0xf1 0xdf 0x95 0xec
-# CHECK: r17 = mpy(r21.h, r31.h):<<1:sat
+# CHECK: r17 = mpy(r21.h,r31.h):<<1:sat
0x11 0xdf 0xb5 0xec
-# CHECK: r17 = mpy(r21.l, r31.l):<<1:rnd
+# CHECK: r17 = mpy(r21.l,r31.l):<<1:rnd
0x31 0xdf 0xb5 0xec
-# CHECK: r17 = mpy(r21.l, r31.h):<<1:rnd
+# CHECK: r17 = mpy(r21.l,r31.h):<<1:rnd
0x51 0xdf 0xb5 0xec
-# CHECK: r17 = mpy(r21.h, r31.l):<<1:rnd
+# CHECK: r17 = mpy(r21.h,r31.l):<<1:rnd
0x71 0xdf 0xb5 0xec
-# CHECK: r17 = mpy(r21.h, r31.h):<<1:rnd
+# CHECK: r17 = mpy(r21.h,r31.h):<<1:rnd
0x91 0xdf 0xb5 0xec
-# CHECK: r17 = mpy(r21.l, r31.l):<<1:rnd:sat
+# CHECK: r17 = mpy(r21.l,r31.l):<<1:rnd:sat
0xb1 0xdf 0xb5 0xec
-# CHECK: r17 = mpy(r21.l, r31.h):<<1:rnd:sat
+# CHECK: r17 = mpy(r21.l,r31.h):<<1:rnd:sat
0xd1 0xdf 0xb5 0xec
-# CHECK: r17 = mpy(r21.h, r31.l):<<1:rnd:sat
+# CHECK: r17 = mpy(r21.h,r31.l):<<1:rnd:sat
0xf1 0xdf 0xb5 0xec
-# CHECK: r17 = mpy(r21.h, r31.h):<<1:rnd:sat
+# CHECK: r17 = mpy(r21.h,r31.h):<<1:rnd:sat
0x11 0xdf 0x95 0xee
-# CHECK: r17 += mpy(r21.l, r31.l):<<1
+# CHECK: r17 += mpy(r21.l,r31.l):<<1
0x31 0xdf 0x95 0xee
-# CHECK: r17 += mpy(r21.l, r31.h):<<1
+# CHECK: r17 += mpy(r21.l,r31.h):<<1
0x51 0xdf 0x95 0xee
-# CHECK: r17 += mpy(r21.h, r31.l):<<1
+# CHECK: r17 += mpy(r21.h,r31.l):<<1
0x71 0xdf 0x95 0xee
-# CHECK: r17 += mpy(r21.h, r31.h):<<1
+# CHECK: r17 += mpy(r21.h,r31.h):<<1
0x91 0xdf 0x95 0xee
-# CHECK: r17 += mpy(r21.l, r31.l):<<1:sat
+# CHECK: r17 += mpy(r21.l,r31.l):<<1:sat
0xb1 0xdf 0x95 0xee
-# CHECK: r17 += mpy(r21.l, r31.h):<<1:sat
+# CHECK: r17 += mpy(r21.l,r31.h):<<1:sat
0xd1 0xdf 0x95 0xee
-# CHECK: r17 += mpy(r21.h, r31.l):<<1:sat
+# CHECK: r17 += mpy(r21.h,r31.l):<<1:sat
0xf1 0xdf 0x95 0xee
-# CHECK: r17 += mpy(r21.h, r31.h):<<1:sat
+# CHECK: r17 += mpy(r21.h,r31.h):<<1:sat
0x11 0xdf 0xb5 0xee
-# CHECK: r17 -= mpy(r21.l, r31.l):<<1
+# CHECK: r17 -= mpy(r21.l,r31.l):<<1
0x31 0xdf 0xb5 0xee
-# CHECK: r17 -= mpy(r21.l, r31.h):<<1
+# CHECK: r17 -= mpy(r21.l,r31.h):<<1
0x51 0xdf 0xb5 0xee
-# CHECK: r17 -= mpy(r21.h, r31.l):<<1
+# CHECK: r17 -= mpy(r21.h,r31.l):<<1
0x71 0xdf 0xb5 0xee
-# CHECK: r17 -= mpy(r21.h, r31.h):<<1
+# CHECK: r17 -= mpy(r21.h,r31.h):<<1
0x91 0xdf 0xb5 0xee
-# CHECK: r17 -= mpy(r21.l, r31.l):<<1:sat
+# CHECK: r17 -= mpy(r21.l,r31.l):<<1:sat
0xb1 0xdf 0xb5 0xee
-# CHECK: r17 -= mpy(r21.l, r31.h):<<1:sat
+# CHECK: r17 -= mpy(r21.l,r31.h):<<1:sat
0xd1 0xdf 0xb5 0xee
-# CHECK: r17 -= mpy(r21.h, r31.l):<<1:sat
+# CHECK: r17 -= mpy(r21.h,r31.l):<<1:sat
0xf1 0xdf 0xb5 0xee
-# CHECK: r17 -= mpy(r21.h, r31.h):<<1:sat
+# CHECK: r17 -= mpy(r21.h,r31.h):<<1:sat
# Multiply unsigned halfwords
0x10 0xdf 0xd5 0xe4
-# CHECK: r17:16 = mpyu(r21.l, r31.l):<<1
+# CHECK: r17:16 = mpyu(r21.l,r31.l):<<1
0x30 0xdf 0xd5 0xe4
-# CHECK: r17:16 = mpyu(r21.l, r31.h):<<1
+# CHECK: r17:16 = mpyu(r21.l,r31.h):<<1
0x50 0xdf 0xd5 0xe4
-# CHECK: r17:16 = mpyu(r21.h, r31.l):<<1
+# CHECK: r17:16 = mpyu(r21.h,r31.l):<<1
0x70 0xdf 0xd5 0xe4
-# CHECK: r17:16 = mpyu(r21.h, r31.h):<<1
+# CHECK: r17:16 = mpyu(r21.h,r31.h):<<1
0x10 0xdf 0xd5 0xe6
-# CHECK: r17:16 += mpyu(r21.l, r31.l):<<1
+# CHECK: r17:16 += mpyu(r21.l,r31.l):<<1
0x30 0xdf 0xd5 0xe6
-# CHECK: r17:16 += mpyu(r21.l, r31.h):<<1
+# CHECK: r17:16 += mpyu(r21.l,r31.h):<<1
0x50 0xdf 0xd5 0xe6
-# CHECK: r17:16 += mpyu(r21.h, r31.l):<<1
+# CHECK: r17:16 += mpyu(r21.h,r31.l):<<1
0x70 0xdf 0xd5 0xe6
-# CHECK: r17:16 += mpyu(r21.h, r31.h):<<1
+# CHECK: r17:16 += mpyu(r21.h,r31.h):<<1
0x10 0xdf 0xf5 0xe6
-# CHECK: r17:16 -= mpyu(r21.l, r31.l):<<1
+# CHECK: r17:16 -= mpyu(r21.l,r31.l):<<1
0x30 0xdf 0xf5 0xe6
-# CHECK: r17:16 -= mpyu(r21.l, r31.h):<<1
+# CHECK: r17:16 -= mpyu(r21.l,r31.h):<<1
0x50 0xdf 0xf5 0xe6
-# CHECK: r17:16 -= mpyu(r21.h, r31.l):<<1
+# CHECK: r17:16 -= mpyu(r21.h,r31.l):<<1
0x70 0xdf 0xf5 0xe6
-# CHECK: r17:16 -= mpyu(r21.h, r31.h):<<1
+# CHECK: r17:16 -= mpyu(r21.h,r31.h):<<1
0x11 0xdf 0xd5 0xec
-# CHECK: r17 = mpyu(r21.l, r31.l):<<1
+# CHECK: r17 = mpyu(r21.l,r31.l):<<1
0x31 0xdf 0xd5 0xec
-# CHECK: r17 = mpyu(r21.l, r31.h):<<1
+# CHECK: r17 = mpyu(r21.l,r31.h):<<1
0x51 0xdf 0xd5 0xec
-# CHECK: r17 = mpyu(r21.h, r31.l):<<1
+# CHECK: r17 = mpyu(r21.h,r31.l):<<1
0x71 0xdf 0xd5 0xec
-# CHECK: r17 = mpyu(r21.h, r31.h):<<1
+# CHECK: r17 = mpyu(r21.h,r31.h):<<1
0x11 0xdf 0xd5 0xee
-# CHECK: r17 += mpyu(r21.l, r31.l):<<1
+# CHECK: r17 += mpyu(r21.l,r31.l):<<1
0x31 0xdf 0xd5 0xee
-# CHECK: r17 += mpyu(r21.l, r31.h):<<1
+# CHECK: r17 += mpyu(r21.l,r31.h):<<1
0x51 0xdf 0xd5 0xee
-# CHECK: r17 += mpyu(r21.h, r31.l):<<1
+# CHECK: r17 += mpyu(r21.h,r31.l):<<1
0x71 0xdf 0xd5 0xee
-# CHECK: r17 += mpyu(r21.h, r31.h):<<1
+# CHECK: r17 += mpyu(r21.h,r31.h):<<1
0x11 0xdf 0xf5 0xee
-# CHECK: r17 -= mpyu(r21.l, r31.l):<<1
+# CHECK: r17 -= mpyu(r21.l,r31.l):<<1
0x31 0xdf 0xf5 0xee
-# CHECK: r17 -= mpyu(r21.l, r31.h):<<1
+# CHECK: r17 -= mpyu(r21.l,r31.h):<<1
0x51 0xdf 0xf5 0xee
-# CHECK: r17 -= mpyu(r21.h, r31.l):<<1
+# CHECK: r17 -= mpyu(r21.h,r31.l):<<1
0x71 0xdf 0xf5 0xee
-# CHECK: r17 -= mpyu(r21.h, r31.h):<<1
+# CHECK: r17 -= mpyu(r21.h,r31.h):<<1
# Polynomial multiply words
0xf0 0xdf 0x55 0xe5
-# CHECK: r17:16 = pmpyw(r21, r31)
+# CHECK: r17:16 = pmpyw(r21,r31)
0xf0 0xdf 0x35 0xe7
-# CHECK: r17:16 ^= pmpyw(r21, r31)
+# CHECK: r17:16 ^= pmpyw(r21,r31)
# Vector reduce multiply word by signed half (32x16)
0x50 0xde 0x34 0xe8
-# CHECK: r17:16 = vrmpywoh(r21:20, r31:30)
+# CHECK: r17:16 = vrmpywoh(r21:20,r31:30)
0x50 0xde 0xb4 0xe8
-# CHECK: r17:16 = vrmpywoh(r21:20, r31:30):<<1
+# CHECK: r17:16 = vrmpywoh(r21:20,r31:30):<<1
0x90 0xde 0x54 0xe8
-# CHECK: r17:16 = vrmpyweh(r21:20, r31:30)
+# CHECK: r17:16 = vrmpyweh(r21:20,r31:30)
0x90 0xde 0xd4 0xe8
-# CHECK: r17:16 = vrmpyweh(r21:20, r31:30):<<1
+# CHECK: r17:16 = vrmpyweh(r21:20,r31:30):<<1
0xd0 0xde 0x74 0xea
-# CHECK: r17:16 += vrmpywoh(r21:20, r31:30)
+# CHECK: r17:16 += vrmpywoh(r21:20,r31:30)
0xd0 0xde 0xf4 0xea
-# CHECK: r17:16 += vrmpywoh(r21:20, r31:30):<<1
+# CHECK: r17:16 += vrmpywoh(r21:20,r31:30):<<1
0xd0 0xde 0x34 0xea
-# CHECK: r17:16 += vrmpyweh(r21:20, r31:30)
+# CHECK: r17:16 += vrmpyweh(r21:20,r31:30)
0xd0 0xde 0xb4 0xea
-# CHECK: r17:16 += vrmpyweh(r21:20, r31:30):<<1
+# CHECK: r17:16 += vrmpyweh(r21:20,r31:30):<<1
# Multiply and use upper result
0x31 0xdf 0x15 0xed
-# CHECK: r17 = mpy(r21, r31)
+# CHECK: r17 = mpy(r21,r31)
0x31 0xdf 0x35 0xed
-# CHECK: r17 = mpy(r21, r31):rnd
+# CHECK: r17 = mpy(r21,r31):rnd
0x31 0xdf 0x55 0xed
-# CHECK: r17 = mpyu(r21, r31)
+# CHECK: r17 = mpyu(r21,r31)
0x31 0xdf 0x75 0xed
-# CHECK: r17 = mpysu(r21, r31)
+# CHECK: r17 = mpysu(r21,r31)
0x11 0xdf 0xb5 0xed
-# CHECK: r17 = mpy(r21, r31.h):<<1:sat
+# CHECK: r17 = mpy(r21,r31.h):<<1:sat
0x31 0xdf 0xb5 0xed
-# CHECK: r17 = mpy(r21, r31.l):<<1:sat
+# CHECK: r17 = mpy(r21,r31.l):<<1:sat
0x91 0xdf 0xb5 0xed
-# CHECK: r17 = mpy(r21, r31.h):<<1:rnd:sat
+# CHECK: r17 = mpy(r21,r31.h):<<1:rnd:sat
0x11 0xdf 0xf5 0xed
-# CHECK: r17 = mpy(r21, r31):<<1:sat
+# CHECK: r17 = mpy(r21,r31):<<1:sat
0x91 0xdf 0xf5 0xed
-# CHECK: r17 = mpy(r21, r31.l):<<1:rnd:sat
+# CHECK: r17 = mpy(r21,r31.l):<<1:rnd:sat
0x51 0xdf 0xb5 0xed
-# CHECK: r17 = mpy(r21, r31):<<1
+# CHECK: r17 = mpy(r21,r31):<<1
0x11 0xdf 0x75 0xef
-# CHECK: r17 += mpy(r21, r31):<<1:sat
+# CHECK: r17 += mpy(r21,r31):<<1:sat
0x31 0xdf 0x75 0xef
-# CHECK: r17 -= mpy(r21, r31):<<1:sat
+# CHECK: r17 -= mpy(r21,r31):<<1:sat
# Multiply and use full result
0x10 0xdf 0x15 0xe5
-# CHECK: r17:16 = mpy(r21, r31)
+# CHECK: r17:16 = mpy(r21,r31)
0x10 0xdf 0x55 0xe5
-# CHECK: r17:16 = mpyu(r21, r31)
+# CHECK: r17:16 = mpyu(r21,r31)
0x10 0xdf 0x15 0xe7
-# CHECK: r17:16 += mpy(r21, r31)
+# CHECK: r17:16 += mpy(r21,r31)
0x10 0xdf 0x35 0xe7
-# CHECK: r17:16 -= mpy(r21, r31)
+# CHECK: r17:16 -= mpy(r21,r31)
0x10 0xdf 0x55 0xe7
-# CHECK: r17:16 += mpyu(r21, r31)
+# CHECK: r17:16 += mpyu(r21,r31)
0x10 0xdf 0x75 0xe7
-# CHECK: r17:16 -= mpyu(r21, r31)
+# CHECK: r17:16 -= mpyu(r21,r31)
# Vector dual multiply
0x90 0xde 0x14 0xe8
-# CHECK: r17:16 = vdmpy(r21:20, r31:30):sat
+# CHECK: r17:16 = vdmpy(r21:20,r31:30):sat
0x90 0xde 0x94 0xe8
-# CHECK: r17:16 = vdmpy(r21:20, r31:30):<<1:sat
+# CHECK: r17:16 = vdmpy(r21:20,r31:30):<<1:sat
0x90 0xde 0x14 0xea
-# CHECK: r17:16 += vdmpy(r21:20, r31:30):sat
+# CHECK: r17:16 += vdmpy(r21:20,r31:30):sat
0x90 0xde 0x94 0xea
-# CHECK: r17:16 += vdmpy(r21:20, r31:30):<<1:sat
+# CHECK: r17:16 += vdmpy(r21:20,r31:30):<<1:sat
# Vector dual multiply with round and pack
0x11 0xde 0x14 0xe9
-# CHECK: r17 = vdmpy(r21:20, r31:30):rnd:sat
+# CHECK: r17 = vdmpy(r21:20,r31:30):rnd:sat
0x11 0xde 0x94 0xe9
-# CHECK: r17 = vdmpy(r21:20, r31:30):<<1:rnd:sat
+# CHECK: r17 = vdmpy(r21:20,r31:30):<<1:rnd:sat
# Vector reduce multiply bytes
0x30 0xde 0x94 0xe8
-# CHECK: r17:16 = vrmpybu(r21:20, r31:30)
+# CHECK: r17:16 = vrmpybu(r21:20,r31:30)
0x30 0xde 0xd4 0xe8
-# CHECK: r17:16 = vrmpybsu(r21:20, r31:30)
+# CHECK: r17:16 = vrmpybsu(r21:20,r31:30)
0x30 0xde 0x94 0xea
-# CHECK: r17:16 += vrmpybu(r21:20, r31:30)
+# CHECK: r17:16 += vrmpybu(r21:20,r31:30)
0x30 0xde 0xd4 0xea
-# CHECK: r17:16 += vrmpybsu(r21:20, r31:30)
+# CHECK: r17:16 += vrmpybsu(r21:20,r31:30)
# Vector dual multiply signed by unsigned bytes
0x30 0xde 0xb4 0xe8
-# CHECK: r17:16 = vdmpybsu(r21:20, r31:30):sat
+# CHECK: r17:16 = vdmpybsu(r21:20,r31:30):sat
0x30 0xde 0x34 0xea
-# CHECK: r17:16 += vdmpybsu(r21:20, r31:30):sat
+# CHECK: r17:16 += vdmpybsu(r21:20,r31:30):sat
# Vector multiply even haldwords
0xd0 0xde 0x14 0xe8
-# CHECK: r17:16 = vmpyeh(r21:20, r31:30):sat
+# CHECK: r17:16 = vmpyeh(r21:20,r31:30):sat
0xd0 0xde 0x94 0xe8
-# CHECK: r17:16 = vmpyeh(r21:20, r31:30):<<1:sat
+# CHECK: r17:16 = vmpyeh(r21:20,r31:30):<<1:sat
0x50 0xde 0x34 0xea
-# CHECK: r17:16 += vmpyeh(r21:20, r31:30)
+# CHECK: r17:16 += vmpyeh(r21:20,r31:30)
0xd0 0xde 0x14 0xea
-# CHECK: r17:16 += vmpyeh(r21:20, r31:30):sat
+# CHECK: r17:16 += vmpyeh(r21:20,r31:30):sat
0xd0 0xde 0x94 0xea
-# CHECK: r17:16 += vmpyeh(r21:20, r31:30):<<1:sat
+# CHECK: r17:16 += vmpyeh(r21:20,r31:30):<<1:sat
# Vector multiply halfwords
0xb0 0xdf 0x15 0xe5
-# CHECK: r17:16 = vmpyh(r21, r31):sat
+# CHECK: r17:16 = vmpyh(r21,r31):sat
0xb0 0xdf 0x95 0xe5
-# CHECK: r17:16 = vmpyh(r21, r31):<<1:sat
+# CHECK: r17:16 = vmpyh(r21,r31):<<1:sat
0x30 0xdf 0x35 0xe7
-# CHECK: r17:16 += vmpyh(r21, r31)
+# CHECK: r17:16 += vmpyh(r21,r31)
0xb0 0xdf 0x15 0xe7
-# CHECK: r17:16 += vmpyh(r21, r31):sat
+# CHECK: r17:16 += vmpyh(r21,r31):sat
0xb0 0xdf 0x95 0xe7
-# CHECK: r17:16 += vmpyh(r21, r31):<<1:sat
+# CHECK: r17:16 += vmpyh(r21,r31):<<1:sat
# Vector multiply halfwords with round and pack
0xf1 0xdf 0x35 0xed
-# CHECK: r17 = vmpyh(r21, r31):rnd:sat
+# CHECK: r17 = vmpyh(r21,r31):rnd:sat
0xf1 0xdf 0xb5 0xed
-# CHECK: r17 = vmpyh(r21, r31):<<1:rnd:sat
+# CHECK: r17 = vmpyh(r21,r31):<<1:rnd:sat
# Vector multiply halfwords signed by unsigned
0xf0 0xdf 0x15 0xe5
-# CHECK: r17:16 = vmpyhsu(r21, r31):sat
+# CHECK: r17:16 = vmpyhsu(r21,r31):sat
0xf0 0xdf 0x95 0xe5
-# CHECK: r17:16 = vmpyhsu(r21, r31):<<1:sat
+# CHECK: r17:16 = vmpyhsu(r21,r31):<<1:sat
0xb0 0xdf 0x75 0xe7
-# CHECK: r17:16 += vmpyhsu(r21, r31):sat
+# CHECK: r17:16 += vmpyhsu(r21,r31):sat
0xb0 0xdf 0xf5 0xe7
-# CHECK: r17:16 += vmpyhsu(r21, r31):<<1:sat
+# CHECK: r17:16 += vmpyhsu(r21,r31):<<1:sat
# Vector reduce multiply halfwords
0x50 0xde 0x14 0xe8
-# CHECK: r17:16 = vrmpyh(r21:20, r31:30)
+# CHECK: r17:16 = vrmpyh(r21:20,r31:30)
0x50 0xde 0x14 0xea
-# CHECK: r17:16 += vrmpyh(r21:20, r31:30)
+# CHECK: r17:16 += vrmpyh(r21:20,r31:30)
# Vector multiply bytes
0x30 0xdf 0x55 0xe5
-# CHECK: r17:16 = vmpybsu(r21, r31)
+# CHECK: r17:16 = vmpybsu(r21,r31)
0x30 0xdf 0x95 0xe5
-# CHECK: r17:16 = vmpybu(r21, r31)
+# CHECK: r17:16 = vmpybu(r21,r31)
0x30 0xdf 0x95 0xe7
-# CHECK: r17:16 += vmpybu(r21, r31)
+# CHECK: r17:16 += vmpybu(r21,r31)
0x30 0xdf 0xd5 0xe7
-# CHECK: r17:16 += vmpybsu(r21, r31)
+# CHECK: r17:16 += vmpybsu(r21,r31)
# Vector polynomial multiply halfwords
0xf0 0xdf 0xd5 0xe5
-# CHECK: r17:16 = vpmpyh(r21, r31)
+# CHECK: r17:16 = vpmpyh(r21,r31)
0xf0 0xdf 0xb5 0xe7
-# CHECK: r17:16 ^= vpmpyh(r21, r31)
+# CHECK: r17:16 ^= vpmpyh(r21,r31)
Modified: llvm/trunk/test/MC/Disassembler/Hexagon/xtype_perm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/xtype_perm.txt?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Hexagon/xtype_perm.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Hexagon/xtype_perm.txt Fri Feb 10 09:33:13 2017
@@ -3,7 +3,7 @@
# CABAC decode bin
0xd0 0xde 0xd4 0xc1
-# CHECK: r17:16 = decbin(r21:20, r31:30)
+# CHECK: r17:16 = decbin(r21:20,r31:30)
# Saturate
0x11 0xc0 0xd4 0x88
@@ -23,9 +23,9 @@
# Vector align
0x70 0xd4 0x1e 0xc2
-# CHECK: r17:16 = valignb(r21:20, r31:30, p3)
+# CHECK: r17:16 = valignb(r21:20,r31:30,p3)
0x70 0xde 0x94 0xc2
-# CHECK: r17:16 = vspliceb(r21:20, r31:30, p3)
+# CHECK: r17:16 = vspliceb(r21:20,r31:30,p3)
# Vector round and pack
0x91 0xc0 0x94 0x88
@@ -59,13 +59,13 @@
# Vector shuffle
0x50 0xde 0x14 0xc1
-# CHECK: r17:16 = shuffeb(r21:20, r31:30)
+# CHECK: r17:16 = shuffeb(r21:20,r31:30)
0x90 0xd4 0x1e 0xc1
-# CHECK: r17:16 = shuffob(r21:20, r31:30)
+# CHECK: r17:16 = shuffob(r21:20,r31:30)
0xd0 0xde 0x14 0xc1
-# CHECK: r17:16 = shuffeh(r21:20, r31:30)
+# CHECK: r17:16 = shuffeh(r21:20,r31:30)
0x10 0xd4 0x9e 0xc1
-# CHECK: r17:16 = shuffoh(r21:20, r31:30)
+# CHECK: r17:16 = shuffoh(r21:20,r31:30)
# Vector splat bytes
0xf1 0xc0 0x55 0x8c
@@ -77,9 +77,9 @@
# Vector splice
0x70 0xde 0x94 0xc0
-# CHECK: r17:16 = vspliceb(r21:20, r31:30, #3)
+# CHECK: r17:16 = vspliceb(r21:20,r31:30,#3)
0x70 0xde 0x94 0xc2
-# CHECK: r17:16 = vspliceb(r21:20, r31:30, p3)
+# CHECK: r17:16 = vspliceb(r21:20,r31:30,p3)
# Vector sign extend
0x10 0xc0 0x15 0x84
@@ -93,9 +93,9 @@
0x51 0xc0 0x94 0x88
# CHECK: r17 = vtrunehb(r21:20)
0x50 0xde 0x94 0xc1
-# CHECK: r17:16 = vtrunewh(r21:20, r31:30)
+# CHECK: r17:16 = vtrunewh(r21:20,r31:30)
0x90 0xde 0x94 0xc1
-# CHECK: r17:16 = vtrunowh(r21:20, r31:30)
+# CHECK: r17:16 = vtrunowh(r21:20,r31:30)
# Vector zero extend
0x50 0xc0 0x15 0x84
Modified: llvm/trunk/test/MC/Disassembler/Hexagon/xtype_pred.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/xtype_pred.txt?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Hexagon/xtype_pred.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Hexagon/xtype_pred.txt Fri Feb 10 09:33:13 2017
@@ -3,59 +3,59 @@
# Bounds check
0x83 0xf4 0x10 0xd2
-# CHECK: p3 = boundscheck(r17:16, r21:20):raw:lo
+# CHECK: p3 = boundscheck(r17:16,r21:20):raw:lo
0xa3 0xf4 0x10 0xd2
-# CHECK: p3 = boundscheck(r17:16, r21:20):raw:hi
+# CHECK: p3 = boundscheck(r17:16,r21:20):raw:hi
# Compare byte
0x43 0xd5 0xd1 0xc7
-# CHECK: p3 = cmpb.gt(r17, r21)
+# CHECK: p3 = cmpb.gt(r17,r21)
0xc3 0xd5 0xd1 0xc7
-# CHECK: p3 = cmpb.eq(r17, r21)
+# CHECK: p3 = cmpb.eq(r17,r21)
0xe3 0xd5 0xd1 0xc7
-# CHECK: p3 = cmpb.gtu(r17, r21)
+# CHECK: p3 = cmpb.gtu(r17,r21)
0xa3 0xc2 0x11 0xdd
-# CHECK: p3 = cmpb.eq(r17, #21)
+# CHECK: p3 = cmpb.eq(r17,#21)
0xa3 0xc2 0x31 0xdd
-# CHECK: p3 = cmpb.gt(r17, #21)
+# CHECK: p3 = cmpb.gt(r17,#21)
0xa3 0xc2 0x51 0xdd
-# CHECK: p3 = cmpb.gtu(r17, #21)
+# CHECK: p3 = cmpb.gtu(r17,#21)
# Compare half
0x63 0xd5 0xd1 0xc7
-# CHECK: p3 = cmph.eq(r17, r21)
+# CHECK: p3 = cmph.eq(r17,r21)
0x83 0xd5 0xd1 0xc7
-# CHECK: p3 = cmph.gt(r17, r21)
+# CHECK: p3 = cmph.gt(r17,r21)
0xa3 0xd5 0xd1 0xc7
-# CHECK: p3 = cmph.gtu(r17, r21)
+# CHECK: p3 = cmph.gtu(r17,r21)
0xab 0xc2 0x11 0xdd
-# CHECK: p3 = cmph.eq(r17, #21)
+# CHECK: p3 = cmph.eq(r17,#21)
0xab 0xc2 0x31 0xdd
-# CHECK: p3 = cmph.gt(r17, #21)
+# CHECK: p3 = cmph.gt(r17,#21)
0xab 0xc2 0x51 0xdd
-# CHECK: p3 = cmph.gtu(r17, #21)
+# CHECK: p3 = cmph.gtu(r17,#21)
# Compare doublewords
0x03 0xde 0x94 0xd2
-# CHECK: p3 = cmp.eq(r21:20, r31:30)
+# CHECK: p3 = cmp.eq(r21:20,r31:30)
0x43 0xde 0x94 0xd2
-# CHECK: p3 = cmp.gt(r21:20, r31:30)
+# CHECK: p3 = cmp.gt(r21:20,r31:30)
0x83 0xde 0x94 0xd2
-# CHECK: p3 = cmp.gtu(r21:20, r31:30)
+# CHECK: p3 = cmp.gtu(r21:20,r31:30)
# Compare bitmask
0x03 0xd5 0x91 0x85
-# CHECK: p3 = bitsclr(r17, #21)
+# CHECK: p3 = bitsclr(r17,#21)
0x03 0xd5 0xb1 0x85
-# CHECK: p3 = !bitsclr(r17, #21)
+# CHECK: p3 = !bitsclr(r17,#21)
0x03 0xd5 0x51 0xc7
-# CHECK: p3 = bitsset(r17, r21)
+# CHECK: p3 = bitsset(r17,r21)
0x03 0xd5 0x71 0xc7
-# CHECK: p3 = !bitsset(r17, r21)
+# CHECK: p3 = !bitsset(r17,r21)
0x03 0xd5 0x91 0xc7
-# CHECK: p3 = bitsclr(r17, r21)
+# CHECK: p3 = bitsclr(r17,r21)
0x03 0xd5 0xb1 0xc7
-# CHECK: p3 = !bitsclr(r17, r21)
+# CHECK: p3 = !bitsclr(r17,r21)
# mask generate from predicate
0x10 0xc3 0x00 0x86
@@ -63,7 +63,7 @@
# Check for TLB match
0x63 0xf5 0x10 0xd2
-# CHECK: p3 = tlbmatch(r17:16, r21)
+# CHECK: p3 = tlbmatch(r17:16,r21)
# Predicate Transfer
0x03 0xc0 0x45 0x85
@@ -73,64 +73,64 @@
# Test bit
0x03 0xd5 0x11 0x85
-# CHECK: p3 = tstbit(r17, #21)
+# CHECK: p3 = tstbit(r17,#21)
0x03 0xd5 0x31 0x85
-# CHECK: p3 = !tstbit(r17, #21)
+# CHECK: p3 = !tstbit(r17,#21)
0x03 0xd5 0x11 0xc7
-# CHECK: p3 = tstbit(r17, r21)
+# CHECK: p3 = tstbit(r17,r21)
0x03 0xd5 0x31 0xc7
-# CHECK: p3 = !tstbit(r17, r21)
+# CHECK: p3 = !tstbit(r17,r21)
# Vector compare halfwords
0x63 0xde 0x14 0xd2
-# CHECK: p3 = vcmph.eq(r21:20, r31:30)
+# CHECK: p3 = vcmph.eq(r21:20,r31:30)
0x83 0xde 0x14 0xd2
-# CHECK: p3 = vcmph.gt(r21:20, r31:30)
+# CHECK: p3 = vcmph.gt(r21:20,r31:30)
0xa3 0xde 0x14 0xd2
-# CHECK: p3 = vcmph.gtu(r21:20, r31:30)
+# CHECK: p3 = vcmph.gtu(r21:20,r31:30)
0xeb 0xc3 0x14 0xdc
-# CHECK: p3 = vcmph.eq(r21:20, #31)
+# CHECK: p3 = vcmph.eq(r21:20,#31)
0xeb 0xc3 0x34 0xdc
-# CHECK: p3 = vcmph.gt(r21:20, #31)
+# CHECK: p3 = vcmph.gt(r21:20,#31)
0xeb 0xc3 0x54 0xdc
-# CHECK: p3 = vcmph.gtu(r21:20, #31)
+# CHECK: p3 = vcmph.gtu(r21:20,#31)
# Vector compare bytes for any match
0x03 0xfe 0x14 0xd2
-# CHECK: p3 = any8(vcmpb.eq(r21:20, r31:30))
+# CHECK: p3 = any8(vcmpb.eq(r21:20,r31:30))
# Vector compare bytes
0x63 0xde 0x14 0xd2
-# CHECK: p3 = vcmph.eq(r21:20, r31:30)
+# CHECK: p3 = vcmph.eq(r21:20,r31:30)
0x83 0xde 0x14 0xd2
-# CHECK: p3 = vcmph.gt(r21:20, r31:30)
+# CHECK: p3 = vcmph.gt(r21:20,r31:30)
0xa3 0xde 0x14 0xd2
-# CHECK: p3 = vcmph.gtu(r21:20, r31:30)
+# CHECK: p3 = vcmph.gtu(r21:20,r31:30)
0xeb 0xc3 0x14 0xdc
-# CHECK: p3 = vcmph.eq(r21:20, #31)
+# CHECK: p3 = vcmph.eq(r21:20,#31)
0xeb 0xc3 0x34 0xdc
-# CHECK: p3 = vcmph.gt(r21:20, #31)
+# CHECK: p3 = vcmph.gt(r21:20,#31)
0xeb 0xc3 0x54 0xdc
-# CHECK: p3 = vcmph.gtu(r21:20, #31)
+# CHECK: p3 = vcmph.gtu(r21:20,#31)
# Vector compare words
0x03 0xde 0x14 0xd2
-# CHECK: p3 = vcmpw.eq(r21:20, r31:30)
+# CHECK: p3 = vcmpw.eq(r21:20,r31:30)
0x23 0xde 0x14 0xd2
-# CHECK: p3 = vcmpw.gt(r21:20, r31:30)
+# CHECK: p3 = vcmpw.gt(r21:20,r31:30)
0x43 0xde 0x14 0xd2
-# CHECK: p3 = vcmpw.gtu(r21:20, r31:30)
+# CHECK: p3 = vcmpw.gtu(r21:20,r31:30)
0xf3 0xc3 0x14 0xdc
-# CHECK: p3 = vcmpw.eq(r21:20, #31)
+# CHECK: p3 = vcmpw.eq(r21:20,#31)
0xf3 0xc3 0x34 0xdc
-# CHECK: p3 = vcmpw.gt(r21:20, #31)
+# CHECK: p3 = vcmpw.gt(r21:20,#31)
0xf3 0xc3 0x54 0xdc
-# CHECK: p3 = vcmpw.gtu(r21:20, #31)
+# CHECK: p3 = vcmpw.gtu(r21:20,#31)
# Viterbi pack even and odd predicate bits
0x11 0xc2 0x03 0x89
-# CHECK: r17 = vitpack(p3, p2)
+# CHECK: r17 = vitpack(p3,p2)
# Vector mux
0x70 0xde 0x14 0xd1
-# CHECK: r17:16 = vmux(p3, r21:20, r31:30)
+# CHECK: r17:16 = vmux(p3,r21:20,r31:30)
Modified: llvm/trunk/test/MC/Disassembler/Hexagon/xtype_shift.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/xtype_shift.txt?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Hexagon/xtype_shift.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Hexagon/xtype_shift.txt Fri Feb 10 09:33:13 2017
@@ -3,258 +3,258 @@
# Shift by immediate
0x10 0xdf 0x14 0x80
-# CHECK: r17:16 = asr(r21:20, #31)
+# CHECK: r17:16 = asr(r21:20,#31)
0x30 0xdf 0x14 0x80
-# CHECK: r17:16 = lsr(r21:20, #31)
+# CHECK: r17:16 = lsr(r21:20,#31)
0x50 0xdf 0x14 0x80
-# CHECK: r17:16 = asl(r21:20, #31)
+# CHECK: r17:16 = asl(r21:20,#31)
0x11 0xdf 0x15 0x8c
-# CHECK: r17 = asr(r21, #31)
+# CHECK: r17 = asr(r21,#31)
0x31 0xdf 0x15 0x8c
-# CHECK: r17 = lsr(r21, #31)
+# CHECK: r17 = lsr(r21,#31)
0x51 0xdf 0x15 0x8c
-# CHECK: r17 = asl(r21, #31)
+# CHECK: r17 = asl(r21,#31)
# Shift by immediate and accumulate
0x10 0xdf 0x14 0x82
-# CHECK: r17:16 -= asr(r21:20, #31)
+# CHECK: r17:16 -= asr(r21:20,#31)
0x30 0xdf 0x14 0x82
-# CHECK: r17:16 -= lsr(r21:20, #31)
+# CHECK: r17:16 -= lsr(r21:20,#31)
0x50 0xdf 0x14 0x82
-# CHECK: r17:16 -= asl(r21:20, #31)
+# CHECK: r17:16 -= asl(r21:20,#31)
0x90 0xdf 0x14 0x82
-# CHECK: r17:16 += asr(r21:20, #31)
+# CHECK: r17:16 += asr(r21:20,#31)
0xb0 0xdf 0x14 0x82
-# CHECK: r17:16 += lsr(r21:20, #31)
+# CHECK: r17:16 += lsr(r21:20,#31)
0xd0 0xdf 0x14 0x82
-# CHECK: r17:16 += asl(r21:20, #31)
+# CHECK: r17:16 += asl(r21:20,#31)
0x11 0xdf 0x15 0x8e
-# CHECK: r17 -= asr(r21, #31)
+# CHECK: r17 -= asr(r21,#31)
0x31 0xdf 0x15 0x8e
-# CHECK: r17 -= lsr(r21, #31)
+# CHECK: r17 -= lsr(r21,#31)
0x51 0xdf 0x15 0x8e
-# CHECK: r17 -= asl(r21, #31)
+# CHECK: r17 -= asl(r21,#31)
0x91 0xdf 0x15 0x8e
-# CHECK: r17 += asr(r21, #31)
+# CHECK: r17 += asr(r21,#31)
0xb1 0xdf 0x15 0x8e
-# CHECK: r17 += lsr(r21, #31)
+# CHECK: r17 += lsr(r21,#31)
0xd1 0xdf 0x15 0x8e
-# CHECK: r17 += asl(r21, #31)
+# CHECK: r17 += asl(r21,#31)
0x4c 0xf7 0x11 0xde
-# CHECK: r17 = add(#21, asl(r17, #23))
+# CHECK: r17 = add(#21,asl(r17,#23))
0x4e 0xf7 0x11 0xde
-# CHECK: r17 = sub(#21, asl(r17, #23))
+# CHECK: r17 = sub(#21,asl(r17,#23))
0x5c 0xf7 0x11 0xde
-# CHECK: r17 = add(#21, lsr(r17, #23))
+# CHECK: r17 = add(#21,lsr(r17,#23))
0x5e 0xf7 0x11 0xde
-# CHECK: r17 = sub(#21, lsr(r17, #23))
+# CHECK: r17 = sub(#21,lsr(r17,#23))
# Shift by immediate and add
0xf1 0xd5 0x1f 0xc4
-# CHECK: r17 = addasl(r21, r31, #7)
+# CHECK: r17 = addasl(r21,r31,#7)
# Shift by immediate and logical
0x10 0xdf 0x54 0x82
-# CHECK: r17:16 &= asr(r21:20, #31)
+# CHECK: r17:16 &= asr(r21:20,#31)
0x30 0xdf 0x54 0x82
-# CHECK: r17:16 &= lsr(r21:20, #31)
+# CHECK: r17:16 &= lsr(r21:20,#31)
0x50 0xdf 0x54 0x82
-# CHECK: r17:16 &= asl(r21:20, #31)
+# CHECK: r17:16 &= asl(r21:20,#31)
0x90 0xdf 0x54 0x82
-# CHECK: r17:16 |= asr(r21:20, #31)
+# CHECK: r17:16 |= asr(r21:20,#31)
0xb0 0xdf 0x54 0x82
-# CHECK: r17:16 |= lsr(r21:20, #31)
+# CHECK: r17:16 |= lsr(r21:20,#31)
0xd0 0xdf 0x54 0x82
-# CHECK: r17:16 |= asl(r21:20, #31)
+# CHECK: r17:16 |= asl(r21:20,#31)
0x30 0xdf 0x94 0x82
-# CHECK: r17:16 ^= lsr(r21:20, #31)
+# CHECK: r17:16 ^= lsr(r21:20,#31)
0x50 0xdf 0x94 0x82
-# CHECK: r17:16 ^= asl(r21:20, #31)
+# CHECK: r17:16 ^= asl(r21:20,#31)
0x11 0xdf 0x55 0x8e
-# CHECK: r17 &= asr(r21, #31)
+# CHECK: r17 &= asr(r21,#31)
0x31 0xdf 0x55 0x8e
-# CHECK: r17 &= lsr(r21, #31)
+# CHECK: r17 &= lsr(r21,#31)
0x51 0xdf 0x55 0x8e
-# CHECK: r17 &= asl(r21, #31)
+# CHECK: r17 &= asl(r21,#31)
0x91 0xdf 0x55 0x8e
-# CHECK: r17 |= asr(r21, #31)
+# CHECK: r17 |= asr(r21,#31)
0xb1 0xdf 0x55 0x8e
-# CHECK: r17 |= lsr(r21, #31)
+# CHECK: r17 |= lsr(r21,#31)
0xd1 0xdf 0x55 0x8e
-# CHECK: r17 |= asl(r21, #31)
+# CHECK: r17 |= asl(r21,#31)
0x31 0xdf 0x95 0x8e
-# CHECK: r17 ^= lsr(r21, #31)
+# CHECK: r17 ^= lsr(r21,#31)
0x51 0xdf 0x95 0x8e
-# CHECK: r17 ^= asl(r21, #31)
+# CHECK: r17 ^= asl(r21,#31)
0x48 0xff 0x11 0xde
-# CHECK: r17 = and(#21, asl(r17, #31))
+# CHECK: r17 = and(#21,asl(r17,#31))
0x4a 0xff 0x11 0xde
-# CHECK: r17 = or(#21, asl(r17, #31))
+# CHECK: r17 = or(#21,asl(r17,#31))
0x58 0xff 0x11 0xde
-# CHECK: r17 = and(#21, lsr(r17, #31))
+# CHECK: r17 = and(#21,lsr(r17,#31))
0x5a 0xff 0x11 0xde
-# CHECK: r17 = or(#21, lsr(r17, #31))
+# CHECK: r17 = or(#21,lsr(r17,#31))
# Shift right by immediate with rounding
0xf0 0xdf 0xd4 0x80
-# CHECK: r17:16 = asr(r21:20, #31):rnd
+# CHECK: r17:16 = asr(r21:20,#31):rnd
0x11 0xdf 0x55 0x8c
-# CHECK: r17 = asr(r21, #31):rnd
+# CHECK: r17 = asr(r21,#31):rnd
# Shift left by immediate with saturation
0x51 0xdf 0x55 0x8c
-# CHECK: r17 = asl(r21, #31):sat
+# CHECK: r17 = asl(r21,#31):sat
# Shift by register
0x10 0xdf 0x94 0xc3
-# CHECK: r17:16 = asr(r21:20, r31)
+# CHECK: r17:16 = asr(r21:20,r31)
0x50 0xdf 0x94 0xc3
-# CHECK: r17:16 = lsr(r21:20, r31)
+# CHECK: r17:16 = lsr(r21:20,r31)
0x90 0xdf 0x94 0xc3
-# CHECK: r17:16 = asl(r21:20, r31)
+# CHECK: r17:16 = asl(r21:20,r31)
0xd0 0xdf 0x94 0xc3
-# CHECK: r17:16 = lsl(r21:20, r31)
+# CHECK: r17:16 = lsl(r21:20,r31)
0x11 0xdf 0x55 0xc6
-# CHECK: r17 = asr(r21, r31)
+# CHECK: r17 = asr(r21,r31)
0x51 0xdf 0x55 0xc6
-# CHECK: r17 = lsr(r21, r31)
+# CHECK: r17 = lsr(r21,r31)
0x91 0xdf 0x55 0xc6
-# CHECK: r17 = asl(r21, r31)
+# CHECK: r17 = asl(r21,r31)
0xd1 0xdf 0x55 0xc6
-# CHECK: r17 = lsl(r21, r31)
+# CHECK: r17 = lsl(r21,r31)
0xf1 0xdf 0x8a 0xc6
-# CHECK: r17 = lsl(#21, r31)
+# CHECK: r17 = lsl(#21,r31)
# Shift by register and accumulate
0x10 0xdf 0x94 0xcb
-# CHECK: r17:16 -= asr(r21:20, r31)
+# CHECK: r17:16 -= asr(r21:20,r31)
0x50 0xdf 0x94 0xcb
-# CHECK: r17:16 -= lsr(r21:20, r31)
+# CHECK: r17:16 -= lsr(r21:20,r31)
0x90 0xdf 0x94 0xcb
-# CHECK: r17:16 -= asl(r21:20, r31)
+# CHECK: r17:16 -= asl(r21:20,r31)
0xd0 0xdf 0x94 0xcb
-# CHECK: r17:16 -= lsl(r21:20, r31)
+# CHECK: r17:16 -= lsl(r21:20,r31)
0x10 0xdf 0xd4 0xcb
-# CHECK: r17:16 += asr(r21:20, r31)
+# CHECK: r17:16 += asr(r21:20,r31)
0x50 0xdf 0xd4 0xcb
-# CHECK: r17:16 += lsr(r21:20, r31)
+# CHECK: r17:16 += lsr(r21:20,r31)
0x90 0xdf 0xd4 0xcb
-# CHECK: r17:16 += asl(r21:20, r31)
+# CHECK: r17:16 += asl(r21:20,r31)
0xd0 0xdf 0xd4 0xcb
-# CHECK: r17:16 += lsl(r21:20, r31)
+# CHECK: r17:16 += lsl(r21:20,r31)
0x11 0xdf 0x95 0xcc
-# CHECK: r17 -= asr(r21, r31)
+# CHECK: r17 -= asr(r21,r31)
0x51 0xdf 0x95 0xcc
-# CHECK: r17 -= lsr(r21, r31)
+# CHECK: r17 -= lsr(r21,r31)
0x91 0xdf 0x95 0xcc
-# CHECK: r17 -= asl(r21, r31)
+# CHECK: r17 -= asl(r21,r31)
0xd1 0xdf 0x95 0xcc
-# CHECK: r17 -= lsl(r21, r31)
+# CHECK: r17 -= lsl(r21,r31)
0x11 0xdf 0xd5 0xcc
-# CHECK: r17 += asr(r21, r31)
+# CHECK: r17 += asr(r21,r31)
0x51 0xdf 0xd5 0xcc
-# CHECK: r17 += lsr(r21, r31)
+# CHECK: r17 += lsr(r21,r31)
0x91 0xdf 0xd5 0xcc
-# CHECK: r17 += asl(r21, r31)
+# CHECK: r17 += asl(r21,r31)
0xd1 0xdf 0xd5 0xcc
-# CHECK: r17 += lsl(r21, r31)
+# CHECK: r17 += lsl(r21,r31)
# Shift by register and logical
0x10 0xdf 0x14 0xcb
-# CHECK: r17:16 |= asr(r21:20, r31)
+# CHECK: r17:16 |= asr(r21:20,r31)
0x50 0xdf 0x14 0xcb
-# CHECK: r17:16 |= lsr(r21:20, r31)
+# CHECK: r17:16 |= lsr(r21:20,r31)
0x90 0xdf 0x14 0xcb
-# CHECK: r17:16 |= asl(r21:20, r31)
+# CHECK: r17:16 |= asl(r21:20,r31)
0xd0 0xdf 0x14 0xcb
-# CHECK: r17:16 |= lsl(r21:20, r31)
+# CHECK: r17:16 |= lsl(r21:20,r31)
0x10 0xdf 0x54 0xcb
-# CHECK: r17:16 &= asr(r21:20, r31)
+# CHECK: r17:16 &= asr(r21:20,r31)
0x50 0xdf 0x54 0xcb
-# CHECK: r17:16 &= lsr(r21:20, r31)
+# CHECK: r17:16 &= lsr(r21:20,r31)
0x90 0xdf 0x54 0xcb
-# CHECK: r17:16 &= asl(r21:20, r31)
+# CHECK: r17:16 &= asl(r21:20,r31)
0xd0 0xdf 0x54 0xcb
-# CHECK: r17:16 &= lsl(r21:20, r31)
+# CHECK: r17:16 &= lsl(r21:20,r31)
0x10 0xdf 0x74 0xcb
-# CHECK: r17:16 ^= asr(r21:20, r31)
+# CHECK: r17:16 ^= asr(r21:20,r31)
0x50 0xdf 0x74 0xcb
-# CHECK: r17:16 ^= lsr(r21:20, r31)
+# CHECK: r17:16 ^= lsr(r21:20,r31)
0x90 0xdf 0x74 0xcb
-# CHECK: r17:16 ^= asl(r21:20, r31)
+# CHECK: r17:16 ^= asl(r21:20,r31)
0xd0 0xdf 0x74 0xcb
-# CHECK: r17:16 ^= lsl(r21:20, r31)
+# CHECK: r17:16 ^= lsl(r21:20,r31)
0x11 0xdf 0x15 0xcc
-# CHECK: r17 |= asr(r21, r31)
+# CHECK: r17 |= asr(r21,r31)
0x51 0xdf 0x15 0xcc
-# CHECK: r17 |= lsr(r21, r31)
+# CHECK: r17 |= lsr(r21,r31)
0x91 0xdf 0x15 0xcc
-# CHECK: r17 |= asl(r21, r31)
+# CHECK: r17 |= asl(r21,r31)
0xd1 0xdf 0x15 0xcc
-# CHECK: r17 |= lsl(r21, r31)
+# CHECK: r17 |= lsl(r21,r31)
0x11 0xdf 0x55 0xcc
-# CHECK: r17 &= asr(r21, r31)
+# CHECK: r17 &= asr(r21,r31)
0x51 0xdf 0x55 0xcc
-# CHECK: r17 &= lsr(r21, r31)
+# CHECK: r17 &= lsr(r21,r31)
0x91 0xdf 0x55 0xcc
-# CHECK: r17 &= asl(r21, r31)
+# CHECK: r17 &= asl(r21,r31)
0xd1 0xdf 0x55 0xcc
-# CHECK: r17 &= lsl(r21, r31)
+# CHECK: r17 &= lsl(r21,r31)
# Shift by register with saturation
0x11 0xdf 0x15 0xc6
-# CHECK: r17 = asr(r21, r31):sat
+# CHECK: r17 = asr(r21,r31):sat
0x91 0xdf 0x15 0xc6
-# CHECK: r17 = asl(r21, r31):sat
+# CHECK: r17 = asl(r21,r31):sat
# Vector shift halfwords by immediate
0x10 0xc5 0x94 0x80
-# CHECK: r17:16 = vasrh(r21:20, #5)
+# CHECK: r17:16 = vasrh(r21:20,#5)
0x30 0xc5 0x94 0x80
-# CHECK: r17:16 = vlsrh(r21:20, #5)
+# CHECK: r17:16 = vlsrh(r21:20,#5)
0x50 0xc5 0x94 0x80
-# CHECK: r17:16 = vaslh(r21:20, #5)
+# CHECK: r17:16 = vaslh(r21:20,#5)
# Vector arithmetic shift halfwords with round
0x10 0xc5 0x34 0x80
-# CHECK: r17:16 = vasrh(r21:20, #5):raw
+# CHECK: r17:16 = vasrh(r21:20,#5):raw
# Vector arithmetic shift halfwords with saturate and pack
0x91 0xc5 0x74 0x88
-# CHECK: r17 = vasrhub(r21:20, #5):raw
+# CHECK: r17 = vasrhub(r21:20,#5):raw
0xb1 0xc5 0x74 0x88
-# CHECK: r17 = vasrhub(r21:20, #5):sat
+# CHECK: r17 = vasrhub(r21:20,#5):sat
# Vector shift halfwords by register
0x10 0xdf 0x54 0xc3
-# CHECK: r17:16 = vasrh(r21:20, r31)
+# CHECK: r17:16 = vasrh(r21:20,r31)
0x50 0xdf 0x54 0xc3
-# CHECK: r17:16 = vlsrh(r21:20, r31)
+# CHECK: r17:16 = vlsrh(r21:20,r31)
0x90 0xdf 0x54 0xc3
-# CHECK: r17:16 = vaslh(r21:20, r31)
+# CHECK: r17:16 = vaslh(r21:20,r31)
0xd0 0xdf 0x54 0xc3
-# CHECK: r17:16 = vlslh(r21:20, r31)
+# CHECK: r17:16 = vlslh(r21:20,r31)
# Vector shift words by immediate
0x10 0xdf 0x54 0x80
-# CHECK: r17:16 = vasrw(r21:20, #31)
+# CHECK: r17:16 = vasrw(r21:20,#31)
0x30 0xdf 0x54 0x80
-# CHECK: r17:16 = vlsrw(r21:20, #31)
+# CHECK: r17:16 = vlsrw(r21:20,#31)
0x50 0xdf 0x54 0x80
-# CHECK: r17:16 = vaslw(r21:20, #31)
+# CHECK: r17:16 = vaslw(r21:20,#31)
# Vector shift words by register
0x10 0xdf 0x14 0xc3
-# CHECK: r17:16 = vasrw(r21:20, r31)
+# CHECK: r17:16 = vasrw(r21:20,r31)
0x50 0xdf 0x14 0xc3
-# CHECK: r17:16 = vlsrw(r21:20, r31)
+# CHECK: r17:16 = vlsrw(r21:20,r31)
0x90 0xdf 0x14 0xc3
-# CHECK: r17:16 = vaslw(r21:20, r31)
+# CHECK: r17:16 = vaslw(r21:20,r31)
0xd0 0xdf 0x14 0xc3
-# CHECK: r17:16 = vlslw(r21:20, r31)
+# CHECK: r17:16 = vlslw(r21:20,r31)
# Vector shift words with truncate and pack
0x51 0xdf 0xd4 0x88
-# CHECK: r17 = vasrw(r21:20, #31)
+# CHECK: r17 = vasrw(r21:20,#31)
0x51 0xdf 0x14 0xc5
-# CHECK: r17 = vasrw(r21:20, r31)
+# CHECK: r17 = vasrw(r21:20,r31)
Modified: llvm/trunk/test/MC/Hexagon/align.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Hexagon/align.s?rev=294753&r1=294752&r2=294753&view=diff
==============================================================================
--- llvm/trunk/test/MC/Hexagon/align.s (original)
+++ llvm/trunk/test/MC/Hexagon/align.s Fri Feb 10 09:33:13 2017
@@ -3,7 +3,7 @@
# Verify that the .align directive emits the proper insn packets.
{ r1 = sub(#1, r1) }
-# CHECK: 76414021 { r1 = sub(#1, r1)
+# CHECK: 76414021 { r1 = sub(#1,r1)
# CHECK-NEXT: 7f004000 nop
# CHECK-NEXT: 7f004000 nop
# CHECK-NEXT: 7f00c000 nop }
@@ -11,8 +11,8 @@
.align 16
{ r1 = sub(#1, r1)
r2 = sub(#1, r2) }
-# CHECK: 76414021 { r1 = sub(#1, r1)
-# CHECK-NEXT: 76424022 r2 = sub(#1, r2)
+# CHECK: 76414021 { r1 = sub(#1,r1)
+# CHECK-NEXT: 76424022 r2 = sub(#1,r2)
# CHECK-NEXT: 7f004000 nop
# CHECK-NEXT: 7f00c000 nop }
@@ -20,7 +20,7 @@
{ r1 = sub(#1, r1)
r2 = sub(#1, r2)
r3 = sub(#1, r3) }
-# CHECK: 76434023 r3 = sub(#1, r3)
+# CHECK: 76434023 r3 = sub(#1,r3)
# CHECK-NEXT: 7f00c000 nop }
.align 16
@@ -33,13 +33,13 @@
# CHECK: 9200c020 { r0 = vextract(v0,r0) }
r0 = vextract(v0, r0)
.align 128
-# CHECK: 76414021 { r1 = sub(#1, r1)
+# CHECK: 76414021 { r1 = sub(#1,r1)
# CHECK-NEXT: 7f00c000 nop }
{ r1 = sub(#1, r1) }
-#CHECK: { r1 = sub(#1, r1)
-#CHECK: r2 = sub(#1, r2)
-#CHECK: r3 = sub(#1, r3) }
+#CHECK: { r1 = sub(#1,r1)
+#CHECK: r2 = sub(#1,r2)
+#CHECK: r3 = sub(#1,r3) }
.falign
.align 8
{ r1 = sub(#1, r1)
@@ -47,14 +47,14 @@ r0 = vextract(v0, r0)
r3 = sub(#1, r3) }
# CHECK: { immext(#0)
-# CHECK: r0 = sub(##1, r0)
+# CHECK: r0 = sub(##1,r0)
# CHECK: immext(#0)
-# CHECK: r1 = sub(##1, r1) }
+# CHECK: r1 = sub(##1,r1) }
# CHECK: { nop
# CHECK: nop
# CHECK: nop }
-# CHECK: { r0 = sub(#1, r0) }
+# CHECK: { r0 = sub(#1,r0) }
{ r0 = sub (##1, r0)
r1 = sub (##1, r1) }
.align 16
-{ r0 = sub (#1, r0) }
\ No newline at end of file
+{ r0 = sub (#1, r0) }
More information about the llvm-commits
mailing list