[llvm] r294551 - SwiftCC: swifterror register cannot be as the base register
Hans Wennborg via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 9 08:57:54 PST 2017
Sounds good to me if Tim agrees.
Cheers,
Hans
On Thu, Feb 9, 2017 at 7:26 AM, Arnold Schwaighofer via llvm-commits
<llvm-commits at lists.llvm.org> wrote:
> Hi Hans, Tim
>
> And again, .. Can we merged this into the 4.0 branch?
>
> This only effects lowering if there is a swifterror attribute — i.e almost zero risk for code that does not use the swift calling convention.
>
>> On Feb 8, 2017, at 5:52 PM, Arnold Schwaighofer via llvm-commits <llvm-commits at lists.llvm.org> wrote:
>>
>> Author: arnolds
>> Date: Wed Feb 8 19:52:17 2017
>> New Revision: 294551
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=294551&view=rev
>> Log:
>> SwiftCC: swifterror register cannot be as the base register
>>
>> Functions that have a dynamic alloca require a base register which is defined to
>> be X19 on AArch64 and r6 on ARM. We have defined the swifterror register to be
>> the same register. Use a different callee save register for swifterror instead:
>>
>> X21 on AArch64
>> R8 on ARM
>>
>> rdar://30433803
>>
>> Modified:
>> llvm/trunk/lib/Target/AArch64/AArch64CallingConvention.td
>> llvm/trunk/lib/Target/ARM/ARMCallingConv.td
>> llvm/trunk/test/CodeGen/AArch64/swifterror.ll
>> llvm/trunk/test/CodeGen/ARM/swifterror.ll
>>
>> Modified: llvm/trunk/lib/Target/AArch64/AArch64CallingConvention.td
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64CallingConvention.td?rev=294551&r1=294550&r2=294551&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/AArch64/AArch64CallingConvention.td (original)
>> +++ llvm/trunk/lib/Target/AArch64/AArch64CallingConvention.td Wed Feb 8 19:52:17 2017
>> @@ -91,7 +91,7 @@ def RetCC_AArch64_AAPCS : CallingConv<[
>> CCIfType<[v2f32], CCBitConvertToType<v2i32>>,
>> CCIfType<[v2f64, v4f32], CCBitConvertToType<v2i64>>,
>>
>> - CCIfSwiftError<CCIfType<[i64], CCAssignToRegWithShadow<[X19], [W19]>>>,
>> + CCIfSwiftError<CCIfType<[i64], CCAssignToRegWithShadow<[X21], [W21]>>>,
>>
>> // Big endian vectors must be passed as if they were 1-element vectors so that
>> // their lanes are in a consistent order.
>> @@ -138,8 +138,8 @@ def CC_AArch64_DarwinPCS : CallingConv<[
>> // Pass SwiftSelf in a callee saved register.
>> CCIfSwiftSelf<CCIfType<[i64], CCAssignToRegWithShadow<[X20], [W20]>>>,
>>
>> - // A SwiftError is passed in X19.
>> - CCIfSwiftError<CCIfType<[i64], CCAssignToRegWithShadow<[X19], [W19]>>>,
>> + // A SwiftError is passed in X21.
>> + CCIfSwiftError<CCIfType<[i64], CCAssignToRegWithShadow<[X21], [W21]>>>,
>>
>> CCIfConsecutiveRegs<CCCustom<"CC_AArch64_Custom_Block">>,
>>
>> @@ -289,7 +289,7 @@ def CSR_AArch64_AAPCS : CalleeSavedRegs<
>> def CSR_AArch64_AAPCS_ThisReturn : CalleeSavedRegs<(add CSR_AArch64_AAPCS, X0)>;
>>
>> def CSR_AArch64_AAPCS_SwiftError
>> - : CalleeSavedRegs<(sub CSR_AArch64_AAPCS, X19)>;
>> + : CalleeSavedRegs<(sub CSR_AArch64_AAPCS, X21)>;
>>
>> // The function used by Darwin to obtain the address of a thread-local variable
>> // guarantees more than a normal AAPCS function. x16 and x17 are used on the
>>
>> Modified: llvm/trunk/lib/Target/ARM/ARMCallingConv.td
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCallingConv.td?rev=294551&r1=294550&r2=294551&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMCallingConv.td (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMCallingConv.td Wed Feb 8 19:52:17 2017
>> @@ -26,8 +26,8 @@ def CC_ARM_APCS : CallingConv<[
>> // Pass SwiftSelf in a callee saved register.
>> CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>,
>>
>> - // A SwiftError is passed in R6.
>> - CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R6]>>>,
>> + // A SwiftError is passed in R8.
>> + CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R8]>>>,
>>
>> // Handle all vector types as either f64 or v2f64.
>> CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
>> @@ -51,8 +51,8 @@ def RetCC_ARM_APCS : CallingConv<[
>> // Pass SwiftSelf in a callee saved register.
>> CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>,
>>
>> - // A SwiftError is returned in R6.
>> - CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R6]>>>,
>> + // A SwiftError is returned in R8.
>> + CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R8]>>>,
>>
>> // Handle all vector types as either f64 or v2f64.
>> CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
>> @@ -166,8 +166,8 @@ def CC_ARM_AAPCS : CallingConv<[
>> // Pass SwiftSelf in a callee saved register.
>> CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>,
>>
>> - // A SwiftError is passed in R6.
>> - CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R6]>>>,
>> + // A SwiftError is passed in R8.
>> + CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R8]>>>,
>>
>> CCIfType<[f64, v2f64], CCCustom<"CC_ARM_AAPCS_Custom_f64">>,
>> CCIfType<[f32], CCBitConvertToType<i32>>,
>> @@ -182,8 +182,8 @@ def RetCC_ARM_AAPCS : CallingConv<[
>> // Pass SwiftSelf in a callee saved register.
>> CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>,
>>
>> - // A SwiftError is returned in R6.
>> - CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R6]>>>,
>> + // A SwiftError is returned in R8.
>> + CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R8]>>>,
>>
>> CCIfType<[f64, v2f64], CCCustom<"RetCC_ARM_AAPCS_Custom_f64">>,
>> CCIfType<[f32], CCBitConvertToType<i32>>,
>> @@ -206,8 +206,8 @@ def CC_ARM_AAPCS_VFP : CallingConv<[
>> // Pass SwiftSelf in a callee saved register.
>> CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>,
>>
>> - // A SwiftError is passed in R6.
>> - CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R6]>>>,
>> + // A SwiftError is passed in R8.
>> + CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R8]>>>,
>>
>> // HFAs are passed in a contiguous block of registers, or on the stack
>> CCIfConsecutiveRegs<CCCustom<"CC_ARM_AAPCS_Custom_Aggregate">>,
>> @@ -227,8 +227,8 @@ def RetCC_ARM_AAPCS_VFP : CallingConv<[
>> // Pass SwiftSelf in a callee saved register.
>> CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>,
>>
>> - // A SwiftError is returned in R6.
>> - CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R6]>>>,
>> + // A SwiftError is returned in R8.
>> + CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R8]>>>,
>>
>> CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
>> CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
>> @@ -267,8 +267,8 @@ def CSR_AAPCS_ThisReturn : CalleeSavedRe
>> // Also save R7-R4 first to match the stack frame fixed spill areas.
>> def CSR_iOS : CalleeSavedRegs<(add LR, R7, R6, R5, R4, (sub CSR_AAPCS, R9))>;
>>
>> -// R6 is used to pass swifterror, remove it from CSR.
>> -def CSR_iOS_SwiftError : CalleeSavedRegs<(sub CSR_iOS, R6)>;
>> +// R8 is used to pass swifterror, remove it from CSR.
>> +def CSR_iOS_SwiftError : CalleeSavedRegs<(sub CSR_iOS, R8)>;
>>
>> def CSR_iOS_ThisReturn : CalleeSavedRegs<(add LR, R7, R6, R5, R4,
>> (sub CSR_AAPCS_ThisReturn, R9))>;
>>
>> Modified: llvm/trunk/test/CodeGen/AArch64/swifterror.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/swifterror.ll?rev=294551&r1=294550&r2=294551&view=diff
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/AArch64/swifterror.ll (original)
>> +++ llvm/trunk/test/CodeGen/AArch64/swifterror.ll Wed Feb 8 19:52:17 2017
>> @@ -13,18 +13,18 @@ define float @foo(%swift_error** swifter
>> ; CHECK-APPLE: malloc
>> ; CHECK-APPLE: orr [[ID:w[0-9]+]], wzr, #0x1
>> ; CHECK-APPLE: strb [[ID]], [x0, #8]
>> -; CHECK-APPLE: mov x19, x0
>> -; CHECK-APPLE-NOT: x19
>> +; CHECK-APPLE: mov x21, x0
>> +; CHECK-APPLE-NOT: x21
>>
>> ; CHECK-O0-LABEL: foo:
>> ; CHECK-O0: orr w{{.*}}, wzr, #0x10
>> ; CHECK-O0: malloc
>> -; CHECK-O0: mov x19, x0
>> -; CHECK-O0-NOT: x19
>> +; CHECK-O0: mov x21, x0
>> +; CHECK-O0-NOT: x21
>> ; CHECK-O0: orr [[ID:w[0-9]+]], wzr, #0x1
>> -; CHECK-O0-NOT: x19
>> +; CHECK-O0-NOT: x21
>> ; CHECK-O0: strb [[ID]], [x0, #8]
>> -; CHECK-O0-NOT: x19
>> +; CHECK-O0-NOT: x21
>> entry:
>> %call = call i8* @malloc(i64 16)
>> %call.0 = bitcast i8* %call to %swift_error*
>> @@ -38,20 +38,20 @@ entry:
>> define float @caller(i8* %error_ref) {
>> ; CHECK-APPLE-LABEL: caller:
>> ; CHECK-APPLE: mov [[ID:x[0-9]+]], x0
>> -; CHECK-APPLE: mov x19, xzr
>> +; CHECK-APPLE: mov x21, xzr
>> ; CHECK-APPLE: bl {{.*}}foo
>> -; CHECK-APPLE: cbnz x19
>> +; CHECK-APPLE: cbnz x21
>> ; Access part of the error object and save it to error_ref
>> -; CHECK-APPLE: ldrb [[CODE:w[0-9]+]], [x19, #8]
>> +; CHECK-APPLE: ldrb [[CODE:w[0-9]+]], [x21, #8]
>> ; CHECK-APPLE: strb [[CODE]], [{{.*}}[[ID]]]
>> -; CHECK-APPLE: mov x0, x19
>> +; CHECK-APPLE: mov x0, x21
>> ; CHECK-APPLE: bl {{.*}}free
>>
>> ; CHECK-O0-LABEL: caller:
>> -; CHECK-O0: mov x19
>> +; CHECK-O0: mov x21
>> ; CHECK-O0: bl {{.*}}foo
>> -; CHECK-O0: mov [[ID:x[0-9]+]], x19
>> -; CHECK-O0: cbnz x19
>> +; CHECK-O0: mov [[ID:x[0-9]+]], x21
>> +; CHECK-O0: cbnz x21
>> entry:
>> %error_ptr_ref = alloca swifterror %swift_error*
>> store %swift_error* null, %swift_error** %error_ptr_ref
>> @@ -75,22 +75,22 @@ define float @caller2(i8* %error_ref) {
>> ; CHECK-APPLE-LABEL: caller2:
>> ; CHECK-APPLE: mov [[ID:x[0-9]+]], x0
>> ; CHECK-APPLE: fmov [[CMP:s[0-9]+]], #1.0
>> -; CHECK-APPLE: mov x19, xzr
>> +; CHECK-APPLE: mov x21, xzr
>> ; CHECK-APPLE: bl {{.*}}foo
>> -; CHECK-APPLE: cbnz x19
>> +; CHECK-APPLE: cbnz x21
>> ; CHECK-APPLE: fcmp s0, [[CMP]]
>> ; CHECK-APPLE: b.le
>> ; Access part of the error object and save it to error_ref
>> -; CHECK-APPLE: ldrb [[CODE:w[0-9]+]], [x19, #8]
>> +; CHECK-APPLE: ldrb [[CODE:w[0-9]+]], [x21, #8]
>> ; CHECK-APPLE: strb [[CODE]], [{{.*}}[[ID]]]
>> -; CHECK-APPLE: mov x0, x19
>> +; CHECK-APPLE: mov x0, x21
>> ; CHECK-APPLE: bl {{.*}}free
>>
>> ; CHECK-O0-LABEL: caller2:
>> -; CHECK-O0: mov x19
>> +; CHECK-O0: mov x21
>> ; CHECK-O0: bl {{.*}}foo
>> -; CHECK-O0: mov [[ID:x[0-9]+]], x19
>> -; CHECK-O0: cbnz x19
>> +; CHECK-O0: mov [[ID:x[0-9]+]], x21
>> +; CHECK-O0: cbnz x21
>> entry:
>> %error_ptr_ref = alloca swifterror %swift_error*
>> br label %bb_loop
>> @@ -123,24 +123,24 @@ define float @foo_if(%swift_error** swif
>> ; CHECK-APPLE: malloc
>> ; CHECK-APPLE: orr [[ID:w[0-9]+]], wzr, #0x1
>> ; CHECK-APPLE: strb [[ID]], [x0, #8]
>> -; CHECK-APPLE: mov x19, x0
>> -; CHECK-APPLE-NOT: x19
>> +; CHECK-APPLE: mov x21, x0
>> +; CHECK-APPLE-NOT: x21
>> ; CHECK-APPLE: ret
>>
>> ; CHECK-O0-LABEL: foo_if:
>> -; spill x19
>> -; CHECK-O0: str x19, [sp, [[SLOT:#[0-9]+]]]
>> +; spill x21
>> +; CHECK-O0: str x21, [sp, [[SLOT:#[0-9]+]]]
>> ; CHECK-O0: cbz w0
>> ; CHECK-O0: orr w{{.*}}, wzr, #0x10
>> ; CHECK-O0: malloc
>> ; CHECK-O0: mov [[ID:x[0-9]+]], x0
>> ; CHECK-O0: orr [[ID2:w[0-9]+]], wzr, #0x1
>> ; CHECK-O0: strb [[ID2]], [x0, #8]
>> -; CHECK-O0: mov x19, [[ID]]
>> +; CHECK-O0: mov x21, [[ID]]
>> ; CHECK-O0: ret
>> ; reload from stack
>> ; CHECK-O0: ldr [[ID3:x[0-9]+]], [sp, [[SLOT]]]
>> -; CHECK-O0: mov x19, [[ID3]]
>> +; CHECK-O0: mov x21, [[ID3]]
>> ; CHECK-O0: ret
>> entry:
>> %cond = icmp ne i32 %cc, 0
>> @@ -162,19 +162,19 @@ normal:
>> ; under a certain condition inside a loop.
>> define float @foo_loop(%swift_error** swifterror %error_ptr_ref, i32 %cc, float %cc2) {
>> ; CHECK-APPLE-LABEL: foo_loop:
>> -; CHECK-APPLE: mov x0, x19
>> +; CHECK-APPLE: mov x0, x21
>> ; CHECK-APPLE: cbz
>> ; CHECK-APPLE: orr w0, wzr, #0x10
>> ; CHECK-APPLE: malloc
>> ; CHECK-APPLE: strb w{{.*}}, [x0, #8]
>> ; CHECK-APPLE: fcmp
>> ; CHECK-APPLE: b.le
>> -; CHECK-APPLE: mov x19, x0
>> +; CHECK-APPLE: mov x21, x0
>> ; CHECK-APPLE: ret
>>
>> ; CHECK-O0-LABEL: foo_loop:
>> -; spill x19
>> -; CHECK-O0: str x19, [sp, [[SLOT:#[0-9]+]]]
>> +; spill x21
>> +; CHECK-O0: str x21, [sp, [[SLOT:#[0-9]+]]]
>> ; CHECK-O0: b [[BB1:[A-Za-z0-9_]*]]
>> ; CHECK-O0: [[BB1]]:
>> ; CHECK-O0: ldr x0, [sp, [[SLOT]]]
>> @@ -193,7 +193,7 @@ define float @foo_loop(%swift_error** sw
>> ; CHECK-O0: b.le [[BB1]]
>> ; reload from stack
>> ; CHECK-O0: ldr [[ID3:x[0-9]+]], [sp]
>> -; CHECK-O0: mov x19, [[ID3]]
>> +; CHECK-O0: mov x21, [[ID3]]
>> ; CHECK-O0: ret
>> entry:
>> br label %bb_loop
>> @@ -229,23 +229,23 @@ define void @foo_sret(%struct.S* sret %a
>> ; CHECK-APPLE: orr [[ID:w[0-9]+]], wzr, #0x1
>> ; CHECK-APPLE: strb [[ID]], [x0, #8]
>> ; CHECK-APPLE: str w{{.*}}, [{{.*}}[[SRET]], #4]
>> -; CHECK-APPLE: mov x19, x0
>> -; CHECK-APPLE-NOT: x19
>> +; CHECK-APPLE: mov x21, x0
>> +; CHECK-APPLE-NOT: x21
>>
>> ; CHECK-O0-LABEL: foo_sret:
>> ; CHECK-O0: orr w{{.*}}, wzr, #0x10
>> ; spill x8
>> ; CHECK-O0-DAG: str x8
>> -; spill x19
>> -; CHECK-O0-DAG: str x19
>> +; spill x21
>> +; CHECK-O0-DAG: str x21
>> ; CHECK-O0: malloc
>> ; CHECK-O0: orr [[ID:w[0-9]+]], wzr, #0x1
>> ; CHECK-O0: strb [[ID]], [x0, #8]
>> ; reload from stack
>> ; CHECK-O0: ldr [[SRET:x[0-9]+]]
>> ; CHECK-O0: str w{{.*}}, [{{.*}}[[SRET]], #4]
>> -; CHECK-O0: mov x19
>> -; CHECK-O0-NOT: x19
>> +; CHECK-O0: mov x21
>> +; CHECK-O0-NOT: x21
>> entry:
>> %call = call i8* @malloc(i64 16)
>> %call.0 = bitcast i8* %call to %swift_error*
>> @@ -261,22 +261,22 @@ entry:
>> define float @caller3(i8* %error_ref) {
>> ; CHECK-APPLE-LABEL: caller3:
>> ; CHECK-APPLE: mov [[ID:x[0-9]+]], x0
>> -; CHECK-APPLE: mov x19, xzr
>> +; CHECK-APPLE: mov x21, xzr
>> ; CHECK-APPLE: bl {{.*}}foo_sret
>> -; CHECK-APPLE: cbnz x19
>> +; CHECK-APPLE: cbnz x21
>> ; Access part of the error object and save it to error_ref
>> -; CHECK-APPLE: ldrb [[CODE:w[0-9]+]], [x19, #8]
>> +; CHECK-APPLE: ldrb [[CODE:w[0-9]+]], [x21, #8]
>> ; CHECK-APPLE: strb [[CODE]], [{{.*}}[[ID]]]
>> -; CHECK-APPLE: mov x0, x19
>> +; CHECK-APPLE: mov x0, x21
>> ; CHECK-APPLE: bl {{.*}}free
>>
>> ; CHECK-O0-LABEL: caller3:
>> ; spill x0
>> ; CHECK-O0: str x0
>> -; CHECK-O0: mov x19
>> +; CHECK-O0: mov x21
>> ; CHECK-O0: bl {{.*}}foo_sret
>> -; CHECK-O0: mov [[ID2:x[0-9]+]], x19
>> -; CHECK-O0: cbnz [[ID2]]
>> +; CHECK-O0: mov [[ID2:x[0-9]+]], x21
>> +; CHECK-O0: cbnz x21
>> ; Access part of the error object and save it to error_ref
>> ; reload from stack
>> ; CHECK-O0: ldrb [[CODE:w[0-9]+]]
>> @@ -323,8 +323,8 @@ define float @foo_vararg(%swift_error**
>> ; Third vararg
>> ; CHECK-APPLE: ldr {{w[0-9]+}}, [{{x[0-9]+}}]
>>
>> -; CHECK-APPLE: mov x19, x0
>> -; CHECK-APPLE-NOT: x19
>> +; CHECK-APPLE: mov x21, x0
>> +; CHECK-APPLE-NOT: x21
>> entry:
>> %call = call i8* @malloc(i64 16)
>> %call.0 = bitcast i8* %call to %swift_error*
>> @@ -356,13 +356,13 @@ define float @caller4(i8* %error_ref) {
>> ; CHECK-APPLE: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #8]
>> ; CHECK-APPLE: str {{x[0-9]+}}, [sp]
>>
>> -; CHECK-APPLE: mov x19, xzr
>> +; CHECK-APPLE: mov x21, xzr
>> ; CHECK-APPLE: bl {{.*}}foo_vararg
>> -; CHECK-APPLE: cbnz x19
>> +; CHECK-APPLE: cbnz x21
>> ; Access part of the error object and save it to error_ref
>> -; CHECK-APPLE: ldrb [[CODE:w[0-9]+]], [x19, #8]
>> +; CHECK-APPLE: ldrb [[CODE:w[0-9]+]], [x21, #8]
>> ; CHECK-APPLE: strb [[CODE]], [{{.*}}[[ID]]]
>> -; CHECK-APPLE: mov x0, x19
>> +; CHECK-APPLE: mov x0, x21
>> ; CHECK-APPLE: bl {{.*}}free
>> entry:
>> %error_ptr_ref = alloca swifterror %swift_error*
>> @@ -407,29 +407,29 @@ entry:
>> }
>>
>> ; CHECK-APPLE-LABEL: swifterror_clobber
>> -; CHECK-APPLE: mov [[REG:x[0-9]+]], x19
>> +; CHECK-APPLE: mov [[REG:x[0-9]+]], x21
>> ; CHECK-APPLE: nop
>> -; CHECK-APPLE: mov x19, [[REG]]
>> +; CHECK-APPLE: mov x21, [[REG]]
>> define swiftcc void @swifterror_clobber(%swift_error** nocapture swifterror %err) {
>> - call void asm sideeffect "nop", "~{x19}"()
>> + call void asm sideeffect "nop", "~{x21}"()
>> ret void
>> }
>>
>> ; CHECK-APPLE-LABEL: swifterror_reg_clobber
>> -; CHECK-APPLE: stp {{.*}}x19
>> +; CHECK-APPLE: stp {{.*}}x21
>> ; CHECK-APPLE: nop
>> -; CHECK-APPLE: ldp {{.*}}x19
>> +; CHECK-APPLE: ldp {{.*}}x21
>> define swiftcc void @swifterror_reg_clobber(%swift_error** nocapture %err) {
>> - call void asm sideeffect "nop", "~{x19}"()
>> + call void asm sideeffect "nop", "~{x21}"()
>> ret void
>> }
>> ; CHECK-APPLE-LABEL: params_in_reg
>> ; Save callee saved registers and swifterror since it will be clobbered by the first call to params_in_reg2.
>> -; CHECK-APPLE: stp x19, x28, [sp
>> +; CHECK-APPLE: stp x21, x28, [sp
>> ; CHECK-APPLE: stp x27, x26, [sp
>> ; CHECK-APPLE: stp x25, x24, [sp
>> ; CHECK-APPLE: stp x23, x22, [sp
>> -; CHECK-APPLE: stp x21, x20, [sp
>> +; CHECK-APPLE: stp x20, x19, [sp
>> ; CHECK-APPLE: stp x29, x30, [sp
>> ; CHECK-APPLE: str x20, [sp
>> ; Store argument registers.
>> @@ -439,7 +439,7 @@ define swiftcc void @swifterror_reg_clob
>> ; CHECK-APPLE: mov x26, x4
>> ; CHECK-APPLE: mov x27, x3
>> ; CHECK-APPLE: mov x28, x2
>> -; CHECK-APPLE: mov x21, x1
>> +; CHECK-APPLE: mov x19, x1
>> ; CHECK-APPLE: mov x22, x0
>> ; Setup call.
>> ; CHECK-APPLE: orr w0, wzr, #0x1
>> @@ -451,11 +451,11 @@ define swiftcc void @swifterror_reg_clob
>> ; CHECK-APPLE: orr w6, wzr, #0x7
>> ; CHECK-APPLE: orr w7, wzr, #0x8
>> ; CHECK-APPLE: mov x20, xzr
>> -; CHECK-APPLE: mov x19, xzr
>> +; CHECK-APPLE: mov x21, xzr
>> ; CHECK-APPLE: bl _params_in_reg2
>> ; Restore original arguments for next call.
>> ; CHECK-APPLE: mov x0, x22
>> -; CHECK-APPLE: mov x1, x21
>> +; CHECK-APPLE: mov x1, x19
>> ; CHECK-APPLE: mov x2, x28
>> ; CHECK-APPLE: mov x3, x27
>> ; CHECK-APPLE: mov x4, x26
>> @@ -463,22 +463,22 @@ define swiftcc void @swifterror_reg_clob
>> ; CHECK-APPLE: mov x6, x24
>> ; CHECK-APPLE: mov x7, x23
>> ; Restore original swiftself argument and swifterror %err.
>> -; CHECK-APPLE: ldp x20, x19, [sp
>> +; CHECK-APPLE: ldp x20, x21, [sp
>> ; CHECK-APPLE: bl _params_in_reg2
>> -; Restore calle save registers but don't clober swifterror x19.
>> -; CHECK-APPLE-NOT: x19
>> +; Restore calle save registers but don't clober swifterror x21.
>> +; CHECK-APPLE-NOT: x21
>> ; CHECK-APPLE: ldp x29, x30, [sp
>> -; CHECK-APPLE-NOT: x19
>> -; CHECK-APPLE: ldp x21, x20, [sp
>> -; CHECK-APPLE-NOT: x19
>> +; CHECK-APPLE-NOT: x21
>> +; CHECK-APPLE: ldp x20, x19, [sp
>> +; CHECK-APPLE-NOT: x21
>> ; CHECK-APPLE: ldp x23, x22, [sp
>> -; CHECK-APPLE-NOT: x19
>> +; CHECK-APPLE-NOT: x21
>> ; CHECK-APPLE: ldp x25, x24, [sp
>> -; CHECK-APPLE-NOT: x19
>> +; CHECK-APPLE-NOT: x21
>> ; CHECK-APPLE: ldp x27, x26, [sp
>> -; CHECK-APPLE-NOT: x19
>> +; CHECK-APPLE-NOT: x21
>> ; CHECK-APPLE: ldr x28, [sp
>> -; CHECK-APPLE-NOT: x19
>> +; CHECK-APPLE-NOT: x21
>> ; CHECK-APPLE: ret
>> define swiftcc void @params_in_reg(i64, i64, i64, i64, i64, i64, i64, i64, i8* swiftself, %swift_error** nocapture swifterror %err) {
>> %error_ptr_ref = alloca swifterror %swift_error*, align 8
>> @@ -495,17 +495,17 @@ declare swiftcc void @params_in_reg2(i64
>> ; CHECK-APPLE: stp x27, x26, [sp
>> ; CHECK-APPLE: stp x25, x24, [sp
>> ; CHECK-APPLE: stp x23, x22, [sp
>> -; CHECK-APPLE: stp x21, x20, [sp
>> +; CHECK-APPLE: stp x20, x19, [sp
>> ; CHECK-APPLE: stp x29, x30, [sp
>> ; Save original arguments.
>> -; CHECK-APPLE: mov x23, x19
>> +; CHECK-APPLE: mov x23, x21
>> ; CHECK-APPLE: str x7, [sp, #16]
>> ; CHECK-APPLE: mov x24, x6
>> ; CHECK-APPLE: mov x25, x5
>> ; CHECK-APPLE: mov x26, x4
>> ; CHECK-APPLE: mov x27, x3
>> ; CHECK-APPLE: mov x28, x2
>> -; CHECK-APPLE: mov x21, x1
>> +; CHECK-APPLE: mov x19, x1
>> ; CHECK-APPLE: mov x22, x0
>> ; Setup call arguments.
>> ; CHECK-APPLE: orr w0, wzr, #0x1
>> @@ -517,23 +517,23 @@ declare swiftcc void @params_in_reg2(i64
>> ; CHECK-APPLE: orr w6, wzr, #0x7
>> ; CHECK-APPLE: orr w7, wzr, #0x8
>> ; CHECK-APPLE: mov x20, xzr
>> -; CHECK-APPLE: mov x19, xzr
>> +; CHECK-APPLE: mov x21, xzr
>> ; CHECK-APPLE: bl _params_in_reg2
>> ; Store swifterror %error_ptr_ref.
>> -; CHECK-APPLE: str x19, [sp, #8]
>> +; CHECK-APPLE: str x21, [sp, #8]
>> ; Setup call arguments from original arguments.
>> ; CHECK-APPLE: mov x0, x22
>> -; CHECK-APPLE: mov x1, x21
>> +; CHECK-APPLE: mov x1, x19
>> ; CHECK-APPLE: mov x2, x28
>> ; CHECK-APPLE: mov x3, x27
>> ; CHECK-APPLE: mov x4, x26
>> ; CHECK-APPLE: mov x5, x25
>> ; CHECK-APPLE: mov x6, x24
>> ; CHECK-APPLE: ldp x7, x20, [sp, #16]
>> -; CHECK-APPLE: mov x19, x23
>> +; CHECK-APPLE: mov x21, x23
>> ; CHECK-APPLE: bl _params_and_return_in_reg2
>> ; Store return values.
>> -; CHECK-APPLE: mov x21, x0
>> +; CHECK-APPLE: mov x19, x0
>> ; CHECK-APPLE: mov x22, x1
>> ; CHECK-APPLE: mov x24, x2
>> ; CHECK-APPLE: mov x25, x3
>> @@ -542,7 +542,7 @@ declare swiftcc void @params_in_reg2(i64
>> ; CHECK-APPLE: mov x28, x6
>> ; CHECK-APPLE: mov x23, x7
>> ; Save swifterror %err.
>> -; CHECK-APPLE: str x19, [sp, #24]
>> +; CHECK-APPLE: str x21, [sp, #24]
>> ; Setup call.
>> ; CHECK-APPLE: orr w0, wzr, #0x1
>> ; CHECK-APPLE: orr w1, wzr, #0x2
>> @@ -554,10 +554,10 @@ declare swiftcc void @params_in_reg2(i64
>> ; CHECK-APPLE: orr w7, wzr, #0x8
>> ; CHECK-APPLE: mov x20, xzr
>> ; ... setup call with swiferror %error_ptr_ref.
>> -; CHECK-APPLE: ldr x19, [sp, #8]
>> +; CHECK-APPLE: ldr x21, [sp, #8]
>> ; CHECK-APPLE: bl _params_in_reg2
>> ; Restore return values for return from this function.
>> -; CHECK-APPLE: mov x0, x21
>> +; CHECK-APPLE: mov x0, x19
>> ; CHECK-APPLE: mov x1, x22
>> ; CHECK-APPLE: mov x2, x24
>> ; CHECK-APPLE: mov x3, x25
>> @@ -566,9 +566,9 @@ declare swiftcc void @params_in_reg2(i64
>> ; CHECK-APPLE: mov x6, x28
>> ; CHECK-APPLE: mov x7, x23
>> ; Restore swifterror %err and callee save registers.
>> -; CHECK-APPLE: ldp x19, x28, [sp, #24
>> +; CHECK-APPLE: ldp x21, x28, [sp, #24
>> ; CHECK-APPLE: ldp x29, x30, [sp
>> -; CHECK-APPLE: ldp x21, x20, [sp
>> +; CHECK-APPLE: ldp x20, x19, [sp
>> ; CHECK-APPLE: ldp x23, x22, [sp
>> ; CHECK-APPLE: ldp x25, x24, [sp
>> ; CHECK-APPLE: ldp x27, x26, [sp
>>
>> Modified: llvm/trunk/test/CodeGen/ARM/swifterror.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/swifterror.ll?rev=294551&r1=294550&r2=294551&view=diff
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/ARM/swifterror.ll (original)
>> +++ llvm/trunk/test/CodeGen/ARM/swifterror.ll Wed Feb 8 19:52:17 2017
>> @@ -13,7 +13,7 @@ define float @foo(%swift_error** swifter
>> ; CHECK-APPLE: mov r0, #16
>> ; CHECK-APPLE: malloc
>> ; CHECK-APPLE-DAG: mov [[ID:r[0-9]+]], #1
>> -; CHECK-APPLE-DAG: mov r6, r{{.*}}
>> +; CHECK-APPLE-DAG: mov r8, r{{.*}}
>> ; CHECK-APPLE-DAG: strb [[ID]], [r{{.*}}, #8]
>>
>> ; CHECK-O0-LABEL: foo:
>> @@ -22,7 +22,7 @@ define float @foo(%swift_error** swifter
>> ; CHECK-O0: mov [[ID2:r[0-9]+]], r0
>> ; CHECK-O0: mov [[ID:r[0-9]+]], #1
>> ; CHECK-O0: strb [[ID]], [r0, #8]
>> -; CHECK-O0: mov r6, [[ID2]]
>> +; CHECK-O0: mov r8, [[ID2]]
>> entry:
>> %call = call i8* @malloc(i64 16)
>> %call.0 = bitcast i8* %call to %swift_error*
>> @@ -36,21 +36,21 @@ entry:
>> define float @caller(i8* %error_ref) {
>> ; CHECK-APPLE-LABEL: caller:
>> ; CHECK-APPLE-DAG: mov [[ID:r[0-9]+]], r0
>> -; CHECK-APPLE-DAG: mov r6, #0
>> +; CHECK-APPLE-DAG: mov r8, #0
>> ; CHECK-APPLE: bl {{.*}}foo
>> -; CHECK-APPLE: cmp r6, #0
>> +; CHECK-APPLE: cmp r8, #0
>> ; Access part of the error object and save it to error_ref
>> -; CHECK-APPLE: ldrbeq [[CODE:r[0-9]+]], [r6, #8]
>> +; CHECK-APPLE: ldrbeq [[CODE:r[0-9]+]], [r8, #8]
>> ; CHECK-APPLE: strbeq [[CODE]], [{{.*}}[[ID]]]
>> -; CHECK-APPLE: mov r0, r6
>> +; CHECK-APPLE: mov r0, r8
>> ; CHECK-APPLE: bl {{.*}}free
>>
>> ; CHECK-O0-LABEL: caller:
>> ; spill r0
>> -; CHECK-O0-DAG: mov r6, #0
>> +; CHECK-O0-DAG: mov r8, #0
>> ; CHECK-O0-DAG: str r0, [sp, [[SLOT:#[0-9]+]]
>> ; CHECK-O0: bl {{.*}}foo
>> -; CHECK-O0: mov [[TMP:r[0-9]+]], r6
>> +; CHECK-O0: mov [[TMP:r[0-9]+]], r8
>> ; CHECK-O0: str [[TMP]], [sp]
>> ; CHECK-O0: bne
>> ; CHECK-O0: ldrb [[CODE:r[0-9]+]], [r0, #8]
>> @@ -81,22 +81,22 @@ handler:
>> define float @caller2(i8* %error_ref) {
>> ; CHECK-APPLE-LABEL: caller2:
>> ; CHECK-APPLE-DAG: mov [[ID:r[0-9]+]], r0
>> -; CHECK-APPLE-DAG: mov r6, #0
>> +; CHECK-APPLE-DAG: mov r8, #0
>> ; CHECK-APPLE: bl {{.*}}foo
>> -; CHECK-APPLE: cmp r6, #0
>> +; CHECK-APPLE: cmp r8, #0
>> ; CHECK-APPLE: bne
>> ; Access part of the error object and save it to error_ref
>> -; CHECK-APPLE: ldrb [[CODE:r[0-9]+]], [r6, #8]
>> +; CHECK-APPLE: ldrb [[CODE:r[0-9]+]], [r8, #8]
>> ; CHECK-APPLE: strb [[CODE]], [{{.*}}[[ID]]]
>> -; CHECK-APPLE: mov r0, r6
>> +; CHECK-APPLE: mov r0, r8
>> ; CHECK-APPLE: bl {{.*}}free
>>
>> ; CHECK-O0-LABEL: caller2:
>> ; spill r0
>> ; CHECK-O0-DAG: str r0,
>> -; CHECK-O0-DAG: mov r6, #0
>> +; CHECK-O0-DAG: mov r8, #0
>> ; CHECK-O0: bl {{.*}}foo
>> -; CHECK-O0: mov r{{.*}}, r6
>> +; CHECK-O0: mov r{{.*}}, r8
>> ; CHECK-O0: str r0, [sp]
>> ; CHECK-O0: bne
>> ; CHECK-O0: ble
>> @@ -138,22 +138,22 @@ define float @foo_if(%swift_error** swif
>> ; CHECK-APPLE: mov r0, #16
>> ; CHECK-APPLE: malloc
>> ; CHECK-APPLE: mov [[ID:r[0-9]+]], #1
>> -; CHECK-APPLE-DAG: mov r6, r{{.*}}
>> +; CHECK-APPLE-DAG: mov r8, r{{.*}}
>> ; CHECK-APPLE-DAG: strb [[ID]], [r{{.*}}, #8]
>>
>> ; CHECK-O0-LABEL: foo_if:
>> ; CHECK-O0: cmp r0, #0
>> ; spill to stack
>> -; CHECK-O0: str r6
>> +; CHECK-O0: str r8
>> ; CHECK-O0: beq
>> ; CHECK-O0: mov r0, #16
>> ; CHECK-O0: malloc
>> ; CHECK-O0: mov [[ID:r[0-9]+]], r0
>> ; CHECK-O0: mov [[ID2:[a-z0-9]+]], #1
>> ; CHECK-O0: strb [[ID2]], [r0, #8]
>> -; CHECK-O0: mov r6, [[ID]]
>> +; CHECK-O0: mov r8, [[ID]]
>> ; reload from stack
>> -; CHECK-O0: ldr r6
>> +; CHECK-O0: ldr r8
>> entry:
>> %cond = icmp ne i32 %cc, 0
>> br i1 %cond, label %gen_error, label %normal
>> @@ -176,17 +176,17 @@ define float @foo_loop(%swift_error** sw
>> ; CHECK-APPLE-LABEL: foo_loop:
>> ; CHECK-APPLE: mov [[CODE:r[0-9]+]], r0
>> ; swifterror is kept in a register
>> -; CHECK-APPLE: mov [[ID:r[0-9]+]], r6
>> +; CHECK-APPLE: mov [[ID:r[0-9]+]], r8
>> ; CHECK-APPLE: cmp [[CODE]], #0
>> ; CHECK-APPLE: beq
>> ; CHECK-APPLE: mov r0, #16
>> ; CHECK-APPLE: malloc
>> ; CHECK-APPLE: strb r{{.*}}, [{{.*}}[[ID]], #8]
>> ; CHECK-APPLE: ble
>> -; CHECK-APPLE: mov r6, [[ID]]
>> +; CHECK-APPLE: mov r8, [[ID]]
>>
>> ; CHECK-O0-LABEL: foo_loop:
>> -; CHECK-O0: mov r{{.*}}, r6
>> +; CHECK-O0: mov r{{.*}}, r8
>> ; CHECK-O0: cmp r{{.*}}, #0
>> ; CHECK-O0: beq
>> ; CHECK-O0-DAG: movw r{{.*}}, #1
>> @@ -200,7 +200,7 @@ define float @foo_loop(%swift_error** sw
>> ; CHECK-O0: vcmpe
>> ; CHECK-O0: ble
>> ; reload from stack
>> -; CHECK-O0: ldr r6
>> +; CHECK-O0: ldr r8
>> entry:
>> br label %bb_loop
>>
>> @@ -231,7 +231,7 @@ define void @foo_sret(%struct.S* sret %a
>> ; CHECK-APPLE: mov r0, #16
>> ; CHECK-APPLE: malloc
>> ; CHECK-APPLE: mov [[REG:r[0-9]+]], #1
>> -; CHECK-APPLE-DAG: mov r6, r0
>> +; CHECK-APPLE-DAG: mov r8, r0
>> ; CHECK-APPLE-DAG: strb [[REG]], [r0, #8]
>> ; CHECK-APPLE-DAG: str r{{.*}}, [{{.*}}[[SRET]], #4]
>>
>> @@ -247,7 +247,7 @@ define void @foo_sret(%struct.S* sret %a
>> ; CHECK-O0: ldr
>> ; CHECK-O0: ldr
>> ; CHECK-O0: str r{{.*}}, [{{.*}}, #4]
>> -; CHECK-O0: mov r6
>> +; CHECK-O0: mov r8
>> entry:
>> %call = call i8* @malloc(i64 16)
>> %call.0 = bitcast i8* %call to %swift_error*
>> @@ -263,22 +263,22 @@ entry:
>> define float @caller3(i8* %error_ref) {
>> ; CHECK-APPLE-LABEL: caller3:
>> ; CHECK-APPLE: mov [[ID:r[0-9]+]], r0
>> -; CHECK-APPLE: mov r6, #0
>> +; CHECK-APPLE: mov r8, #0
>> ; CHECK-APPLE: bl {{.*}}foo_sret
>> -; CHECK-APPLE: cmp r6, #0
>> +; CHECK-APPLE: cmp r8, #0
>> ; Access part of the error object and save it to error_ref
>> -; CHECK-APPLE: ldrbeq [[CODE:r[0-9]+]], [r6, #8]
>> +; CHECK-APPLE: ldrbeq [[CODE:r[0-9]+]], [r8, #8]
>> ; CHECK-APPLE: strbeq [[CODE]], [{{.*}}[[ID]]]
>> -; CHECK-APPLE: mov r0, r6
>> +; CHECK-APPLE: mov r0, r8
>> ; CHECK-APPLE: bl {{.*}}free
>>
>> ; CHECK-O0-LABEL: caller3:
>> -; CHECK-O0-DAG: mov r6, #0
>> +; CHECK-O0-DAG: mov r8, #0
>> ; CHECK-O0-DAG: mov r0
>> ; CHECK-O0-DAG: mov r1
>> ; CHECK-O0: bl {{.*}}foo_sret
>> -; CHECK-O0: mov [[ID2:r[0-9]+]], r6
>> -; CHECK-O0: cmp r6
>> +; CHECK-O0: mov [[ID2:r[0-9]+]], r8
>> +; CHECK-O0: cmp r8
>> ; CHECK-O0: str [[ID2]], [sp[[SLOT:.*]]]
>> ; CHECK-O0: bne
>> ; Access part of the error object and save it to error_ref
>> @@ -316,7 +316,7 @@ define float @foo_vararg(%swift_error**
>> ; CHECK-APPLE: mov [[REG:r[0-9]+]], r0
>> ; CHECK-APPLE: mov [[ID:r[0-9]+]], #1
>> ; CHECK-APPLE-DAG: strb [[ID]], [{{.*}}[[REG]], #8]
>> -; CHECK-APPLE-DAG: mov r6, [[REG]]
>> +; CHECK-APPLE-DAG: mov r8, [[REG]]
>>
>> entry:
>> %call = call i8* @malloc(i64 16)
>> @@ -345,13 +345,13 @@ entry:
>> define float @caller4(i8* %error_ref) {
>> ; CHECK-APPLE-LABEL: caller4:
>> ; CHECK-APPLE: mov [[ID:r[0-9]+]], r0
>> -; CHECK-APPLE: mov r6, #0
>> +; CHECK-APPLE: mov r8, #0
>> ; CHECK-APPLE: bl {{.*}}foo_vararg
>> -; CHECK-APPLE: cmp r6, #0
>> +; CHECK-APPLE: cmp r8, #0
>> ; Access part of the error object and save it to error_ref
>> -; CHECK-APPLE: ldrbeq [[CODE:r[0-9]+]], [r6, #8]
>> +; CHECK-APPLE: ldrbeq [[CODE:r[0-9]+]], [r8, #8]
>> ; CHECK-APPLE: strbeq [[CODE]], [{{.*}}[[ID]]]
>> -; CHECK-APPLE: mov r0, r6
>> +; CHECK-APPLE: mov r0, r8
>> ; CHECK-APPLE: bl {{.*}}free
>> entry:
>> %error_ptr_ref = alloca swifterror %swift_error*
>> @@ -396,51 +396,51 @@ entry:
>> }
>>
>> ; CHECK-APPLE-LABEL: swifterror_clobber
>> -; CHECK-APPLE: mov [[REG:r[0-9]+]], r6
>> +; CHECK-APPLE: mov [[REG:r[0-9]+]], r8
>> ; CHECK-APPLE: nop
>> -; CHECK-APPLE: mov r6, [[REG]]
>> +; CHECK-APPLE: mov r8, [[REG]]
>> define swiftcc void @swifterror_clobber(%swift_error** nocapture swifterror %err) {
>> - call void asm sideeffect "nop", "~{r6}"()
>> + call void asm sideeffect "nop", "~{r8}"()
>> ret void
>> }
>>
>> ; CHECK-APPLE-LABEL: swifterror_reg_clobber
>> -; CHECK-APPLE: push {{.*}}r6
>> +; CHECK-APPLE: push {{.*}}r8
>> ; CHECK-APPLE: nop
>> -; CHECK-APPLE: pop {{.*}}r6
>> +; CHECK-APPLE: pop {{.*}}r8
>> define swiftcc void @swifterror_reg_clobber(%swift_error** nocapture %err) {
>> - call void asm sideeffect "nop", "~{r6}"()
>> + call void asm sideeffect "nop", "~{r8}"()
>> ret void
>> }
>>
>> ; CHECK-ARMV7-LABEL: _params_in_reg
>> ; Store callee saved registers excluding swifterror.
>> -; CHECK-ARMV7: push {r4, r5, r7, r8, r10, r11, lr}
>> -; Store swiftself (r10) and swifterror (r6).
>> -; CHECK-ARMV7-DAG: str r6, [s[[STK1:.*]]]
>> +; CHECK-ARMV7: push {r4, r5, r6, r7, r10, r11, lr}
>> +; Store swiftself (r10) and swifterror (r8).
>> +; CHECK-ARMV7-DAG: str r8, [s[[STK1:.*]]]
>> ; CHECK-ARMV7-DAG: str r10, [s[[STK2:.*]]]
>> ; Store arguments.
>> -; CHECK-ARMV7: mov r4, r3
>> -; CHECK-ARMV7: mov r5, r2
>> -; CHECK-ARMV7: mov r8, r1
>> -; CHECK-ARMV7: mov r11, r0
>> +; CHECK-ARMV7: mov r6, r3
>> +; CHECK-ARMV7: mov r4, r2
>> +; CHECK-ARMV7: mov r11, r1
>> +; CHECK-ARMV7: mov r5, r0
>> ; Setup call.
>> ; CHECK-ARMV7: mov r0, #1
>> ; CHECK-ARMV7: mov r1, #2
>> ; CHECK-ARMV7: mov r2, #3
>> ; CHECK-ARMV7: mov r3, #4
>> ; CHECK-ARMV7: mov r10, #0
>> -; CHECK-ARMV7: mov r6, #0
>> +; CHECK-ARMV7: mov r8, #0
>> ; CHECK-ARMV7: bl _params_in_reg2
>> ; Restore original arguments.
>> ; CHECK-ARMV7-DAG: ldr r10, [s[[STK2]]]
>> -; CHECK-ARMV7-DAG: ldr r6, [s[[STK1]]]
>> -; CHECK-ARMV7: mov r0, r11
>> -; CHECK-ARMV7: mov r1, r8
>> -; CHECK-ARMV7: mov r2, r5
>> -; CHECK-ARMV7: mov r3, r4
>> +; CHECK-ARMV7-DAG: ldr r8, [s[[STK1]]]
>> +; CHECK-ARMV7: mov r0, r5
>> +; CHECK-ARMV7: mov r1, r11
>> +; CHECK-ARMV7: mov r2, r4
>> +; CHECK-ARMV7: mov r3, r6
>> ; CHECK-ARMV7: bl _params_in_reg2
>> -; CHECK-ARMV7: pop {r4, r5, r7, r8, r10, r11, pc}
>> +; CHECK-ARMV7: pop {r4, r5, r6, r7, r10, r11, pc}
>> define swiftcc void @params_in_reg(i32, i32, i32, i32, i8* swiftself, %swift_error** nocapture swifterror %err) {
>> %error_ptr_ref = alloca swifterror %swift_error*, align 8
>> store %swift_error* null, %swift_error** %error_ptr_ref
>> @@ -451,42 +451,42 @@ define swiftcc void @params_in_reg(i32,
>> declare swiftcc void @params_in_reg2(i32, i32, i32, i32, i8* swiftself, %swift_error** nocapture swifterror %err)
>>
>> ; CHECK-ARMV7-LABEL: params_and_return_in_reg
>> -; CHECK-ARMV7: push {r4, r5, r7, r8, r10, r11, lr}
>> +; CHECK-ARMV7: push {r4, r5, r6, r7, r10, r11, lr}
>> ; Store swifterror and swiftself
>> -; CHECK-ARMV7: mov r4, r6
>> +; CHECK-ARMV7: mov r6, r8
>> ; CHECK-ARMV7: str r10, [s[[STK1:.*]]]
>> ; Store arguments.
>> ; CHECK-ARMV7: str r3, [s[[STK2:.*]]]
>> -; CHECK-ARMV7: mov r5, r2
>> -; CHECK-ARMV7: mov r8, r1
>> -; CHECK-ARMV7: mov r11, r0
>> +; CHECK-ARMV7: mov r4, r2
>> +; CHECK-ARMV7: mov r11, r1
>> +; CHECK-ARMV7: mov r5, r0
>> ; Setup call.
>> ; CHECK-ARMV7: mov r0, #1
>> ; CHECK-ARMV7: mov r1, #2
>> ; CHECK-ARMV7: mov r2, #3
>> ; CHECK-ARMV7: mov r3, #4
>> ; CHECK-ARMV7: mov r10, #0
>> -; CHECK-ARMV7: mov r6, #0
>> +; CHECK-ARMV7: mov r8, #0
>> ; CHECK-ARMV7: bl _params_in_reg2
>> ; Restore original arguments.
>> ; CHECK-ARMV7: ldr r3, [s[[STK2]]]
>> ; CHECK-ARMV7: ldr r10, [s[[STK1]]]
>> ; Store %error_ptr_ref;
>> -; CHECK-ARMV7: str r6, [s[[STK3:.*]]]
>> +; CHECK-ARMV7: str r8, [s[[STK3:.*]]]
>> ; Restore original arguments.
>> -; CHECK-ARMV7: mov r0, r11
>> -; CHECK-ARMV7: mov r1, r8
>> -; CHECK-ARMV7: mov r2, r5
>> -; CHECK-ARMV7: mov r6, r4
>> +; CHECK-ARMV7: mov r0, r5
>> +; CHECK-ARMV7: mov r1, r11
>> +; CHECK-ARMV7: mov r2, r4
>> +; CHECK-ARMV7: mov r8, r6
>> ; CHECK-ARMV7: bl _params_and_return_in_reg2
>> ; Store swifterror return %err;
>> -; CHECK-ARMV7: str r6, [s[[STK1]]]
>> +; CHECK-ARMV7: str r8, [s[[STK1]]]
>> ; Load swifterror value %error_ptr_ref.
>> -; CHECK-ARMV7: ldr r6, [s[[STK3]]]
>> +; CHECK-ARMV7: ldr r8, [s[[STK3]]]
>> ; Save return values.
>> -; CHECK-ARMV7: mov r5, r0
>> -; CHECK-ARMV7: mov r4, r1
>> -; CHECK-ARMV7: mov r8, r2
>> +; CHECK-ARMV7: mov r4, r0
>> +; CHECK-ARMV7: mov r5, r1
>> +; CHECK-ARMV7: mov r6, r2
>> ; CHECK-ARMV7: mov r11, r3
>> ; Setup call.
>> ; CHECK-ARMV7: mov r0, #1
>> @@ -496,13 +496,13 @@ declare swiftcc void @params_in_reg2(i32
>> ; CHECK-ARMV7: mov r10, #0
>> ; CHECK-ARMV7: bl _params_in_reg2
>> ; Load swifterror %err;
>> -; CHECK-ARMV7: ldr r6, [s[[STK1]]]
>> +; CHECK-ARMV7: ldr r8, [s[[STK1]]]
>> ; Restore return values for returning.
>> -; CHECK-ARMV7: mov r0, r5
>> -; CHECK-ARMV7: mov r1, r4
>> -; CHECK-ARMV7: mov r2, r8
>> +; CHECK-ARMV7: mov r0, r4
>> +; CHECK-ARMV7: mov r1, r5
>> +; CHECK-ARMV7: mov r2, r6
>> ; CHECK-ARMV7: mov r3, r11
>> -; CHECK-ARMV7: pop {r4, r5, r7, r8, r10, r11, pc}
>> +; CHECK-ARMV7: pop {r4, r5, r6, r7, r10, r11, pc}
>> define swiftcc { i32, i32, i32, i32} @params_and_return_in_reg(i32, i32, i32, i32, i8* swiftself, %swift_error** nocapture swifterror %err) {
>> %error_ptr_ref = alloca swifterror %swift_error*, align 8
>> store %swift_error* null, %swift_error** %error_ptr_ref
>>
>>
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at lists.llvm.org
>> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at lists.llvm.org
> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits
More information about the llvm-commits
mailing list